JPH0421043A - One-chip cache memory - Google Patents

Abstract

PURPOSE:To obtain the highest hit rate, respectively in accordance with each application program by providing a pre-fetch number setting register for setting the number of pre-fetch blocks, and a pre-fetcher for executing the pre-fetch by the set number of times. CONSTITUTION:A second set select is obtained by incrementing a first set select in an access address. Subsequently, by a second set select, a cache memory access is executed, whether it is a hit or a miss is decided, and a pre-fetcher 10 for fetching data from a main memory at the time when a miss is decided, and a pre-fetch setting register 11 for setting the number of times of incrementing a second set select are provided. Accordingly, the number of pre- fetch blocks can be set optimumly in accordance with an application program. In such a way, the highest hit rate is obtained at every application program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fetch method for a one-chip cache memory.

[Conventional technology]

Figure 2 shows the conventional 1-chip cache memory μPD43.
608R is a block diagram showing the overall structure of the memory block in 608R.
This is an excerpt from 57). In addition, FIG. 3 shows the one-chip cache memory μPD43608R shown in FIG.
FIG. 2 is a diagram showing the configuration of a memory block in FIG.

In FIG. 2, 2 is a CPU address, 3 is CPU data, 4 is a data block, 5 is a directory, 6 is a block address generator, 7 is an input latch, 8 is a block load buffer, 9 is a bypass buffer, 10 is a prefetcher, 12 is a system bus interface;
13 is a CPU bus interface, and 14 is an LRU.

Next, the operation of the entire one-chip cache memory block will be explained.

The 1-chip cache memory stores data in the main memory in response to requests from the CPU, and reads/writes the data at high speed in place of the main memory when accessed by the CPU.

Memory access from the CPU has locality, and the CPU
Data stored in cache memory upon request from
There is a high possibility that the accessed data will be accessed again in the near future, and there is also a high possibility that data in the vicinity of the accessed data will be accessed again).

Therefore, by storing data once accessed and data in the vicinity thereof in the cache memory, high-speed memory access by the CPU can be easily achieved. When the CPU accesses one chip memory, if data exists, it is said to be a hit, and if it does not, it is called a hit.

In the case of cache data, data is read from the cache memory at high speed. In case of cache miss, CPU
The data block including the word requested by the cache memory G is fetched from the main memory (fetch operation) in preparation for the next CPU access.

Here, a block of data that is a unit of information transfer between the cache memory and the main memory is called a block, and its size is called a block size.

The operation of the cache memory during this information transfer is to eject one of the existing old blocks (replace operation) if there is no free space in the cache memory to store the block.

Next, the memory configuration and operation of a conventional one-chip cache memory will be explained. FIG. 3 shows a four-way set associative memory configuration consisting of three blocks: data block 4, directory 5, and LRU 14. The data block 4 is a memory section that holds data in the main memory. The directory 5 includes an address tag, which is a storage location for an address corresponding to each data block, and a valid bit, which indicates whether the stored data is valid or invalid.

The LRU 14 stores information on how old each 4-way data was accessed from the CPU.

The CPU accesses using addresses within the memory block.

As shown in FIG. 3, it is divided into three parts: access address tag, set select, and word select. By selecting the access address, the address tag and valid bit are selected and read from the directory. Similarly, a block is selected from the data blocks and read out.

Here, we will discuss the four-step associative method. Generally, the address tag, which is the upper part of the access address, is compared with the contents of the address tag part in the directory selected by set select. Therefore, in the above method, up to four address tags are simultaneously stored for one send select. Therefore, Hi-nod/
When a mistake is determined, four address tags are simultaneously referenced and compared for a certain set selection. In addition, the no-read bit indicates the validity of each stored address tag, and checks whether it is valid or not when determining a hit/miss.The four ways perform the same operation in parallel and are read from the directory. The address tag of the access address is compared with the address tag part of the access address in all four ways at the same time to determine whether it is a hit or a miss.

On the other hand, in the read data block, a word is selected by word select, and finally a way selection signal indicating which way was hit is received from the hint judgment.
One word is determined.

Next, the fetch method will be explained. The 1-chip cache memory supports on-demand and prefetch-on-miss algorithms.

In the on-demand method, the contents of the main memory are fetched into the one-knob cache memory in units of programs when a certain block is needed (when a cache miss occurs).

On the other hand, in the prefetch-on-miss method, after fetching the block accessed when a cache miss occurs, a cache miss of the next block in the accessed block is checked.

If the next block is a cache miss, that block is also fetched.

Generally, the hit rate is used to indicate the performance of cache memory. The hit rate is the probability that the accessed data exists in the cache memory when the CPU accesses the memory.

[Problem to be solved by the invention]

Since the conventional one-chip cache memory is configured as described above, the number of blocks to be prefetched is fixed at one, but the effect of the number of prefetches on improving the hit rate varies depending on the application. For application programs with high address continuity of data, increasing the number of prefetching can obtain a high hit rate.
If the data addresses are discrete, the hit rate will not improve even if the number of prefetches is increased. If the number of prefetch is fixed, it cannot be expected to obtain a high hit rate for all application programs.

Therefore, in order to maximize system performance, it is necessary to select the number of prefetch blocks that will yield a high hit rate in accordance with the application program.

The present invention was made to solve the above-mentioned problems, and its object is to obtain an l-chip cache memory that can obtain the highest hit rate depending on the application program.

[Means to solve the problem]

The one-chip cache memory according to the present invention includes a prefetch number setting register that sets the number of prefetch blocks, and a prefetcher that executes prefetching a set number of times.

(Operation) In the present invention, a high hit rate can be obtained by optimally setting the number of prefetch blocks in accordance with the application program.

[Example〕 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram of a one-chip cache memory according to one embodiment of the present invention.

In the figure, 1 is a 1-chip cache memory, 2 is a CP
U address, 3 is CPU data, 4 is data block,
5 is a directory, 6 is a file address generator, 7 is an input latch, 8 is a block load buffer,
9 is a bypass buffer, 10 is a brief fetcher, 11 is a prefetch number setting register, 12 is a system bus interface, 13 is a CPU bus interface, 1
4 is LRU.

Next, a read access operation of the one-chip cache memory 1 will be explained. 1-chip cache memory 1 is C
The directory 5 and block load buffer 8 are referred to using the PU address 2, and if a cache hit is made here, data from the data block 4 is output to the CPU data bus 3.

Here, the reason for referring to the block load buffer 8 will be described. This is because the data is written to the data block 4 when one block of data is collected in the block load buffer 8, so even if there is no data in the data block 4, there is a possibility that the data exists in the block load buffer 8.

If there is a cache miss, system bus interface 1
2 to request the use of the memory bus, and when the use of the memory bus is permitted, bus access is started and data is fetched from the main memory using the address generated by the block address generator 6. Fetch data from main memory is passed from input latch 7 to block load buffer 8 and bypass buffer 9. The bypass buffer 9 outputs the data to the CPU data bus 3, and the CPU
Notify the data output completion. When the block load buffer 8 completes data fetching for l blocks, it updates the cache data using the address generated by the block address generator 6. Also, while accessing the memory bus, the prefetcher 10 refers to the next block in the directory 50. .

If it is a cache hit, nothing is done, but if it is a cache miss, a bus usage request is issued to the system bus interface 12 and the next block is fetched. This prefetch is performed the number of times set in the prefetch block number setting register 11. Finally, the cache-missed block and the following blocks corresponding to the set number of prefetch blocks are fetched and written to the data block. After the prefetch is completed, the one-chip cache memory is again in a state where it accepts accesses, and accepts read accesses and write accesses.

Note that the setting of the prefetch number setting register 11 is performed at the time of internal register setting after reset.

It is also possible to adopt a configuration in which the prefetch number is set by a signal externally applied to a signal bin of a single-chip cache memory without using a prefetch setting register. In this way, there is no need for the program to set the prefetch block setting register when initializing the 1-chip cache memory, so a program without a 1-chip cache memory can be used without modification.

[Effects of the Invention] As described above, according to the one-chip cache memory according to the present invention, a prefetch number setting register for setting the number of prefetch blocks is provided, as well as a prefetcher for executing prefetch a set number of times. This has the effect of obtaining the highest hit rate for each application program.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a 1-chip memory according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional 1-chip cache memory, and FIG. 3 is a memory configuration of a single-chip memory shown in FIG. 2. It is a diagram. In the figure, 1 is a 1-chip cache memory, 2 is a CP
U address, 3 is CPU data, 4 is data block,
5 is a directory, 6 is a block address generator, 7 is an input latch, 8 is a block load buffer, 9 is a bypass buffer, 10 is a prefetcher, 11 is a prefetch number setting register, 12 is a system bus interface, 13 is a CPU bus interface, 14 is LRU. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a one-chip cache memory having means for holding an access address of a CPU and means for incrementing a first set select in the access address to obtain a second set select, the second set select A prefetcher that performs cache memory access, determines whether it is a hit or a miss, and fetches data from the main memory when a miss is determined, and a prefetch number setting register that sets the number of times the second set select is incremented. A one-chip cache memory characterized by: