JPH04211178A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the performance of a laminated gate type nonvolatile memory cell by increasing the controllability of the P-type impurity concentration profile in the peripheral area of a drain or source area on the channel side. CONSTITUTION:After laminated gate electrodes are formed, an area having a high concentration of a first conductivity type impurity is formed in the vicinity of the boundary between the source or drain area of the transistor having the said laminated gate and a second conductivity type diffusion layer by implanting the ions of a first conductivity type impurity into a semiconductor substrate at an angle of >=8 deg. against the normal line to the substrate.

Description

[Detailed description of the invention] [00011

FIELD OF INDUSTRIAL APPLICATION The present invention relates to a method for manufacturing a semiconductor device, and is used in manufacturing a nonvolatile semiconductor memory, particularly for forming a floating gate type memory cell. BACKGROUND OF THE INVENTION In recent years, as non-volatile memories have become larger in storage capacity, miniaturization of memory cells and reduction in data writing time have become issues. To solve these problems, DSA (Diffusion Self-A) is an approach from the memory cell structure.
ligated) structure has been proposed. Figure 12 shows the DSA
A nonvolatile memory cell is shown to explain the structure, and 11 is a P-type silicon substrate, 12 is an isolation oxide film, and 13 is a nonvolatile memory cell.
a is a source region (N-type impurity region), 13b is a drain region (N-type impurity region), 14 is a floating gate, 15 is a control gate, 16 is a P-type impurity region, 17 is a channel region, 18 is a gate insulating film, 19 is a polysilicon interlayer insulating film. That is, in the DSA structure, as shown in FIG.
A P-type impurity region 16 (abbreviated as P pocket) having a higher concentration than the center of the channel region 17 is formed around the channel region 17,
The purpose is to increase the electric field strength in the channel region near the train during writing, thereby increasing the gate injection current. In particular, regarding the punch-through breakdown voltage of cell transistors, there is a problem unique to floating gate cell transistors. This is because when a floating gate field effect transistor is used in a cell, as voltage is applied to the train, the potential of the floating gate floats due to capacitive coupling between the floating gate and the train, so the cell transistor becomes even more Punch-through is easier compared to gate-type transistors. This tendency becomes more pronounced as the gate length of the transistor becomes shorter, so this is a problem that must be solved first when attempting to reduce the cell transistor size. By forming the P-pocket 16, the expansion of the depletion region is suppressed, and the punch-through breakdown voltage of the cell transistor is improved, which is advantageous for downsizing the cell. [00031] From the above, when a DSA structure is used in a floating gate memory cell transistor, it has the advantages of improved writing speed and stronger punch-through resistance, and has become an indispensable technology for large-capacity non-volatile memory. sell. [0004]

Problems to be Solved by the Invention Now, in order to form a DSA structure in an N-channel cell transistor and fully exhibit its intended function, it is necessary to improve the P-pocket region near the drain end of the floating gate. The impurity concentration profile is important. In order to improve the punch-through voltage and write speed of cell transistors,
It is necessary to make the impurity concentration of the P-pocket region near the drain end sufficiently higher than that of the channel region. However, since the P pocket region is formed by ion-implanting P type impurities after forming the stacked gate electrode, the following problem occurs. Since the drain end is covered with a stacked gate, in order to prevent channeling (preventing ions from being implanted deeply from the path that they easily pass), when ions are implanted using conventional ion implantation methods, the normal direction of the substrate is Since the angle between the two electrodes is as small as 7 degrees at most, it is impossible to directly implant sufficient P-type impurities into the vicinity of the drain end under the floating gate. Therefore, as a practical method, ion implantation is performed to form a P-pocket region, and a thermal process such as annealing is applied to diffuse the P-type impurity from the region that will become the train end to the channel side, and then the source/drain region is The method is to perform ion implantation to form the structure. For this reason, D
When attempting to introduce a P-pocket in the SA structure, one additional thermal process is required, and because of this thermal process, the two ion implantations cannot be performed simultaneously, and the number of patterning processes using a mask is also increased by one. be. If a P-pocket region is formed by such diffusion, the controllability of the impurity concentration profile is insufficient, and it is difficult to obtain a sufficiently high P-type impurity concentration near the drain end. Another drawback is that the channel impurity concentration profile is greatly affected by the thermal process for forming the P-pocket region. Furthermore, in order to sufficiently thermally diffuse the P-type impurity in the lateral direction to form the P-pocket region and to maintain a high concentration of the P-type impurity in this diffused region, the dose profile of ion implantation must be made considerably large. However, this causes problems such as an increase in junction capacitance and a deterioration in junction breakdown voltage. The junction breakdown voltage is determined by the pn junction breakdown voltage formed between the region of the P-pocket region, which overlaps with the channel stopper region under the element isolation region and has a higher concentration of P-type impurities, and the N region of the source/drain. Therefore, the junction breakdown voltage is greatly affected by the impurity concentration distribution in this area. [0005] Therefore, an object of the present invention is to provide a semiconductor that can increase the controllability of the P-type impurity concentration profile and improve the performance in the peripheral region on the channel side of the train or source region in a stacked gate nonvolatile memory cell. An object of the present invention is to provide a method for manufacturing a device. [0006]

[Means and effects for solving the problems] The present invention has [00
07] (1) A step of providing a floating gate electrode via an insulating film on the region where a channel of the first conductivity type is to be formed and laminating a control gate electrode on this gate electrode, and forming each of the laminated gate electrodes. After that, impurities of the first conductivity type are ion-implanted at an angle of 8 degrees or more with respect to the normal to the semiconductor substrate surface,
A method for manufacturing a semiconductor device, comprising the step of forming a region with a high impurity concentration of the first conductivity type near the boundary of the second conductivity type diffusion layer that becomes a train of the transistor having the stacked gate electrodes. be. The present invention also provides (
2) The method for manufacturing a semiconductor device according to (1) above, wherein the ion implantation is performed at an angle of 60 degrees or less with respect to a normal to the semiconductor substrate. [0008] That is, in order to achieve the above object, the present invention rotates the substrate appropriately during impurity ion implantation for forming the P-pocket region, and specifically rotates the stacked gate with respect to the normal to the substrate. At least 8 degrees or more, 6 degrees to the side of the
Ions are implanted at an angle of less than 0 degrees to increase the impurity concentration in the pocket region near the end of the train under the floating gate. By changing the implantation angle, the impurity concentration profile in this region is controlled, and the writing characteristics are improved and the short channel effect is suppressed at the same time. [0009] The reason why the ion implantation direction is set to 8 degrees or more and 60 degrees or less is that if the conventional ion implantation direction is 7 degrees or less, the effect of increasing the impurity concentration in the pocket region near the end of the train under the floating gate is extremely small. However, the reason for setting it below 60 degrees is that around 8 degrees is the starting point for improvement compared to before.
This is because if the angle is larger than this, the angle becomes too large and it becomes difficult to properly implant ions into the substrate. In the present invention, since ions are implanted at an angle of 8 degrees or more, the above-mentioned channeling problem occurs, but the problem does not occur because deep ion implantation is performed. [00101

[Embodiment] A method for manufacturing an EPROM cell transistor, which is an embodiment of the present invention, will be explained using FIGS. 1 to 6, taking an N-channel type transistor as an example. For example, by a well-known technique, a field insulating film 22 and a channel stopper region 23 are formed on the surface of a P-type silicon substrate 21 to perform element isolation. Next, a gate insulating film 24 having a thickness of, for example, about 20 nm is formed on the surface of the silicon substrate 21 by thermal oxidation. The normal process is
After forming the gate insulating film 24, P-type impurity ions are implanted into the channel region to adjust the threshold value of the cell transistor.According to the present invention, the threshold value of the cell transistor is adjusted to the P pocket ion implantation conditions. In this embodiment, the channel region is formed only with the P-type impurity in the P-type silicon substrate 21, and the P-type impurity is added to increase the concentration. No ion implantation is performed. Next, a phosphorus-doped polycrystalline silicon layer 25, which will be the material of the floating gate, is formed. Thereafter, a thermal oxide film 26 having a thickness of, for example, about 20 nm is formed on this polycrystalline silicon layer 25 by thermal oxidation. Subsequently, a second phosphorus-doped polycrystalline silicon layer 27 is formed on this oxide film 26 to be a material for a control gate electrode (see FIG. 1). [00121] Next, the second phosphorus-doped polycrystalline silicon layer 27, the thermal oxide film 26, and the first phosphorus-doped polycrystalline silicon layer 25 are sequentially patterned to form the control gate electrode 27.
, a stacked gate electrode consisting of a second gate insulating film 26 and a floating gate electrode 25 is formed. After that, thermal oxidation is performed to form a post-oxidation film 31 on the stacked gate and substrate surface (Fig. 2
reference). [0013] Next, ion implantation of P-type impurities is performed in a self-aligned manner using the stacked gate as a mask, and the source and
A P-type ion implantation layer 32 is placed near the part where the train region is planned to be formed.
a, 32b are formed. In this ion implantation, for example, the silicon substrate 21 is rotated at least once per minute, and boron ions are implanted at a dose of 5×10 12 cm −2 or more at an angle of 10°≦θ≦45° with respect to the normal line 33 of the substrate. (Figure 32
(See Figure 4). In this case, the ion-implanted impurity may be implanted at a concentration higher than the center of the channel region of the cell transistor and lower than the impurity concentration of the train region of the cell transistor. This ion implantation may be performed by a semiconductor device manufacturing method performed under conditions determined by the following equation. X-tanθ ≧ X [0014] However, here, The angle of ion implantation, X, is the distance that the end of the drain or source extends by diffusion in the direction of the channel under the stacked gate from after ion implantation to the final process (FIG. 7).
reference). That is, the product of the distance X from the substrate surface of the average range of the P-type impurity implanted by the above-mentioned ion implantation and tanθ, that is, in this example, the distance of the P-type impurity entering under the floating gate in the channel direction is: If the drain end is larger than the distance X that the drain end diffuses into below the floating gate, the P-pocket concentration at the train end can be made sufficiently high, and the effect of the P-pocket can be exhibited. Also, the depth X of ion implantation at this time is approximately the same as the junction depth X of the train diffusion layer (width X
/2 ≦ The effect will be greater. If the implantation is too shallow, the P-type impurity will be sucked out into the upper oxide film by a later thermal process such as oxidation, which is not effective. [0015] FIG. 11 shows the dependence of the punch-through characteristic on the implantation angle θ when X = 0.20 μm, X approximately 0.16 μm, and X = 0.30 μm. In this case, according to the above formula, it is predicted that the P pocket becomes effective when θ>28° or more. What can be seen from this Figure 11 is that
When θ=0°, θ=15°, i.e., less than 28°, the punch-through withstand voltage drops sharply when the floating gate length is less than 0.6 μm, but when θ=30°, i.e., 28° or more, the punch-through withstand voltage is improved. is large, and a sufficient value is obtained up to L=0.5 μm. However, in the present invention, θ-8
As mentioned above, it can be put to practical use even when θ=60° or more, and it can still be put to practical use even when θ=60° or less. [00161 Figure 32 In Figure 4, 34 and 36 are P-type impurity ion beams, 35 are P-type impurity ions that enter from the stacked gate sidewalls, 36a and 36b are P-type impurity ions that enter from the field edge ends, and 21 is a rotating silicon substrate. represents. [00171]N-type impurity ions are then implanted in a self-aligned manner using the stacked gate as a mask to form N-type ion implantation layers 39a and 39b. This ion implantation
Ion implantation is performed parallel to the side surface of the stacked gate (at 7 degrees to the normal to the substrate surface). For example, arsenic 5x
Ion implantation is performed under the condition of 1015 cm-2 (see Figure 5).
. In FIG. 5, 38 represents an N-type impurity ion beam. [00181] Next, a thermal process, for example, annealing at 900° C., is performed to activate the ion-implanted impurities and to recover the damage to the oxide film 24, 31 caused by the two ion implantations. At this time, the P-type ion implantation layer 32a. 32b forms P-pocket regions 40a, 40b;
The N-type ion implantation layers 39a and 39b form source/drain regions 41a and 41b. After this, normal M
An interlayer insulating film 42 is formed according to a method for manufacturing an O8 integrated circuit. Next, a part of the interlayer insulating film 42 above the source train regions 41a and 41b is opened to form a contact hole 43, and then an AI electrode 44 is formed, and the EPROM
The cell is completed (see Figure 6). In FIG. 6, 45 is P
The area where the pocket area and channel stopper area overlap,
46 represents a channel region. [0019] According to the above method for manufacturing an EPROM cell transistor, the P-type impurity concentration in the P-pocket region near the end of the drain region, which is important in the DSA structure, can be increased, and as a result, the write efficiency of the cell can be increased. improved,
It becomes easier to miniaturize cells and increase their integration.

FIG. 7 shows a cross section near the drain end of the cell formed in the above embodiment. The P-pocket region indicated by a dotted line in FIG. 7 is the case where the conventional ion implantation method was used to form the P-pocket region in the above embodiment. In FIG. 7, X is the junction depth of the train 41b, and X is the distance that the drain end extends by diffusion in the channel direction under the floating gate 25 from after ion implantation to the final process. FIG. 8 shows a specific impurity concentration distribution in the AA' cross section of FIG. 7. The boron concentration shown by the dotted line is P in the above example.
- In the pocket region formation, a conventional ion implantation method is used. [00211 (a) With this method, the concentration of the P-pocket region 40b near the floating gate 25 can be made sufficiently higher than that of the channel region 46, the electric field strength near the drain region 41b increases, and the amount of hot electrons generated increases. Therefore, the write efficiency of memory cells is improved. [0022] (b) According to the above (a), the pn junction between the source or drain region and the P-pocket region can be configured with a high impurity concentration, and the extension of the depletion region can be suppressed.
A sufficient effective channel length of the cell transistor can be ensured, and short channel effects can be suppressed. [0023] (c) With the above (a) and (b), the threshold value of the cell transistor can be controlled only by the P-pocket region,
Ion implantation used to form a channel of a cell transistor can be omitted. [0024] (d) With this method, in the P-type impurity concentration profile of the P-pocket region, the portion that affects the write efficiency of the memory cell, that is, the vicinity of the drain side edge under the gate 25, and the portion that affects the short channel effect, that is, Since the area near the bottom of the train under the gate 25 can be controlled independently (for example, by performing ion implantation twice at different acceleration voltages and angles), it is possible to flexibly deal with changes in the cell structure and changes in the thermal process after cell transistor formation. becomes possible. (e) This method makes it possible to omit the thermal step required to form the P-pocket region using conventional ion implantation methods. [0025] (F) According to (E) above, ion implantation for forming the P-pocket region of the cell transistor and ion implantation for forming the source/drain region can be performed simultaneously, and patterning using a mask can be performed. The number of processes can be reduced. (g) By this method, a portion 4 where the channel stopper region 23 and the P-pocket region under the element isolation region 22 overlap
5, in the portion 45 where the P-pocket regions overlap, the P-
The P-type impurity ions forming the pockets are transmitted and scattered at the field edge, so that they have a slow profile deep from the substrate surface. In addition, when rotating the wafer and performing oblique ion implantation into the P-pocket, the number of P-type impurity ions implanted below the field edge is, for example, in the P-pocket region of layer 32b. The concentration of P-type impurities in the overlapping portion 45 of the P-pocket 36b and the channel stopper 22 is reduced due to the effect that the impurity ion concentration is maximum in the direction of the directional impurity ion 36b, but is hardly implanted in the direction of the 180° opposite direction 36a. It turns out. (See Figure 3) Because of these effects, the p-n junction formed in the above portion has a p
Compared to an n-junction, the p-n junction has an improved breakdown voltage due to the effect of reducing the concentration of P-type impurities near the junction and the effect of relaxing the concentration gradient. [0026] Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the embodiment described above, the P-pocket region was formed to cover the source/drain region (see FIG. 6). 9. It is clear that a P-pocket region as shown in FIG. 10 may be partially formed near the drain. Further, in the above embodiment, a case has been described in which the P-pocket layer is formed on both the train and source sides, but it is clear that it may be formed only on the drain side using a mask process. Further, although the description has been made regarding an N-channel type cell, the same applies to a P-channel type cell. [0027]

【Effect of the invention】

(1) According to the present invention, the concentration of the P-pocket region near the floating gate can be made sufficiently higher than that of the channel region, the electric field strength near the drain region increases, the amount of hot electrons generated increases, and the concentration of the P-pocket region near the floating gate increases. Increased efficiency. [0028] (2) According to (1) above, the pn junction between the source or drain region and the P-pocket region can be formed with a high impurity concentration, and the elongation of the depletion region can be suppressed, so that the effective efficiency of the cell transistor can be reduced. A sufficient channel length can be ensured and short channel effects can be suppressed. [0029] (3) According to (1) and (2) above, the cell transistor can operate only in the P-pocket region, and the ion implantation used to form the channel of the cell transistor can be omitted.

(4) According to the present invention, in the P-type impurity concentration profile of the P-pocket region, it is possible to independently control the part that affects the write efficiency of the memory cell and the part that affects the short channel effect. It becomes possible to flexibly deal with changes in structure and changes in thermal process after cell transistor formation. (5) According to the present invention, it is possible to omit the thermal process required to form the P-pocket region using the conventional ion implantation method. [00311 (6) According to (5) above, ion implantation for forming the P-pocket region of the cell transistor and ion implantation for forming the source/drain region can be performed simultaneously, and the patterning process using a mask can be performed. can be reduced. [0032] (7) According to the present invention, in the portion where the channel stopper region and the P-pocket region under the element isolation region overlap, the P-type impurity ions forming the P-pocket are transmitted and scattered at the field edge, and the substrate surface It has a slow profile from deep to deep. Furthermore, when performing oblique ion implantation of the P-pocket by rotating the wafer, the number of P-type impurity ions implanted below the field edge is reduced. For this reason, the pn junction formed in the above portion has the effect of reducing the concentration of P-type impurities near the junction and the effect of easing the concentration gradient, compared to a pn junction where a P-pocket is formed by conventional ion implantation. The withstand voltage of the pn junction can be improved.

[Brief explanation of the drawing]

FIG. 1 is a process diagram of an embodiment of the present invention.

FIG. 2 is a process diagram of the same example.

FIG. 3 is a process diagram of the same example.

FIG. 4 is a process diagram of the same example.

FIG. 5 is a process diagram of the same example.

FIG. 6 is a process diagram of the same example.

FIG. 7 is a cross-sectional view of the vicinity of the drain.

FIG. 8 is a diagram showing an impurity concentration profile in FIG. 7.

FIG. 9 is a sectional view of a main part of a different embodiment of the present invention.

FIG. 10 is a sectional view of a main part of a different embodiment of the present invention.

FIG. 11 is a diagram showing punch-through breakdown voltage characteristics of a cell transistor.

FIG. 12 is a cross-sectional view of a conventional nonvolatile memory cell.

[Explanation of symbols]

21... P-type substrate, 22... Field insulating film, 2
3... Channel stopper, 24.29... Gate insulating film, 25... Floating gate electrode (polysilicon), 2
6... Oxide film, 27... Control gate electrode (polysilicon), 31... Post oxide film, 32a, 32b-P type ion implantation layer, 39a, 39b-N type ion implantation layer, 40
a, 40b...P-pocket region, 41a, 41b.
... Source train, 42... Interlayer insulating film, 43.
...Contact hole, 44...AI electrode, 45...
- P region type portion, 46...channel region.

[Figure 1]

[Figure 2]

[Figure 3]

[Figure 4]

[Figure 7]

[Figure 5]

[Figure 6]

[Figure 8]

[Figure 9]

[Figure 10]

[Figure 11]

[Figure 12]

Claims (9)

[Claims] 1. A step of providing a floating gate electrode on a region where a channel of a first conductivity type is to be formed via an insulating film, and laminating a control gate electrode on the gate electrode with an insulating film interposed therebetween; After forming each gate electrode, impurities of the first conductivity type are ion-implanted at an angle of 8 degrees or more with respect to the normal to the semiconductor substrate surface, and a second conductivity type impurity is implanted at an angle of 8 degrees or more to the normal to the semiconductor substrate surface to form a second conductivity type impurity, which becomes the drain of the transistor having the stacked gate electrodes. 1. A method of manufacturing a semiconductor device, comprising: forming a region with a high impurity concentration of a first conductivity type near a boundary of a conductivity type diffusion layer. 2. The semiconductor device according to claim 1, wherein a region with a high impurity concentration of the first conductivity type is formed not only at the drain of the transistor but also near the boundary of the second conductivity type diffusion layer which becomes the source. manufacturing method. 3. The impurity according to claim 1, further comprising the step of implanting the impurity at a concentration higher than the center of the channel region of the transistor and lower than the impurity concentration of the train region of the transistor. A method of manufacturing the semiconductor device described above. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation is performed by continuously rotating the substrate. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation is performed by intermittently rotating the substrate. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation is performed at an angle of 60 degrees or less with respect to a normal to the semiconductor substrate. 7. The semiconductor device according to claim 1, wherein the ion implantation at an angle of 8 degrees or more is performed simultaneously with ion implantation for forming a source and a drain of the transistor. Production method. 8. The ion implantation according to claim 1 or 2, wherein the ion implantation is performed under conditions determined by the following formula.
A method for manufacturing a semiconductor device according to . X-tanθ ≧ The angle, X, is the distance that the end of the train or source extends by diffusion in the direction of the channel under the stacked gate after ion implantation until the final step. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation includes an ion implantation step in which X satisfies the following conditions. X /2 ≦ X ≦ 2X where X is the distance from the substrate surface of the average range of the first conductivity type impurity ion-implanted in the ion implantation, and X is the junction depth of the drain diffusion layer. .