JPH04211533A - High speed line terminating circuit - Google Patents

Abstract

PURPOSE:To detect the abnormality of the device itself as well as the abnormality of a high speed line. CONSTITUTION:A transmission signal formed to be transmitted to a high speed line by imparting transmission frame synchronizing signal to transmission data in a multipleing circuit 12, is multiplexed with a reception signal from the high speed line in a multiplexing circuit 15. A frame synchronizing circuit is synchronized with both the multiplexed receiving signal and a transmission signal, and when either of these frame synchronizations is stepped-out, outputted a reception frame synchronization stepping-out signal B or a transmission frame synchronization stepping-out signal C. A separation circuit 18 separates the receiving data and the transmission data from the multiplexed reception signal and transmission signal and outputs them. The separated transmission data are collated with the transmission data inputted to the multiplexing circuit 12 in a pattern collating circuit 19, and when incoincidence is detected, a transmission data incoincidence signal N is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed line termination circuit, and more particularly to a high-speed line termination circuit used as a high-speed interface in a multiplexer of a data transmission system.

0002

2. Description of the Related Art A multiplexing device in a data transmission system performs mutual conversion between data transmitted by a plurality of low-speed lines and data transmitted by a plurality of high-speed lines. Data from each low-speed line is received by a low-speed line termination circuit corresponding to each low-speed line, and is input to a multiplexing/demultiplexing circuit. Data input from each low-speed line termination circuit to the multiplexing/demultiplexing circuit is rearranged and sent to each high-speed line by each high-speed line termination circuit corresponding to each high-speed line. On the other hand, data from each high-speed line is received by each high-speed line termination circuit and input to the multiplexing/demultiplexing circuit. The data input from each high-speed line termination circuit to the multiplexing/demultiplexing circuit is rearranged and processed by each low-speed line termination circuit corresponding to each low-speed line.
Sent to each low-speed line.

[0003] A high-speed line termination circuit receives transmission data to be sent to a corresponding high-speed line from a multiplexing/demultiplexing circuit, multiplexes a transmission frame synchronization signal with this transmission data, and generates a multiplexed signal of the transmission data and the transmission frame synchronization signal. The transmission signal is sent to the corresponding high-speed line. In addition, the high-speed line termination circuit receives a received signal, which is a multiplexed signal of received data and a received frame synchronization signal, from the corresponding high-speed line, removes the received frame synchronization signal from this received signal, and multiplexes and separates the received data. send to the circuit.

[0004] In order to remove the received frame synchronization signal from the received signal, timing information of the received frame synchronization signal is required. In order to obtain this timing information, the high-speed line termination circuit is equipped with a frame synchronization circuit that performs frame synchronization with the received signal. The frame synchronization circuit also plays the role of monitoring received signals from the high-speed line to detect abnormalities in the high-speed line. In other words, the frame synchronization circuit is
When frame synchronization cannot be achieved with the received signal, a frame synchronization loss signal is output to notify an abnormality in the high-speed line. This frame out-of-frame signal is used as a trigger to switch the abnormal high-speed line and the corresponding high-speed line termination circuit to the spare high-speed line and the corresponding spare high-speed line termination circuit.

[0005]

The conventional high-speed line termination circuit described above does not have a function to detect abnormalities in itself. Therefore, the conventional high-speed line termination circuit may not be able to correctly switch to the standby circuit when its own abnormality occurs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a high-speed line termination circuit that can detect not only abnormalities in the corresponding high-speed line but also abnormalities in itself.

[0007]

[Means for Solving the Problems] A high-speed line termination circuit of the present invention includes means for adding a transmission frame synchronization signal to data to be transmitted, and communication of the data to be transmitted to which the transmission frame synchronization signal has been added. A means of transmitting it to the line,
means for receiving a signal from the communication line; and means for multiplexing the received signal and the data to be transmitted to which the transmission frame synchronization signal has been added to create a multiplexed signal;
means for processing the multiplexed signal to output data contained in the received signal; means for separating the data to be transmitted contained in the multiplexed signal from the multiplexed signal; and means for comparing the data to be transmitted and the data to be transmitted obtained from the separating means to detect a mismatch between the two data.

[0008] The high-speed line termination circuit of the present invention may also include means for detecting an out-of-frame synchronization in data to be transmitted to which the transmission frame synchronization signal has been added from the multiplexed signal; , may include means for creating a signal indicating frame synchronization of the received signal from the multiplexed signal and supplying it to the processing means; The method may further include means for generating data in a predetermined pattern, and adding the data in the pattern to the data to be transmitted to which the transmission frame synchronization signal has been added. means for supplying the transmission frame synchronization signal to the means for creating the multiplexed signal in place of the attached data to be transmitted; and generating the pattern data from the multiplexed signal attached with the pattern data. The method may include extracting means, and means for comparing the pattern data from the generating means and the pattern data from the extracting means to detect a mismatch between the two data.

The detecting means may include means for adjusting the phases of the two data, the detecting means may include means for adjusting the phases of the two data, and the sending means may include a line. The receiving means may include a line receiver.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, in a high-speed line termination circuit 10 which is a first embodiment of the present invention, transmission data outputted by a multiplexing/demultiplexing circuit of a multiplexing device of a data transmission system to be sent to a high-speed line is processed. The first multiplex circuit 12 receives,
The transmission frame synchronization signal F2 is multiplexed with the transmission data and sent to the high-speed line, the second multiplexing circuit 15 receives the signal received from the high-speed line, and the separation circuit 17 removes the reception frame synchronization signal from the reception signal and receives it. Output the data to the multiplexing/separating circuit of the multiplexer.

Transmission data input to the high-speed line termination circuit 10 is framed. The frame generation circuit 11 is
Transmission frame synchronization signal F2 at the frame period of transmission data
occurs. The first multiplexing circuit 12 multiplexes the transmission frame synchronization signal F2 generated by the frame generation circuit 11 with the input transmission data, and outputs it to the line driver 1 as a transmission signal.
Output to 3. The line driver 13 is a known circuit that sends the transmission signal from the multiplex circuit 12 to a high-speed line.

The line receiver 14 has a known circuit configuration, equalizes the signal from the high-speed line, and converts the signal (received signal) in which the received data and the received frame synchronization signal are multiplexed into a second signal.
The output signal is output to the multiplex circuit 15. The second multiplex circuit 15 receives the transmission signal from the first multiplex circuit 12 and the line receiver 14.
The multiplexed received signals from the frame synchronization circuit 16 and the demultiplexing circuit 17 are multiplexed.

The frame synchronization circuit 16 detects the transmission frame synchronization signal and the reception frame synchronization signal from the signal output from the multiplex circuit 15, thereby performing frame synchronization between the two frames, the transmission signal frame and the reception signal frame. , outputs the timing signal A of the received frame synchronization signal to the separation circuit 17. Further, if the frame synchronization circuit 16 cannot detect the reception frame synchronization signal, it outputs the reception frame synchronization signal B to the fault notification circuit 20, and if it cannot detect the transmission frame synchronization signal F2, it outputs the transmission frame synchronization signal C to the fault notification circuit. Output to 20. The separation circuit 17 separates the received signal and the transmitted signal from the multiplexing circuit 15,
Each receives the timing signal A from the frame synchronization circuit 16, and separates and outputs the received data D obtained by removing the received frame synchronization signal from the received signal, and the transmitted data E obtained by removing the transmitted frame synchronization signal F2 from the transmitted signal. The separation circuit 17 uses the timing signal A from the frame synchronization circuit 16 to determine the position of the received frame synchronization signal to be removed from the received signal. The transmission data D output by the demultiplexing circuit 17 is sent to the multiplexing/demultiplexing circuit of the multiplexing device.

The transmission data E output from the separation circuit 17 is input to a pattern matching circuit 18. In addition, the multiplex circuit 12
Delaying the transmission data input to the buffer 19,
It is input into the pattern matching circuit 18 in phase with the transmission data E from the separation circuit 17 . The pattern matching circuit 18 matches the two input transmission data and outputs a transmission data mismatch signal N to the failure notification circuit 20 when a mismatch is detected. The failure notification circuit 20 outputs an alarm signal when the transmission data mismatch signal N from the pattern matching circuit 18, the reception frame out-of-synchronization signal B or the transmission frame out-of-synchronization signal C from the frame synchronization circuit 16 is input.

If an abnormality occurs in the high-speed line, the received frame synchronization signal disappears from the received signal, so the frame synchronization circuit 16 cannot synchronize the frame with the received signal among the signals from the multiplex circuit 15, and the received frame synchronization signal is lost. Output B. As a result, the fault notification circuit 20 outputs an alarm signal. Further, when the transmission frame synchronization signal F2 disappears from the transmission signal due to an abnormality in the frame generation circuit 11, for example, the frame synchronization circuit 16 outputs the transmission frame synchronization loss signal C. Transmission frame synchronization signal F2 during transmission signal
If an abnormality occurs in the multiplexing circuit 12 such that the data is normally multiplexed but the transmitted data is lost, the pattern matching circuit 18 outputs a transmitted data mismatch signal N. Line driver 13 of high-speed line termination circuit 10, fault notification circuit 2
If an abnormality occurs in any part other than 0, a reception frame synchronization loss signal B and a transmission frame synchronization loss signal C are generated.
Alternatively, at least one of the transmission data mismatch signals N is output, and as a result, the failure notification circuit 20 outputs an alarm signal. Therefore, by outputting an alarm signal from the failure notification circuit 20, it is possible to detect that an abnormality has occurred in the high-speed line or the high-speed line termination circuit 10 itself.

The alarm signal output by the fault notification circuit 20 is used as a trigger to request switching of the high-speed line termination circuit 10 and/or the corresponding high-speed line to standby.

[0018] Furthermore, based on the information on which of the reception frame synchronization loss signal B, transmission frame synchronization loss signal C, and transmission data mismatch signal N occurs when an abnormality occurs, it is possible to determine to a certain extent in which part the abnormality has occurred. It can be estimated.

Referring to FIG. 2, the received signal input from the line receiver 14 to the multiplexing circuit 15 is a signal in which the received frame synchronization signal F1 and the received data are multiplexed. Further, the transmission signal inputted from the multiplexing circuit 12 to the multiplexing circuit 15 is a signal in which the transmission frame synchronization signal F2 and the transmission data are multiplexed. The received signal and the transmitted signal have the same frame period, but are not synchronized in frame phase. The multiplex circuit 15 converts the input received signal and transmitted signal into
These two signals are multiplexed without matching their frame phases. That is, the multiplexing circuit 15 multiplexes the received signal and the transmitted signal so that the received signal input in each frame period of the transmitted signal is placed before each corresponding frame of the transmitted signal. Therefore, the multiplex circuit 15 is the frame synchronization circuit 1
The timing of the boundary between the received signal and the transmitted signal in the signals output to 6 and the separation circuit 17 is known. Furthermore, the insertion position of the transmission frame synchronization signal F2 in the transmission signal is also known because the transmission frame synchronization signal F2 is multiplexed with the transmission data by the multiplexing circuit 12. However, the insertion position of the received frame synchronization signal F1 in the received signal is unknown to the multiplex circuit 15.

Referring to FIG. 3, the signal output from the multiplex circuit 15 is input to the frame synchronization circuit 16 and applied to the first and second pattern matching circuits 161 and 162, respectively. The frame synchronization circuit 16 includes a frame generation circuit 163. With reference also to FIG.
2, the frame generation circuit 163 generates a transmission frame synchronization signal F2. Frame generation circuit 16
The transmission frame synchronization signal F2 generated by the transmission frame synchronization signal F2 passes through the variable buffer 164 and is input to the first pattern matching circuit 161, and is also directly input to the second pattern matching circuit 162.

The second pattern matching circuit 162 matches the signal from the multiplex circuit 15 with the transmission frame synchronization signal F2 from the frame generation circuit 163 at the timing of the transmission frame synchronization signal F2 from the frame generation circuit 163. As a result, the transmission frame synchronization signal F2 is detected from the signal output from the multiplexing circuit 15, and frame synchronization is performed with the frame of the transmission signal. Furthermore, if there is a mismatch in the matching results, or in other words, if the second pattern matching circuit 162 cannot detect the transmission frame synchronization signal F2 from the signal output from the multiplexing circuit 15, it generates a transmission frame out-of-synchronization signal C. Output to the fault notification circuit 20.

The transmission frame synchronization signal F2 and the reception frame synchronization signal F1 contained in the signal from the multiplex circuit 15 have different phases but have the same pattern that repeats in a plurality of frame periods, for example, 24 frame periods. variable buffer 1
64 can be matched with the phase of any time slot of the received signal for 24 frames in the signal from the multiplex circuit 15 (see FIG. 2), and The variable delay range of the variable buffer 164 is set so as not to match the phase of any time slot of the signal. First pattern matching circuit 16
1 compares the signal from the multiplex circuit 15 with the transmission frame synchronization signal F2 from the variable buffer 164 at the timing of the transmission frame synchronization signal F2 from the variable buffer 164, and if there is a discrepancy in the comparison result, the reception frame synchronization is performed. The failure signal B is sent to the variable buffer 164 and the fault notification circuit 20.
Output to. When the received frame out-of-synchronization signal B is input, the variable buffer 164 changes the delay time of the signal from the multiplex circuit 15 by one time slot. When the variable buffer 164 changes the delay time, the pattern matching circuit 161 matches the two input signals again. If the received frame synchronization signal F1 is correctly included in the signal from the multiplex circuit 15, while the variable buffer 164 is sequentially changing the delay time within the variable range, the matching result of the first pattern matching circuit 161 is There will always be a match. The first pattern matching circuit 161 transfers the timing signal A of the received frame synchronization signal F1 to the separation circuit 1 every time the matching results match.
Output to 7. If the matching result of the first pattern matching circuit 161 does not match even if the delay time of the variable buffer 164 changes over the entire variable range, the first pattern matching circuit 161 continuously synchronizes the received frame. A deviation signal B is output.

Referring to FIG. 4, the signal output from the multiplexing circuit 15 and the timing signal A output from the first pattern matching circuit 161 of the frame synchronization circuit 16 are transmitted to the separation circuit 1.
7 is input to the selector 171. The selector 171 is
Of the signals input from the multiplexing circuit 15 (see FIG. 2), only the received data is separated and outputted to the buffer 172, and only the transmitted data is separated and outputted to the buffer 173. The timing of the boundary between the received signal and the transmitted signal in the signal from the multiplex circuit 15 and the insertion position of the transmission frame synchronization signal F2 are already known, as described above, and the insertion position of the reception frame synchronization signal F1 is determined from the frame synchronization circuit 16. Since the timing information is given by the timing signal A, the selector 171 performs the above-described separation operation using this timing information. One frame of received data D is sequentially read from the buffer 172 over one frame period and sent to the multiplexing/demultiplexing circuit of the multiplexer. Also, one frame of transmission data E is read out sequentially over one frame period from the buffer 173,
Output to the pattern matching circuit 18.

By the way, due to an abnormality in the multiplex circuit 15 or an abnormality in the selector 171 in the separation circuit 17, the separation circuit 1
The transmission data E from 7 to the pattern matching circuit 18 is “1” or “1” regardless of the transmission data input to the multiplexing circuit 12.
There may be an abnormality in which the value is fixed at 0. If such an abnormality occurs in the multiplexer circuit 15 or the separation circuit 17, and the transmission data input to the multiplexer circuit 12 becomes a series of 1s or 0s, Although the probability of occurrence is small, something like this can happen.The above-described high-speed line termination circuit 10 cannot detect such an abnormality.Referring to FIG. 5, a high-speed line termination circuit according to a second embodiment of the present invention 30 can also detect such abnormalities.

The high-speed line termination circuit 30 includes, in addition to the high-speed line termination circuit 10 of the first embodiment shown in FIG. A buffer 34 is provided. The pattern generation circuit 31 generates an additional pattern rich in randomness, such as a pseudo-random pattern, whose repetition period is the frame period of the transmission data.

Referring to FIG. 6, the third multiplex circuit 32 multiplexes the additional pattern from the pattern generation circuit 31 onto the transmission signal from the first multiplex circuit 12 and outputs the resultant signal. Second
The multiplexing circuit 15A multiplexes the signal output from the third multiplexing circuit 32 and the received signal from the line receiver 14 without matching the frame phases of these two signals. That is, the second multiplex circuit 15A is connected to the third multiplex circuit 3.
The two signals are multiplexed such that the received signal input in each frame period of the signal from the third multiplexing circuit 32 is placed before each corresponding frame of the signal from the third multiplexing circuit 32. The frame synchronization circuit 16 detects the transmission frame synchronization signal F2 and the reception frame synchronization signal F1 from the signal output from the second multiplex circuit 15A, and outputs the timing signal A of the reception frame synchronization signal F1. In addition, the frame synchronization circuit 16A
outputs a reception frame out-of-synchronization signal B when it cannot detect a reception frame synchronization signal, and outputs a transmission frame out-of-synchronization signal C when it cannot detect a transmission frame synchronization signal.

The separation circuit 17A is the separation circuit 17 (FIG. 4).
The selector corresponding to the selector 171 and the buffer 17
It consists of two buffers corresponding to 2,173 and another buffer for additional patterns. The selector uses the timing signal A from the frame synchronization circuit 16 to separate the received data, transmitted data, and additional pattern from the signal output by the second multiplexing circuit 15A, and outputs each of them to the corresponding buffer. The received data D read from the buffer into which the received data was input is sent to the multiplexing/demultiplexing circuit of the multiplexing device, and the transmitted data E read from the buffer into which the transmitted data was input is output to the pattern matching circuit 18. Further, the additional bit G read from the buffer into which the additional bit has been input is input to the second pattern matching circuit 33. The additional pattern generated by the pattern generation circuit 31 is also sent to the buffer 34, which delays it and inputs it to the second pattern matching circuit 33 in phase with the additional pattern G from the separation circuit 17A. The second pattern matching circuit 33 matches the two input additional patterns, and outputs an additional pattern mismatch signal M when a mismatch is detected.

The additional pattern mismatch signal M outputted by the second pattern matching circuit 33, the received frame synchronization loss signal B and the transmission frame synchronization loss signal C outputted by the frame synchronization circuit 16, and the transmission signal outputted by the pattern matching circuit 18. The data mismatch signal N is the failure notification circuit 20A.
sent to. The failure notification circuit 20A outputs an alarm signal when receiving frame synchronization loss signal B, transmission frame synchronization loss signal C, transmission data mismatch signal N, or additional pattern mismatch signal M is input.

The high-speed line termination circuit 30 in FIG. 5 includes, in addition to the circuits described above, a pattern generation circuit 11, a multiplex circuit 1
2. Since it is equipped with a line driver 13, a line receiver 14, a pattern matching circuit 18, and a buffer 19,
It has all the functions that the high-speed line termination circuit 10 of FIG. 1 has.

The transmission data input to the first multiplex circuit 12 is multiplexed with the transmission frame synchronization signal F2 in the multiplex circuit 12, multiplexed with an additional pattern in the third multiplex circuit 32, and then transmitted to the second multiplex circuit 15A. It is multiplexed with the received signal at , separated at a separation circuit 17A, and inputted to a pattern matching circuit 18. Second multiplex circuit 15A
Due to an abnormality in the selector in the separation circuit 17A, the transmission data E from the separation circuit 17A to the pattern matching circuit 18 is fixed to "1" or "0" regardless of the transmission data input to the first multiplex circuit 12. Moreover, the transmission data input to the first multiplex circuit 12 is “1” or “1”.
0'', the pattern matching circuit 18 does not output the transmission data mismatch signal N even though an abnormality has occurred because the two input transmission data match.

However, in this case, the additional pattern G separated by the separation circuit 17A and inputted to the second pattern matching circuit 33 is also fixed to "1" or "0". On the other hand, since the additional pattern input from the pattern generation circuit 31 to the second pattern matching circuit 33 via the buffer 34 is a pattern rich in randomness, in this case, the two patterns input to the second pattern matching circuit 33 The append pattern does not match,
The second pattern matching circuit 33 outputs an additional pattern mismatch signal M. As a result, the fault notification circuit 20A outputs an alarm signal. By outputting this alarm signal, the occurrence of the above-mentioned abnormality can be detected.

[0032]

Effects of the Invention As explained above, the high-speed line termination circuit according to the present invention multiplexes a transmission signal with a reception signal and performs frame synchronization on the multiplexed signal, thereby not only frame synchronization with the reception signal but also synchronization with the transmission signal. By checking the frame synchronization of the multiplexed signal and checking whether the transmission data separated from the multiplexed signal matches the original transmission data, it is possible to detect not only abnormalities in the high-speed line but also abnormalities in the high-speed line itself.

[0033] Furthermore, if not only the transmitted signal but also the additional pattern is multiplexed into the received signal, and the additional pattern separated from the multiplexed signal is matched with the original additional pattern, it is possible to detect abnormalities in the signal itself. It can be detected more reliably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of multiplex circuit 15 in FIG. 1;

FIG. 3 is a block diagram of the frame synchronization circuit 16 in FIG. 1.

FIG. 4 is a block diagram of the separation circuit 17 in FIG. 1.

FIG. 5 is a block diagram showing a second embodiment of the invention.

6] Multiplex circuit 32 and multiplex circuit 15 in FIG. 5
3 is a timing chart for explaining the operation of A.

[Explanation of symbols]

11 Frame generation circuit 12, 15, 15A, 32 Multiplex circuit 13
Line driver 14 Line receiver 16 Frame synchronization circuit 17, 17A Separation circuit 18, 33 Pattern matching circuit 19, 34 Buffer 20, 20A Fault notification circuit 31 Pattern generation circuit

Claims (20)

[Claims] 1. Means for adding a transmission frame synchronization signal to data to be transmitted, means for sending out the data to be transmitted to which the transmission frame synchronization signal has been added to a communication line, and receiving a signal from the communication line. means for multiplexing the received signal and the data to be transmitted to which the transmission frame synchronization signal has been added to create a multiplexed signal; means for processing the multiplexed signal; means for separating the data to be transmitted contained in the multiplexed signal from the multiplexed signal; 1. A high-speed line termination circuit, comprising means for detecting a mismatch between two pieces of data by comparing the two pieces of data with each other. 2. The high-speed line termination circuit according to claim 1, further comprising means for detecting frame synchronization loss in data to be transmitted to which the transmission frame synchronization signal has been added from the multiplexed signal. 3. The high-speed line termination circuit according to claim 1, further comprising means for creating a signal indicating frame synchronization of the received signal from the multiplexed signal and supplying the signal to the processing means. 4. The high-speed line termination circuit according to claim 2, further comprising means for detecting frame synchronization loss in the received signal from the multiplexed signal. 5. Means for generating data in a predetermined pattern; and means for transmitting data to be transmitted to which the transmission frame synchronization signal has been added by adding the data in the pattern to the data to be transmitted to which the transmission frame synchronization signal has been added. means for supplying the multiplexed signal to the means for creating the multiplexed signal in place of the data to be generated; means for extracting the pattern data from the multiplexed signal to which the pattern data has been added; 2. The high-speed line termination circuit according to claim 1, further comprising means for comparing said pattern data and said pattern data from said extracting means to detect a mismatch between the two data. 6. The detecting means includes means for adjusting the phases of the two data.
High-speed line termination circuit described. 7. The detecting means includes means for adjusting the phases of the two data.
High-speed line termination circuit described. 8. The high-speed line termination circuit according to claim 1, wherein said sending means includes a line driver. 9. The high-speed line termination circuit according to claim 1, wherein said receiving means includes a line receiver. 10. A first means for receiving transmission data to be sent to a high-speed line, a frame generation circuit for generating a transmission frame synchronization signal to be added to the transmission data, and coupled to the first means and the frame generation circuit. and a first means for inputting the transmission data from the first means and the transmission frame synchronization signal from the frame generation circuit, multiplexing the transmission data and the transmission frame synchronization signal and outputting the multiplexed signal as a transmission signal. multiplex circuit;
a second means for sending the transmission signal to the high-speed line;
third means for receiving a received signal from the high-speed line; coupled to the first multiplex circuit and the third means; inputting the transmitted signal from the first multiplex circuit and from the third means; a second multiplexing circuit that inputs the received signal and multiplexes and outputs the two input signals;
detects the transmission frame synchronization signal and the reception frame synchronization signal included in the reception signal from the multiplexed signal outputted by the multiplex circuit, outputs a timing signal of the detected reception frame synchronization signal; a frame synchronization circuit that outputs a frame synchronization loss signal when the received frame synchronization signal cannot be detected; and a frame synchronization circuit that receives the multiplexed signal output from the second multiplex circuit and the timing signal output from the frame synchronization circuit; Processing the multiplexed signal based on the timing signal to output received data in which the received frame synchronization signal is removed from the received signal included in the multiplexed signal, and output the transmitted data included in the multiplexed signal. a separation circuit; and a separation circuit that transmits the transmission data outputted by the separation circuit to the first
A high-speed line termination circuit comprising: pattern matching means for matching the transmission data from the first means input to the multiplex circuit and outputting a mismatch signal when a mismatch is detected. 11. The high-speed method according to claim 10, wherein the pattern matching means includes a buffer that delays the transmission data from the first means and matches the phase with the transmission data output from the separation circuit. Line termination circuit. 12. The high-speed line termination circuit according to claim 10, wherein the second means includes a line driver that inputs the transmission signal from the first multiplex circuit and sends it to the high-speed line. 13. The high-speed line termination circuit according to claim 12, wherein the third means includes a line receiver that receives the received signal from the high-speed line and outputs it to the second multiplex circuit. 14. The method of claim 1, further comprising a failure notification circuit that receives at least one of the frame synchronization loss signal from the frame synchronization circuit and the mismatch signal from the pattern matching circuit and outputs an alarm signal. The high-speed line termination circuit according to item 10. 15. The frame synchronization circuit outputs a transmission frame synchronization loss signal when the transmission frame synchronization signal cannot be detected, and outputs a reception frame synchronization loss signal when the reception frame synchronization signal cannot be detected. The high-speed line termination circuit according to claim 10. 16. A frame generation circuit that generates a transmission frame synchronization signal; and a frame generation circuit that receives transmission data to be sent to a high-speed line and the transmission frame synchronization signal, multiplexes the transmission data and the transmission frame synchronization signal, and outputs the multiplexed signal as a transmission signal. a first multiplex circuit that generates a predetermined pattern; a second multiplex circuit that multiplexes the pattern from the pattern generator and the transmission signal from the first multiplex circuit; and the second
a third multiplex circuit that multiplexes the signal from the multiplex circuit onto the received signal received from the high-speed line; and a third multiplex circuit that multiplexes the signal output from the third multiplex circuit into the transmit frame synchronization signal and the receive frame included in the receive signal. a frame synchronization circuit that detects a synchronization signal and outputs a timing signal of a received frame synchronization signal, and outputs a frame synchronization loss signal when the transmission frame synchronization signal or the reception frame synchronization signal cannot be detected; The signal outputted by the multiplex circuit is processed based on the timing signal outputted by the frame synchronization circuit, and separated into received data obtained by removing the received frame synchronization signal from the received signal, the transmitted data, and the pattern, and outputted. a separation circuit; a first pattern matching means that compares the transmission data outputted by the separation circuit with the transmission data inputted to the first multiplex circuit and outputs a transmission data mismatch signal when a mismatch is detected; A high-speed line termination circuit comprising: second pattern matching means for comparing the pattern output from the separation circuit with the pattern from the pattern generation circuit and outputting a pattern mismatch signal when a mismatch is detected. 17. The first pattern matching means includes a first buffer that delays the transmission data input to the first multiplex circuit to match the phase with the transmission data output from the separation circuit, and 1. The second pattern matching means includes a second buffer that delays the pattern outputted by the pattern generation means and matches the phase with the pattern outputted from the separation circuit.
6. The high-speed line termination circuit described in 6. 18. A line driver that inputs the transmission signal from the first multiplex circuit and sends it out to the high-speed line, and a line receiver that receives the received signal from the high-speed line and outputs it to the second multiplex circuit. 18. The high-speed line termination circuit according to claim 17, further comprising: 19. At least one of the frame synchronization loss signal from the frame synchronization circuit, the transmission data mismatch signal from the first pattern matching circuit, and the pattern mismatch signal from the second pattern matching circuit. 19. The high-speed line termination circuit according to claim 18, further comprising a failure notification circuit that outputs an alarm signal in response to the failure notification circuit. 20. The frame synchronization circuit outputs a transmission frame synchronization loss signal when the transmission frame synchronization signal cannot be detected, and outputs a reception frame synchronization loss signal when the reception frame synchronization signal cannot be detected. 17. The high-speed line termination circuit according to claim 16.