JPH04211542A - Preamble length adjustment method and independent synchronization type serial data communication equipment for communication network - Google Patents

Abstract

PURPOSE:To always maintain the length of preamble within a convenient range and to ensure stable data transmission in a communication network even in an environment full of adverse conditions, and to obtain an independent synchronization type serial data communication equipment supporting reliable independent synchronization operation in each connection station. CONSTITUTION:The length of the preamplifier inputted to a buffer 22 is monitored and when it is judged that the preamble length of a frame has been preliminarily adjusted in the same direction, the adjustment of the preamble length of the applicable frame is suppressed and the object of adjustment is shifted to the subsequent frame (cycle), and when it is judged that the preamble length of the subsequent applicable frame has also been preliminarily adjusted in the same direction similarly to the previous frame, the object of adjustment is further shifted to the subsequent frame and so on.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION This invention relates to a preamble length adjustment method in a communication network and an independent synchronous serial data communication device employing the preamble length adjustment method. , relates to the implementation of a method and apparatus that can always maintain a suitable length range in any case.

0002

2. Description of the Related Art In general, most transmitter/receiver circuits connected to communication networks require a few bits of time from the time an input appears to the time a valid output is produced, so a preamble is usually inserted before each piece of data constituting a frame. A bit string called . . . is added to compensate for the time it takes to reach a steady state, ie, a state in which these transmitter/receiver circuits can send valid outputs to the system. In addition, FDDI-II
(F.D.D.I. - Two: F
iber Distributed Data Int
In the communication standard defined as IEEE 2013-2013 (Earface-II), the length of this preamble is often set at 5 symbols (1 symbol = 5 bits).

By the way, in such a communication network, since each station connected to the network operates in independent synchronization, the cumulative phase difference of the transmitted serial data caused by subtle differences in the frequencies of these stations also cannot be ignored. This situation is shown in FIGS. 15 and 16.

That is, in FIG. 15, the first station 1 to the nth station
Station n is a station connected to the above communication network, and here it is assumed that it accepts serial data S0 transmitted at transmission frequency f0, temporarily stores it in a buffer memory, and then transfers this stored data to the next It is assumed that the first station 1 that transfers the stored data to the other station performs the read (transfer) operation of the stored data at an internal frequency f1 slightly lower than the transmission frequency f0, and the serial data transferred from the first station 1 The second station 2 receives S1 (transmission frequency f1), temporarily stores it in a buffer memory, and further transfers this stored data to the next station at an internal frequency f2 that is slightly higher than the frequency f1. The readout (transfer) operation of the stored data is performed, and the serial data S2 (transmission frequency f2) transferred from the second station 2 is received and temporarily stored in the buffer memory, and the stored data is further transferred. The third station 3, which transfers to the next station, uses the above frequency f.
If the reading (transfer) operation of the stored data is performed at an internal frequency f3 slightly higher than 2, the phase of each serial data S0 to S3 will naturally be as shown in FIG.
The results vary as shown in (a) to (d). If these phase differences are accumulated, an overflow or underflow will occur in the buffer memory for temporarily storing data in the subsequent connection station, and the normal operation of the buffer memory cannot be guaranteed.

For this reason, conventionally, each station is provided with a device as shown in FIG. 17, and the above-mentioned preamble (the shaded part PA of each serial data in FIG. 16) is transmitted through the device.
By increasing or decreasing the length of , the above phase difference is absorbed.

Incidentally, in the device shown in FIG. 17, the internal clock source 11 is a part that generates a clock signal that determines the operating frequency of the station, and the elastic buffer 12 and smoothing buffer 13 each receive the serial data. FIFO
rst-out) format, and the clock extraction unit 14 extracts the transmission clock from the input serial data and uses the extracted clock WC1.
This part writes the serial data to the elastic buffer 12 based on the data, and the used buffer amount detection unit 15 detects the amount of data written to the elastic buffer 12, that is, the buffer usage amount of the buffer 12 each time. This is the part that detects the clock phase control unit 1.
6 determines the phase of the clock generated from the internal clock source 11 based on the detection output of the used buffer amount detection unit 15 in order to absorb the phase shift of data due to the frequency difference between stations through the elastic buffer 12. The preamble length detector 17 controls the phase shift (advance or delay the phase) and reads out the data stored in the elastic buffer 12 using the clock RC1 of the controlled phase. Detect the length of the preamble PA included in the serial data read from the serial data (
For example, the used buffer amount detection section 18 is a section that detects the preamble PA and counts its length.The used buffer amount detection section 18 is a section that detects the buffer usage amount of the smoothing buffer 13 each time.
The internal clock source 1 is used to increase or decrease the length of the preamble PA through the smoothing buffer 13.
The phase of the clock generated from WC2 is controlled based on the detection outputs of the preamble length detection section 17 and the used buffer amount detection section 18, and the clock WC2 having the controlled phase is used to read from the elastic buffer 12. Smoothing buffer 1
This is the part written in 3. The data written in the smoothing buffer 13 in this way is transferred to the internal clock source 1.
The data is read out based on the clock RC2 generated from RC2, and is output from the station as transfer data to the next station.

Hereinafter, the smoothing buffer 1 of the apparatus shown in FIG.
Regarding the control method No. 3, that is, the preamble length adjustment method, some of the main methods conventionally employed will be shown, and the control algorithms for each will be listed.

◆First method (for convenience, hereinafter referred to as "limit smoother") If the preamble length is 4 to 6 symbols, it is transmitted as is, and when the length is 3 or less or 7 or more symbols, the preamble is The control algorithm is as follows.

(a) When resetting the network, the smoothing buffer 13 is set to 50% usage.

(b) In areas other than the preamble portion, the smoothing buffer 13 is caused to perform FIFO operation. That is, symbols are extracted from the buffer 13 and transmitted until the preamble arrives.

(c) If the detected preamble is 3 symbols or less and the start delimiter (identification code at the beginning of the cycle) of the next cycle appears to be the output of the buffer 13, the buffer 13
If the usage rate is less than 100%, a preamble is transmitted instead of a start delimiter, and the input from the previous station is buffered. When the usage rate of this buffer 13 reaches 100% or when the transmission preamble reaches 4 symbols, transmission of the next cycle starts from the start delimiter at the head of the buffer 13.

(d) Count the number of symbols in the preamble being transmitted, and if the start delimiter of the next cycle does not appear at the output of the buffer 13 even after transmitting 6 symbols, wait until the start delimiter appears. Take out the preamble from buffer 13 and discard it. If the start delimiter has not yet been buffered, the buffer 13 will be empty at this point, so the preamble is retransmitted while waiting for the start delimiter to arrive. ◆Second method (for convenience, hereafter referred to as "centering smoother")
In the case where the above limit smoother transmits a 4-symbol or 6-symbol preamble, if the usage rate of the buffer 13 can be brought close to 50% by increasing the preamble to 5 symbols, then the limit smoother transmits a 4-symbol or 6-symbol preamble as follows. A 5-symbol preamble is transmitted instead of a symbol.

(a) When resetting the network, the smoothing buffer 13 is set to 50% usage.

(b) In areas other than the preamble portion, the smoothing buffer 13 is caused to perform FIFO operation. That is, symbols are extracted from the buffer 13 and transmitted until the preamble arrives.

(c) If the transmission preamble is 3 symbols or less and the start delimiter of the next cycle appears as the output of the buffer 13, and the usage rate of the buffer 13 is less than 100%, transmit the preamble instead of the start delimiter, Input from the previous station is buffered. Also, c-1) When the usage rate of the buffer 13 reaches 100%, or c-2) When the usage rate of the buffer 13 exceeds 50% and the transmission preamble has 4 symbols, or c-
3) When the usage rate of the buffer 13 is 50% or less and the transmission preamble has 5 symbols, the transmission of the next cycle is started from the start delimiter at the beginning of the buffer 13.

(d) Count the number of symbols in the preamble being transmitted, d-1) If a 5-symbol preamble is transmitted and the usage rate of the buffer 13 exceeds 50%, the buffer 13 is
As long as the usage rate exceeds 50%, the preamble remaining in the buffer 13 is discarded until the start delimiter appears at the output of the buffer 13. If the usage rate of the buffer 13 reaches 50% (or less) during the discarding process, the process proceeds to the next step d-2).

d-2) Take out the preamble from the buffer 13 and transmit it. If the total length of the preamble becomes 6 symbols, the preamble is discarded until the start delimiter appears, unless the buffer 13 is empty. If the start delimiter has not yet been buffered, the buffer 13 will be empty at this point, so the preamble is sent while waiting for the start delimiter to arrive.

◆Third method (for convenience, hereinafter referred to as "target smoother") is a method in which the length of the preamble is made as close to 5 symbols as the capacity of the buffer 13 allows, and the control algorithm is as follows.

(a) When resetting the network, the smoothing buffer 13 is set to 50% usage.

(b) In areas other than the preamble portion, the smoothing buffer 13 is caused to perform FIFO operation. That is, symbols are extracted from the buffer 13 and transmitted until the preamble arrives.

(c) If the preamble is 4 symbols or less and the start delimiter of the next cycle appears as the output of the buffer 13 and the usage rate of the buffer 13 is less than 100%, transmit the preamble instead of the start delimiter, Input from the previous station is buffered. Buffer 13 usage rate is 100%
When this occurs, transmission of the next cycle begins from the start delimiter at the head of the buffer 13.

(d) Count the number of symbols in the preamble being transmitted, and after transmitting a 5-symbol preamble, buffer 1
Unless 3 is empty, discard the preamble until the start delimiter is encountered. If the start delimiter has not yet been buffered, the buffer 13 will be empty at this point, so the preamble is sent while waiting for the start delimiter to arrive.

The above is the preamble length adjustment method.
This is the one that has traditionally been considered the most likely. In addition, documents related to these preamble length adjustment methods include the American National Standards Institute (ANSI).
Al Standards Institute) working paper, the following are known:

(A) DRAFT PROPOSED ANS “FDDI Hybrid Ring Control”, August 12, 1988, pp. 32-38 [DRAFT PROPOS
ED ANS ″FDDIHYBRID RIN
G CONTROL” (Aug. 12, 1988
) P. 32-P. 38] (B) David Dodds “Jitter Control
In FDDI-II Systems”, September 3, 1987
0 days [David Dodds ``JITTER
CONTROL IN FDDI-II SY
STEMS” (Sept. 30, 1987)] (C) David Dodds “Jitter Control
In FDDI-II Systems Progress Report, July 8, 1987 [David Dodds
``JITTER CONTROL IN F
DDI-II SYSTEMS Progress
Report” (July 8, 1987)
]

[0025]

[Problems to be Solved by the Invention] In any of the above-mentioned conventional preamble length adjustment methods, as is clear from FIG. The preamble length, which has been adjusted to be extremely short or extremely long by absorbing this phase shift, is then corrected through a smoothing buffer. Therefore, in this method, when short preamble cycles (frames) arrive at a certain station in succession, the smoothing buffer works to restore the preamble length to its original length, and in a few cycles the smoothing buffer It is expected that the allowance will be used up. That is, in this case, subsequent cycles of the serial data must be sent to the next station without being able to perform any correction. Therefore, if the serial data to be transmitted passes through many stations and the above adjustment is repeated in the same cycle, the preamble length in the cycle becomes shorter and shorter, until it becomes 0 symbols (no preamble). It is possible that it may become. This means that subsequent adjustments may affect the data portion and even cause data corruption.

[0026] This invention was made in view of these circumstances, and no matter how bad the environment may be,
A preamble length adjustment method in a communication network that always maintains the length of the preamble within a suitable length range to ensure stable data transmission on the communication network, and each connection using the preamble length adjustment method. An object of the present invention is to provide an independent synchronous serial data communication device that supports highly reliable independent synchronous operation of stations.

[0027]

[Means for Solving the Problems] In order to achieve these objects, the present invention adjusts and absorbs the cumulative phase difference of the serial data by increasing or decreasing the length of a preamble attached to each frame of the serial data. In other words, when increases and decreases in preamble length for the same frame overlap in the same direction (increase or decrease), preamble length adjustment (increase or decrease) of each connected station is performed to refrain from increasing or decreasing the preamble length for the frame. (control) algorithm.

[0028] In detail, as mentioned above, the length of the preamble is increased or decreased through an appropriate buffer in FIFO format, and the allowable usage amount of the buffer is ±m (m is an integer). The length of the input preamble is PAi, the length of the preamble output from the same buffer is PA, and the reference value of the preamble length is n.
(n is an integer), then based on the buffer usage amount B, (a) When -m≦B≦+m, PA=PAi (b
) When B<-m, if PAi ≦n, then PA
=PAi +1 If PAi =n+1 then PA=PAi (no adjustment) (c) When B>+m, if PAi ≧n then PA=PAi -1 If PAi =n-1 then PA=PAi (no adjustment) The length of the preamble is adjusted (increase/decrease control) as follows.

Further, in the present invention, in order to realize a device having such a preamble length adjustment function as an independent synchronous serial data communication device disposed in each connecting station, (A
) An internal clock source that generates a clock of a predetermined frequency for serial data transmission.

(B) Buffer means for temporarily storing serial data in FIFO format.

(C) Clock extraction means for extracting a transmission clock from input serial data and writing the serial data into the buffer means based on the extracted clock.

(D) First detection means for detecting the amount of data stored each time in the buffer means.

(E) A second detection means for detecting the length of a preamble included in the input serial data.

(F) Based on the detection outputs of the first and second detection means, the detection output of the first detection means is less than a predetermined amount and the detection output of the second detection means is less than or equal to a reference value. Sometimes, the phase of the clock generated from the internal clock source is delayed, and when the detection output of the first detection means exceeds a predetermined amount and the detection output of the second detection means is equal to or higher than a reference value, the internal clock is delayed. Control is performed to advance the phase of the clock generated from the internal clock source, and otherwise maintain the phase of the clock generated from the internal clock source at the standard phase for serial data transmission, and clock phase control means for reading out the data stored in the buffer means as output serial data to the next station based on the clock phase control means;

This is realized as a device equipped with the following.

[0036]

[Operation] According to the conventional preamble length adjustment algorithm described above, even if there is a frame (cycle) that has already been adjusted in the same direction to increase or decrease the preamble length in the previous station, the authority itself If it is determined that the preamble length of the frame should be increased or decreased based on the determination conditions, the preamble length is adjusted to further increase or decrease the length. However, in the above preamble length adjustment algorithm according to the present invention, the length of the preamble input to the buffer (corresponding to the conventional elastic buffer) is monitored, and the preamble length of the frame is adjusted in the same direction. If it is determined that the preamble length has been adjusted previously, refrain from adjusting the preamble length for that frame, and proceed to the next frame (cycle). If it is determined that the
Then, the adjustment of the preamble length is carried forward. Therefore, according to the preamble length adjustment algorithm according to the present invention, the preamble length adjustment is not repeated for the same frame, and the resistance against data destruction is significantly improved.

Furthermore, in the above-mentioned independent synchronous serial data communication device, the clock phase control means (F) comprises:
The preamble length adjustment algorithm of (a) to (c) above is executed through the buffer means (corresponding to the conventional elastic buffer) of (B),
By disposing such an independent synchronous serial data communication device at each connecting station connected by a network, always stable data transmission without data corruption etc. can be realized.

In the phase control by the clock phase control means (F), the control to advance the phase of the clock corresponds to "reduction" of the preamble length, and conversely, the control to advance the phase of the clock corresponds to the "reduction" of the preamble length, and conversely, the control to delay the phase of the clock (that is, when the step is stopped) ) control corresponds to an "increase" in the preamble length.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of an independent synchronous serial data communication device according to the present invention.

Similar to the device shown in FIG. 17, this communication device is also provided at each station (see FIG. 15) connected to the communication network.

First, the configuration of this device and the functions of each part will be explained.

In the device shown in FIG. 1, the internal clock source 21 is a part that generates a clock signal that determines the operating frequency of the station. Although this clock frequency is basically set to the same frequency for each station, in reality, its accuracy varies due to variations in the components that make up the clock source 21, and there may be slight variations between each station. As mentioned above, a frequency difference occurs. Incidentally, it is currently possible to suppress such frequency deviation to about ±50 ppm at the maximum.

[0043] The buffer 22 also has a conventional device (FIG. 1).
Although it corresponds to the elastic buffer 12 in 7), it also has the function of the smoothing buffer 13 in the same device, and like these buffers 12 and 13, the serial data input to the authorities is transferred to the FIF.
This is a part for temporary storage in O format. Incidentally, in this example, the buffer capacity of this buffer 22 is ±5 bits (
2 symbols).

[0044] Furthermore, the clock extractor 23 extracts the transmission clock from the serial data input to the authority,
This is the part that writes the serial data to the buffer 22 based on the extracted clock WC. This circuit configuration itself is conventionally well known.

The used buffer amount detection section 24 is a part that detects the amount of data written to the buffer 22, that is, the amount of buffer used each time. Detection of such a buffer usage amount can be realized, for example, by detecting a phase difference between the extracted clock WC, which is a buffer write clock, and a buffer read clock RC, which will be described later.

The preamble length detection section 25 is a section that detects the length of the preamble PA (see the shaded area in FIG. 16) included in the serial data input to the authority. Such detection of the preamble length is realized, for example, by first detecting the start point of the preamble PA in the same serial data, and counting the number of constituent symbols (number of bits) using a counter.

Based on the detection outputs from the used buffer amount detector 24 and preamble length detector 25, the clock phase controller 26 adjusts the clock generated from the internal clock source 21 according to a predetermined preamble length adjustment algorithm. Control is executed to advance, delay, or maintain the phase, and this phase-controlled clock (this is the read clock RC of the buffer 22) is executed.
This is the part that reads out the data stored in the buffer 22. This read data will be output from the authority as serial data to be transferred to the next station.

The preamble length adjustment algorithm, which is the core of the control executed by the clock phase control section 26, will now be described in detail.

First, in this embodiment, (1) The standard value of the length of the preamble PA set in the network (hereinafter, for convenience, this length will be referred to as PA) is 5 symbols as described above. It is.

[0050] (2) This preamble length PA 4≦PA≦6 Adjust to the range of

(3) The buffer 22 has a buffer capacity ±
It is a 5-bit buffer, of which ±3 bits are used as thresholds to perform preamble length adjustment.

[0052] It is assumed that. In this case, "0" of the buffer is the center of the buffer, and its "+" direction is considered to be the output phase delay.

Now, under these assumptions, buffer 2
2, that is, the preamble length detected by the preamble length detection section 25 is PAi [symbol], and this preamble length PAi
The preamble length adjusted by this device, that is, the length of the preamble actually output from the buffer 22, is PA [symbol], and the amount of buffer used each time in the buffer 22, that is, the amount of used buffer detection section 24
When the buffer usage amount detected by B [bits], in the clock phase control section 26, (a)
When −3≦B≦+3, PA=PAi (b) B<
-3, if PAi ≦5, then PA=PAi
+1 If PAi = 6, then PA = PAi (carry over to the next cycle without adjustment) (c) When B > +3, if PAi ≧5, then PA = PAi -1 If PAi = 4, then PA = PAi (without adjustment) The above-described clock phase control is performed so that the preamble length adjustment (carryover to the next cycle) is realized.

In other words, in such preamble length adjustment, the "reduction" of the input preamble length PAi is as follows:
This corresponds to the control to advance the phase of the read clock RC, and conversely, the "increase" in the input preamble length PAi corresponds to the control to delay the phase of the read clock RC (that is, to make it standstill), and the input preamble length "Maintaining" PAi means maintaining the phase of the operating clock as the authority issued from the internal clock source 21, and temporarily storing data (preamble) in the buffer 22 using the clock of this maintained phase (this becomes the clock RC). Since it corresponds to read control, in the relevant clock phase control section 26, the detection output B of the used buffer amount detection section 24 is lower than the above threshold value (B<-3), and the detection output PAi of the preamble length detection section 25 is When it is below the reference value (PAi ≦5), the internal clock source 21
The phase of the clock generated from is delayed by the amount by which the preamble is increased by one symbol (PA=PAi +1), and the detection output B of the used buffer amount detection unit 24 exceeds the above threshold (B>+3), and the preamble length When the detection output PAi of the detection unit 25 is equal to or higher than the reference value (PAi ≧5), the phase of the clock generated from the internal clock source 21 is reduced by one symbol of the preamble (PAi
= PAi -1), otherwise,
Control is performed to maintain the phase of the clock generated from the internal clock source 21 at the standard phase as the authority.

The increase/decrease in the number of preamble symbols determined by the values of the used buffer amount B and the input preamble length PAi as described above is summarized as shown in FIG.

Therefore, the operation of this embodiment device is as follows: (1) After the preamble for one frame is detected from the input serial data to the authority, the buffer amount B detected through the used buffer amount detection section 24 is Ga-
If it is within the threshold value, such as 3≦B≦+3 (case (a) of the above algorithm), the clock generated from the internal clock source 21 is directly added to the buffer 22 as the read clock RC. Therefore, in this case, the preamble length PAi of the frame is unchanged, and the preamble length PAi of the frame is unchanged.
=PAi and is transferred as is to the next station.

(2) Similarly, when the buffer amount B detected by the used buffer amount detection unit 24 falls below the lower limit threshold, such as B<-3 (case (b) of the above algorithm), The preamble length PAi detected through the preamble length detection unit 25 is further referred to, and if this value PAi has not been previously adjusted in the increasing direction, that is, if PAi ≦5, the above-mentioned operation by the clock phase control unit 26 is performed. Through the phase control, the input preamble length PAi is increased by one symbol and transferred to the next station as PA=PAi +1 (=5 or 6). Furthermore, if it is recognized that the preamble length PAi referred to above has been previously adjusted in the same increasing direction, that is, PAi
= 6, no such increase occurs and P
It is transferred to the next station as is as A=PAi (=6) (*1 in Figure 2).
”).

(3) Similarly, when the buffer amount B detected through the used buffer amount detection unit 24 exceeds the upper limit threshold, such as B>+3 (case (c) of the above algorithm), the preamble is The preamble length PAi detected through the length detection section 25 is further referred to, and if this value PAi has not been previously adjusted in the direction of reduction, that is, if PAi ≧5, the above-mentioned process by the clock phase control section 26 is performed. Through phase control, the input preamble length PAi is reduced by one symbol and transferred to the next station as PA=PAi -1 (=5 or 4). Furthermore, if it is recognized that the preamble length PAi referred to above has been previously adjusted in the same direction, that is, PAi
= 4, no such increase occurs and P
It is transferred as is to the next station as A=PAi (=4) ("*2" in Figure 2).
”).

The above process is repeated for each frame of input serial data.

FIG. 3 shows the transition of the preamble length PA adjusted based on the above operation at each of these stations, assuming three consecutive stations in which such an embodiment device is installed.
The example is shown in correspondence with the buffer amount B each time.

As shown in FIG. 3, the preamble length PA adjusted by the first station based on the above algorithm
(see Figure 3(a)) is taken over as the input preamble length PAi to the second station for each cycle (frame), and is further adjusted based on the above algorithm at the second station. However, "*2" is shown in Figure 3(b).
As shown with a mark (corresponding to the "*2" mark in FIG. 2), the buffer amount B exceeds the upper limit threshold (+3 bits),
In the conventional case, the adjustment should be made from "4 symbols" to "3 symbols", but in this embodiment, the recognition of "previously, the adjustment was made in the same direction of reduction" in (3) above is changed. Based on this, further reduction adjustments to the preamble length of the cycle (frame) are refrained from being made. Then, in the next cycle (frame) in which the buffer amount B exceeds the upper threshold (+3 bits) and the input preamble length PAi has not been adjusted in the direction of reduction before then, this preamble is Long reduction adjustments are now carried forward. Therefore, the possibility that the preamble length is adjusted to be shorter than necessary (for example, 3 symbols or less) or longer (for example, 7 symbols or more) is extremely low. Of course, as long as the preamble length is not adjusted to be shorter than necessary, there is no need to worry about the aforementioned data destruction.

In FIG. 3, the transition angle θ of the line showing the transition of the buffer amount B corresponds to the frequency difference with the previous station (the frequency difference of the clocks emitted from each internal clock source). , the smaller the angle θ, the smaller the frequency difference between these stations, and the larger the angle θ, the larger the frequency difference between these stations. Incidentally, FIG. 3(c) in which the angle θ is in the negative direction shows that the frequency of the third station is higher than the frequency of the second station. Additionally, m1, m2, m
3 indicates the amount of buffer consumption per cycle due to the frequency difference between each station.

In any case, it can be seen that according to this embodiment, the preamble length adjustment is not repeated for the same frame, and the resistance against data destruction etc. is greatly improved.

FIG. 4 illustrates, for reference, a circuit that implements preamble length adjustment based on the above-described algorithm for a portion of the buffer 22 and the clock phase control section 26.

That is, in this FIG. 4, 30 is the three DF/F (D
The data buffer section 31, which is composed of a type flip-flop (type flip-flop), operates based on the write clock WC extracted by the clock extraction section 23.
WC that distributes clocks to the above three D-F/Fs of 0
(write clock) distribution circuit, and in this example,
The data buffer section 30 and the WC distribution circuit 31 constitute the buffer 22. WC distribution circuit 31
An example of the configuration is shown in FIG.

Further, in FIG. 4, reference numeral 32 denotes an RC (read clock) distribution control circuit that corresponds to and constitutes a part of the clock phase control section 26. In this RC distribution control circuit 32, the clock phase control section 26, an output enable signal (OUT Enable) for each of the three D-F/Fs constituting the data buffer unit 30 is formed and output. For details of this RC distribution control circuit 32, an example thereof is illustrated in FIG.

Incidentally, the RC distribution control circuit 32 shown in FIG.
Now, a shift register equipped with a control mode switching function using signals S0 and S1 and a D-F/F (D-type flip-flop) that latches the output of the shift register based on the read clock RC are used to perform the required operation. Figure 7 shows the relationship between the control mode settings and the contents of the signals output from each D-F/F.
The relationship is shown in the table below.

Furthermore, the logical contents of the mode setting signals S0 and S1 shown in the table of FIG.
), H (High)”, “H (High), H (High
h)", "L (Low), L (Low)" are the used buffer amount B (detected by the used buffer amount detection section 24) added to the clock phase control section 26, and the preamble length of the input data PAi (detected by the preamble length detection section 25) is set based on the algorithm shown in FIG. 8.The algorithm shown in FIG.
This is none other than the preamble length adjustment algorithm described above. A device for setting the logical contents of the mode setting signals S0 and S1 using such an algorithm can be realized in any form, whether by software or hardware.

FIG. 9 shows a general example of the operation of the circuits illustrated in FIGS. 4 to 6.

That is, if input data is now written to the data buffer unit 30 through the WC distribution circuit 31 in the manner shown in FIG. In the read operation when the symbol number adjustment is "0 (PA=PAi)" in No. 2, the RC distribution control circuit 3
2 (clock phase control section 26), the written contents are outputted as they are from the data buffer section 30 (buffer 22) in the manner shown in FIG. 9(b). However, if the conditions for adjusting the number of symbols to "-1 (PA=PAi -1)" in FIG. 2 are met, or if the number of symbols is adjusted to "+"
1 (PA=PAi +1)", the RC distribution control circuit 32 (clock phase control section 26) performs the shift operation shown in FIG. 7, for example, as shown in FIG. 9C. , reverse shift (advancing the phase) or stepping (delaying the phase) control is performed, respectively.
The preamble length of the data output from 2) is also shown in Figure 9.
Good adjustment can be achieved in the manner shown in (c).

Next, the possibility of preamble loss in the preamble length adjustment method described above will be considered below.

◆Consideration 1 Now, as a simple model in which preamble loss may occur, assume a case where all frequency differences Δf between stations are equal, as shown in FIG. 10.

At this time, the allowable deviation of the station frequency of each station is ±
If ΔFppm, the station frequency F1 of the first station 1 and the nth
As shown in FIG. 11, with the station frequency Fn of station n,
The maximum frequency difference is 2ΔF. Also, at this time, since the frequency difference Δf between each station is equal, the buffer overflow periods of all stations are the same, and in the worst case, the maximum number of carryovers for preamble length adjustment described above (for example, as shown in FIG.
The number of consecutive carryover processes (as marked with "*2" in (b)) is (n-1), if this is N.
It becomes a cycle. That is, N=n-1=2ΔF/Δf
．． ．． ．． (1) Also, the buffer consumption per cycle m due to the frequency difference Δf (m1, m2 shown in FIG. 3)
, m3), one cycle is usually set to 15625 bits, so m=1.5625×0.01×Δf [bit/cyc
[le] Furthermore, if the preamble length adjustment unit is 1 symbol (=5 bits) as described above, the preamble length adjustment period is T, and therefore, the maximum number of carryovers (consecutive numbers) of the above preamble length adjustment The ratio between N and this adjustment period T is given by the formula (1),
From equation (2), it becomes.

Here, the condition that the preamble length PA does not decrease below 4 symbols is that the number of cycles (number of frames) within the adjustment period T is the maximum number N of carryovers of the adjustment.
There is plenty of room for this. That is, the above ratio N
/T represents this margin, and generally,
This margin is N/T<1
．． ．． ．． If (4), the condition that the preamble length PA does not decrease below 4 symbols is satisfied. Incidentally, the above equation (3) means that if ΔF<±160 ppm, the preamble length PA is always set between 4 and 6 symbols, and preamble loss cannot occur.

According to equation (4), it appears that as the number N of carryover adjustments increases, the margin for maintaining the preamble length between 4 and 6 symbols decreases; In this case, the condition for increasing the carryover number N is that the frequency difference Δf between each station becomes smaller.If the frequency difference Δf between each station becomes smaller in this way, the above-mentioned adjustment period T also becomes longer (as described above). (2)
(see formula). In other words, this means that even if the number of carryovers N in the adjustment described above increases, the value of the number N of carryovers that is allowed under the condition that formula (4) is satisfied also increases, and the preamble is adjusted according to the previous algorithm. As long as length adjustments are made, it seems that the relationship expressed in equation (4) will not break down in reality.

In addition, in such a preamble length adjustment method, when the preamble length PA adjustment operation continues for n cycles, the number of buffer bits required for the next cycle carryover adjustment of the preamble length PA is at most 2.
It is sufficient to secure the number of bits caused by the allowable deviation of ΔF. In other words, if ΔF<±100ppm, then the number of bits is b=1.5.
625×2ΔF×0.01=4 [bit]. Incidentally, in the above example, the minimum threshold bit number when performing one symbol (=5 bits) adjustment is ±3 bits, and by adding this bit number b to this, the buffer 22 of the above embodiment device can be adjusted. The required minimum number of bits is determined as ±7 bits.

By the way, according to this consideration 1, as long as the above preamble length adjustment method is adopted, FIGS.
Although it was concluded that preamble loss cannot occur even in the case shown in 1, the model discussed here is not necessarily the worst case under all circumstances. In other words, referring to FIGS. 10 and 11, there are k (k<n) consecutive stations where the frequency difference Δf has positive polarity, and then at the (k+1)th station, the frequency difference Δf once becomes negative polarity. Then, the station frequency returns to the original (the station frequency becomes the same as the station frequency F1 of the first station 1)
Even if something like this happens, the number of carryovers (consecutive number) N accumulated up to that point will not be reset to "0", and the accumulated value will be the number of carryovers (consecutive number) at subsequent stations.
This is because it is added to N.

Therefore, as consideration 2, the following case will be further considered.

◆Consideration 2 Here, for the above-mentioned reason, as a model in which preamble loss is considered to occur more easily, the station frequency (that is, the transmission frequency of serial data) is changed once in the middle as shown in FIG. When returns to the original state, and Fig. 12(B)
If the station frequency returns to its original value twice during the process, as shown in
Assume each. Incidentally, the more times the station frequency returns to its original state midway, the more the overall frequency difference Δ
Since f becomes larger, the above adjustment period T becomes shorter (
(See equation (2) above), and the margin against preamble loss also decreases (see equation (4) above). However, since the number of times the frequency returns in this way also contributes to the reduction of the number of adjustment carryovers (successive number) N, simply because the number of returns is large does not necessarily mean that it will be the worst case, and the number of times the frequency returns is It is considered that the worst case occurs when a certain number of times is reached.

First, the model shown in FIG. 12(A),
In other words, let us consider the case where the station frequency returns to its original value once during the process.

First, from the relationship shown in FIG. 11 and FIG. 12(A), Δf・a1+Δf・a2−Δfb≦2ΔF, and even in the worst case, the frequency difference Δ when the frequency returns to the original value halfway is
fb becomes Δfb=(n-2)Δf-2ΔF.

Therefore, if Tb is the period in which the frequency returns to its original value and the preamble length adjustment is reset in the manner shown in FIG. , the frequency difference Δf is Δf=(320/Tb+2ΔF)/(n-2)
．． ．． ．． (5).

On the other hand, since the preamble length adjustment period T in this case is also based on the equation (2) above, rearranging it based on the above equation (5) gives T=(n-2)/(1 /Tb+2ΔF/320)
．． ．． ．． (6) becomes.

[0084] Here, if the maximum number of carryovers (consecutive number) of preamble length adjustment in this case is N as described above, the number of carryovers N is, as is clear from FIGS. 12(A) and 13, N. =a1+a2-N/Tb Therefore, N=(a1+a
2) Tb/(1+Tb). ．． ．．
(7) Therefore, if we take the ratio of these adjustment carryover numbers N and adjustment period T to find the future margin, we get (6)
According to the formula, (7).

By the way, this shows a monotonous decrease when ΔF<160, and when the frequency returns by 2ΔF, that is, when it takes the minimum value of Tb=5/(1.5625×0.01×2ΔF), the corresponding The ratio N/T is the minimum value (worst). Therefore, in this case, Even in this case, the condition of equation (4) above,
That is, it can be seen that N/T<1 is satisfied.

Next, consider the model shown in FIG. 12(B), that is, the case where the station frequency returns to its original value twice during the process.

[0087] In this case, by setting the reset period when returning for the second time to Tb', it can be considered as an extension of the model shown in FIG. Assuming that the number (consecutive number) is N, the carryover number N is, as is clear from FIGS. 12(B) and 13, N=a1+a2+a3-N/Tb-N/Tb' Therefore, N=(a1+a2+a3)/ (1+1/Tb+1/Tb
')． ．． ．． (9) becomes.

By analogy with the model shown in FIG. 12(A) above, in the case of the model shown in FIG. 12(B), the above ratio N/T reaches its minimum value when . (Worst) At this time, the above carryover number N
is N=(a1+a2+a3)Tb/(Tb+2),
In addition, the frequency difference Δf is calculated as Δf=(
640/Tb+2ΔF)/(n-3),
In the end, the degree of margin in this case, that is, the ratio N/T between the number N of adjustment carryovers and the adjustment period T, is as follows. Although N/T=1 is closer to 1 than in the previous examples, the condition of equation (4) is satisfied in this case as well.

Based on the results of Consideration 2 above, assuming that the frequency returns x times, generalizing the value of the ratio N/T above, we get N/T(x)=(x+1)/(x+160/ΔF )
．． ．． ．． (11).

According to this equation (11), the value of N/T is
It can be seen that as x increases, it approaches "1", but as long as ΔF<160, it never becomes larger than "1".

As a result, according to the preamble length adjustment method according to the present invention using the algorithm described above, the station frequency tolerance ΔF of each station connected to the network can be adjusted to ±1.
00 ppm or less, the preamble length PA can always be adjusted and set in the range of 4 to 6 symbols in all cases. That is, preamble loss cannot occur.

Finally, as support for the results of these considerations, FIG. 14 shows simulation results under various conditions using the embodiment apparatus shown in FIG. 1. For comparison, simulation results using a conventional "limit smoother" and a "centering smoother" under the same conditions are also shown here.

As is clear from FIG. 14, in the conventional "limit smoother", even under simulation condition 1, where the station clock deviation (station frequency deviation) is random at ±50 ppm, the preamble length PA is 1 to 1. 3 symbols, and even with the conventional "centering smoother", depending on the combination of station clock deviations as in simulation condition 2, the preamble loss may be 3 symbols.
In contrast, in the device of the above embodiment, even under more disadvantageous conditions such as simulation conditions 3 and 4, as well as simulation conditions 1 and 2, all stations , in all cycles, the preamble length PA falls within the range of 4 to 6 symbols.

From the above results, it has been proven that the preamble length adjustment method according to the present invention is an extremely reliable method that does not cause data destruction or even excessive reduction of the preamble length.

[0095] In the above embodiment, (1)
The standard value of preamble length PA is 5 symbols.

(2) Adjust this preamble length PA to a range of 4≦PA≦6.

(3) The buffer 22 is a buffer with a buffer capacity of ±5 bits (According to the previous consideration, ±7 bits was determined as the minimum number of bits required), of which ±3 bits is used as a threshold. , perform preamble length adjustment.

[0098] However, the number of symbols or bits determined as the standard value of these preamble lengths,
Settings such as the adjustment range of the preamble length, the buffer capacity of the buffer to be used, and furthermore, the threshold value for implementing the preamble length adjustment are not limited to these, and may vary depending on the applied network or the applied network. It can be determined arbitrarily depending on the actual situation of the station.

[0099] Furthermore, the device itself illustrated in FIG. 1 can be implemented in any manner, including hardware.
Or, whether it is by software, as long as the above-mentioned functions of each part are basically satisfied, the system shown in Figure 4
- This may be realized in any form without being limited to the example shown in FIG.

[0100]

[Effects of the Invention] As described above, according to the present invention, the length of the preamble included in an input frame is monitored, and there are frames that have been adjusted in the same direction to increase or decrease the length of the preamble. If it is determined that the preamble length has been adjusted in the same direction as above, the preamble length adjustment for the frame is refrained from and the next frame is adjusted. Since the adjustment of the preamble length is carried over from frame to frame, the preamble length adjustment will not be repeated for the same frame, and in any case, the preamble length can be adjusted within a suitable length range. will be able to maintain it. This causes not only buffer memory overflow and underflow, but also
Always stable token passing without any data corruption etc. will be realized.

Further, according to the present invention, these excellent functions can be realized with a simpler and smaller-scale configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an independent synchronous serial data communication device according to the present invention.

FIG. 2 is a chart listing preamble length adjustment modes performed by the apparatus shown in FIG. 1;

FIG. 3 is a time chart showing an example of a preamble length adjustment operation between three consecutive stations when the device shown in FIG. 1 is applied to each station connected to the network;

FIG. 4 is a block diagram showing a specific configuration example of part of the buffer and clock phase control section shown in FIG. 1;

FIG. 5 is a block diagram showing an example of a configuration of the WC (write clock) distribution circuit shown in FIG. 4;

6 is a block diagram showing a configuration example of the RC (read clock) distribution control circuit shown in FIG. 4; FIG.

FIG. 7 is a table showing operating characteristics of this RC distribution control circuit.

FIG. 8 is a flowchart showing how to set the operation mode of the RC distribution control circuit (shift register).

FIG. 9 is a time chart showing an example of the operation of the circuit shown in FIGS. 4 to 6;

FIG. 10 is a block diagram that defines each station frequency difference Δf between a plurality of stations as a model for consideration.

FIG. 11 is a time chart schematically showing a frequency deviation accumulation mode assuming that all the station frequency differences Δf are equal, as a case in which preamble loss may occur.

FIG. 12 is a time chart schematically showing a frequency deviation accumulation mode assuming a case in which the station frequency returns to the original value midway, which is a case in which preamble loss is more likely to occur.

13 is a time chart showing the relationship between the preamble length adjustment maximum carryover number N and the preamble length adjustment period T in the case shown in FIG. 12. FIG.

FIG. 14 is a chart listing simulation results regarding preamble length adjustment of the device shown in FIG. 1;

FIG. 15 is a block diagram illustrating the actual situation in which the station frequencies of each station do not completely match in a communication network where each station operates in independent synchronization.

FIG. 16 is a time chart illustrating that a phase shift occurs in transmitted serial data between stations due to the station frequencies that do not match.

FIG. 17 is a block diagram showing a configuration example of a conventional independent synchronous serial data communication device.

[Explanation of symbols]

Claims (3)

[Claims] Claim 1: When a plurality of stations connected to a communication network operate in independent synchronization, the cumulative phase difference of serial data generated due to the difference in frequency of each station is attached to each frame of the serial data. In a preamble length adjustment method in a communication network that adjusts and absorbs by increasing or decreasing the length of a preamble to be transmitted, each station may increase or decrease the length of the preamble for the same frame by increasing or decreasing the length of the preamble in the same direction. 1. A method for adjusting a preamble length in a communication network, the method comprising refraining from increasing or decreasing the length of the preamble regarding the frame when the frame is used. [Claim 2] The length of the preamble is increased or decreased using FIFO.
The allowable usage of the buffer is ±m (m is an integer), the length of the preamble input to the buffer is PAi, the length of the preamble output from the buffer is PAi, and the length of the preamble output from the buffer is PAi. When the standard value of the preamble length is n (n is an integer), the increase or decrease in the length of the preamble is as follows: (a)
When −m≦B≦+m, PA=PAi (b) B
When <-m, if PAi ≦n, then PA=PA
i +1 PAi =n+1 then PA=PAi (c) B
>+m, if PAi ≧n then PA=PA
2. The preamble length adjustment method in a communication network according to claim 1, wherein if i-1 PAi = n-1, then PA=PAi. 3. An internal clock source for generating a clock of a predetermined frequency for serial data transmission; buffer means for temporarily storing the serial data in FIFO format; and extracting the transmission clock from the input serial data;
a clock extraction means for writing the serial data into the buffer means based on the extracted clock; a first detection means for detecting the amount of data stored in the buffer means each time; and a preamble included in the input serial data. a second detection means for detecting the length of the first
Based on the detection output of the second detection means, when the detection output of the first detection means is less than a predetermined amount and the detection output of the second detection means is less than or equal to a reference value, a clock is generated from the internal clock source. delay the phase of the first clock.
When the detection output of the second detection means exceeds a predetermined amount and the detection output of the second detection means exceeds a reference value, the phase of the clock generated from the internal clock source is advanced;
At other times, control is performed to maintain the phase of the clock generated from the internal clock source at a standard phase for serial data transmission, and data stored in the buffer means is controlled based on the phase-controlled clock. an independent synchronous serial data communication device, comprising: clock phase control means for reading out serial data as output serial data to a next station;