JPH04212767A - Digital recorder - Google Patents

Abstract

PURPOSE:To offer a digital recorder by which the editing of sound data is executed without accessing the address of a sound data storage means such as a hard disk or a magneto-optical disk, for instance, where the sound data is stored, every time. CONSTITUTION:By providing a means for storing the discrimination information of an event formed by plurally dividing the sound data stored in the sound data storage means and an event address table including a storage position, the editing of the sound data is performed in event units.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recorder capable of digitally recording, reproducing, and further editing audio signals.

0002

2. Description of the Related Art Conventionally, as a method of recording, reproducing, and editing audio signals, analog audio signals are magnetically recorded on a magnetic tape and then reproduced and edited. However, since such conventional techniques rely on analog recording and playback, deterioration in sound quality is unavoidable, and the deterioration becomes particularly noticeable when dubbing a previously recorded audio signal.

Furthermore, since magnetic tape is used as a recording medium, there are problems in that it takes time to reach the desired editing point, and there is the problem of physically cutting and pasting the recorded portion of the magnetic tape, or editing the edited portion by other means. There is also the problem that editing can only be done after copying the file to the location.

Although the problem of sound quality deterioration can be addressed by digitizing the recording method on magnetic tape,
The drawbacks associated with the freedom of cueing and editing that arise from the use of sequential access recording media cannot be eliminated simply by digitization.

Therefore, in recent years, proposals have been made to solve the conventional problems by performing disk recording using a Winchester type hard disk as a recording medium (for example, JAS Journal '89
・Refer to April issue, pages 16 to 22, "Trends in Digital Audio Workstations (DAW) - From the January Regular Meeting of the AES Japan Branch").

[0006]

[Problems to be Solved by the Invention] However, when editing audio data, accessing each address of the hard disk where the audio data is stored becomes a very complicated processing procedure.

[0007] An object of the present invention is to store audio data without accessing each address of audio data storage means such as a hard disk or a magneto-optical disk.
An object of the present invention is to provide a digital recorder capable of editing audio data.

[0008]

[Means for Solving the Problems] According to the digital recorder according to claim 1, there is provided an audio input/output means for inputting and outputting audio data, and an audio recording device for storing digital audio data supplied from the audio input/output means. A digital recorder is provided that includes a data storage means and a means for storing an event address table including event identification information and storage locations formed by dividing the audio data stored in the audio data storage means into a plurality of parts. .

A digital recorder according to a second aspect of the invention further comprises means for storing a control track in which identification information of events included in the event address table is arranged in the playback order of the events, in addition to the configuration of the first aspect. Be equipped.

[0010] The digital recorder according to claim 3 further comprises a reproduction schedule table including a start address and an end address on the audio data storage means of each of a plurality of events arranged in reproduction order. further comprising means for storing.

In the digital recorder according to claim 4, there is provided an audio input/output means for performing audio input/output operations corresponding to a plurality of tracks, and a plurality of audio input/output means capable of storing digital audio data supplied from the audio input/output means. audio data storage means having a storage area for tracks; means for storing an event address table including event identification information and storage locations formed by dividing the audio data stored in the audio data storage means into a plurality of parts; A digital recorder is provided that includes means for storing individual control tracks in which event identification information included in an event address table is arranged in the event playback order for each track.

[0012] In addition to the configuration of claim 4, the digital recorder according to a fifth aspect of the present invention provides, in addition to the configuration of the fourth aspect, when the individual control track for a plurality of tracks is divided into a plurality of parts on the time axis, each divided individual control track is divided into a plurality of parts on the time axis. Further comprising: means for creating a total control track consisting of arranging the identification information of the control tracks in a playback order; and means for rewriting the identification information of events included in the individual control track and the arrangement thereof in accordance with the total control track. do.

[0013]

[Function] In the digital recorder according to claim 1, since the event address table has a storage location on the audio data storage means for each event, editing of the audio data can be done for each event, and the audio data can be edited one by one. There is no need to access the address of the data storage means.

In the digital recorder according to the second aspect of the present invention, the control means of the digital recorder such as a CPU refers to the control track, confirms the arrangement order of the events on the time axis, and writes the event address table in accordance with this order. By reading, the storage addresses of the audio data storage means for each event can be generated in the playback order, and necessary playback can be realized.

In the digital recorder according to the third aspect, the control means of the digital recorder such as a CPU refers to the reproduction schedule table, confirms the start address and end address of the event to be reproduced, and reads the data from the audio data storage means. Since the event can be read out, it is possible to easily switch the reproduction of the event.

[0016] In the digital recorder according to claim 4, like the digital recorder according to claim 1, since it has an event address table, it is not necessary to access the address of the audio data storage means each time when editing. do not have. In addition, the control means of the digital recorder such as the CPU refers to the individual control track, confirms the position of the event on the time axis, and reads out the event address table in accordance with this order, thereby controlling the audio of each event for each track. By generating storage addresses on the data storage means in the reproduction order, necessary reproduction can be realized for each track.

In the digital recorder according to claim 5, the identification information and arrangement of events in the individual control track are automatically rewritten simply by creating a new total control track or changing the total control track. When editing is changed, there is no need to manually rewrite the event identification information and its arrangement in the individual control track.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the digital recorder of the present invention will be described below with reference to the drawings.

<Overall Configuration> FIG. 1 shows the overall configuration of an embodiment of the digital recorder of the present invention, and in this embodiment, it is possible to record and play back up to three tracks at the same time. . As shown in the figure, the entire system is divided into a CPU section (the left part in the figure) and a DMA unit (audio recording/playback processing device) (the right part in the figure).

The CPU section includes a CPU 1, a program ROM 2 that stores a program (details will be described later) that defines the operation of the CPU 1, and an area 3 that stores various data.
An area for storing the disk access pointer of a track, and identification information (hereinafter referred to as an "event") for each segmented audio data (hereinafter referred to as "event") when the audio data stored on the hard disk 12 is manually or automatically segmented into multiple segments. An area for storing an event address table including event number) and storage location (original track number, start point, and end point), and an area for arranging event identification information included in the event address table in the event playback order for each track. An area for storing individual control tracks consisting of individual control tracks, and an area for storing identification information of each divided individual control track (hereinafter referred to as "total event") when multiple tracks of individual control tracks are divided into multiple parts along the time axis. A RAM 3 including an area for storing total control tracks arranged in playback order, a work area, etc., and a CPU.
A keyboard 4 including various function keys, data input keys, etc., which is a peripheral device connected to the I/O port of 1.
, a display device 5 that includes a CRT or LCD and its driver and performs various displays.

As will be described later, during real-time operation (recording/playback, etc.), the CPU 1 uses the DMA unit's address bus and data bus as needed.
It controls each component of the MA unit, and performs operations such as rearranging data blocks and manipulating disk access pointers during editing. From the keyboard 4, as described later, each track (hereinafter referred to as Tr) can be recorded/recorded.
You can set the playback mode, start, stop, locate, specify edit points, etc. Program ROM2,R
The address terminal of AM3 is connected to the CP via the address bus.
An address signal is sent from U1, and its output terminal is connected to CPU1 or to transceiver 7 via a data bus.

That is, in order to connect the CPU section and the DMA unit, the buffer 6 and the transceiver 7 are connected to the DMA unit.
located within the unit. Buffer 6 is connected to CPU 1 via an address bus, and further connected to an address bus within the DMA unit. Transceiver 7 is a CPU
1 via a data bus, and further connected to a data bus within the DMA unit.

The DMA unit includes an audio input/output device 8-1 for Tr1 and an audio input/output device 8-2 for Tr2.
, Tr3 are provided with audio input/output devices 8-3, and analog audio signals can be input and output independently to each of them.

Inside each audio input/output device 8-1 to 8-3, in addition to a converter for selectively performing A/D conversion and D/A conversion, a low-pass filter for removing sampling noise, and a sampling filter are included. It includes a clock circuit that generates a clock at regular intervals. These audio input/output devices 8-
1 to 8-3, when the track is set to record state, the analog audio signal from the outside is appropriately filtered at each sampling period, and then the A/
D conversion is performed to obtain digital audio data. Conversely, if the track is set to the play state, the digital audio data read out in advance is D/D at each sampling period.
After A conversion and appropriate filtering, the signal is output as an analog audio signal.

[0025] Each audio input/output device 8-1 of Tr1 to Tr3
~8-3 are connected to the corresponding buffers 9- through the data bus.
1 (BUF1), buffer 9-2 (BUF2), and buffer 9-3 (BUF3), and exchange digital audio data.

The buffers 9-1 to 9-3 are Tr1 to T.
r3 respectively, and audio input/output devices 8-1 to 8-
3 is performed by a DMA controller 10 using a direct memory access (DMA) method.

Each of the audio input/output devices 8-1 to 8-3 is
During recording, the DMA controller 10 performs DMA transfer (single transfer) of digital data related to one sampling from the audio input/output devices 8-1 to 8-3 in the direction of the buffers 9-1 to 9-3 at the sampling period. (request) (sends DRQ signal (DRQ1 in Tr1, DRQ2 in Tr2, DRQ3 in Tr3)
)), DM
Response from A controller 10 (acknowledgement is T
DAK1 in r1, DAK2 in Tr2, D in Tr3
given from the DMA controller 10 as AK3)
Actual data transfer is then executed. During play, DMA transfer of digital data related to one sampling from the buffers 9-1 to 9-3 to the audio input/output devices 8-1 to 8-3 at the sampling period (single transfer)
A request is made from the audio input/output devices 8-1 to 8-3,
Data transfer is executed by the DMA controller 10 in the same way as in the case described above.

These buffers 9-1 to 9-3 have a capacity that can store digital audio data once or multiple times. For example, the RAM is divided into three into Tr1 to Tr3, and each ring buffer (last address and first address) is divided into three parts. By using it as a virtual connected buffer), FIF
It is configured to function as an O buffer.

Address designation for the buffers 9-1 to 9-3 is performed by the DMA controller 10 or the like via an address bus. That is, during DMA transfer, the address bus, data bus, and control signal line within the DMA unit are exclusively occupied by the DMA controller 10.

The buffers 9-1 to 9-3 are connected to a hard disk controller (hereinafter referred to as H) via a data bus.
Data is transferred to and from the hard disk 12 under the control of the hard disk 12 (hereinafter referred to as D controller) 11. The hard disk 12 and the HD controller 11 are connected via a data bus and a control signal line, and all read/write access to the hard disk 12 is performed by the HD controller 11.
It is done by. The hard disk 12 has Tr1 to Tr.
The DMA controller 10 has a storage area divided into three tracks of 3, and data transfer to and from buffers 9-1 to 9-3 is performed by a DMA controller 10. This causes an interrupt (
INT) to the CPU 1 and instructs the CPU 1 to transfer the next data block. CPU
1 is an interrupt signal IN from the HD controller 11.
When time T arrives, the DMA controller 10 and the HD controller 11 are set to a desired state or programmed, and then DMA transfer is performed. Details of this operation will be explained later.

During play, the DMA controller 10 reads out a pre-specified amount (for multiple sampling periods) of digital audio data from the hard disk 12, and then reads out a specified amount of digital audio data from one of the buffers 9-1 to 9-3. It operates to perform DMA transfer (block transfer) to the buffer, and during recording, reads a pre-specified amount (multiple sampling cycles) of digital audio data from the specified buffer and transfers it to the specified position on the hard disk 12. It operates to perform DMA transfer (block transfer).

[0032] This hard disk 12 and buffer 9-1
9-3, the HD controller 11 sends a request signal DRE to the DMA controller 10.
Q (received as DRQ4 on the DMA controller 10 side), and when transfer is possible, an answer signal DACK is output.
By receiving (outputting as DAK4 on the DMA controller 10 side), an actual transfer state is entered.

[0033] In this way, the DMA controller 10
3 channels between the audio input/output devices 8-1 to 8-3 of Tr1 to Tr3 and the buffers 9-1 to 9-3 (C
H1 to CH3) data transfer, and one channel (CH4 to be described later) data transfer between any of the sequentially selected buffers 9-1 to 9-3 and the hard disk 12, for a total of 4 channels. Performs divided data transfer operation.

In order to manage the functions and operations of each component in the DMA unit, the CPU 1 not only provides address signals to the buffer 6 via the address bus, but also sends designation signals for each component to the decoder 13 via the buffer 6. supply,
The respective designated signals CS are transmitted to each audio input/output device 8-1 to 8-.
3. Buffers 9-1 to 9-3, DMA controller 10
, is given to the HD controller 11. At the same time, various data are exchanged with the CPU 1 via the transceiver 7 and the data bus.

Furthermore, each audio input/output device 8-
A designation signal WR designating whether to enter the record state (write state) or play state (read state) is applied to the IOWR terminals 1 to 8-3 via the buffer 6.

In addition, each buffer 9-1 to 9-3, DMA
This designation signal (write signal) WR and another designation signal (read signal) RD are also given to the controller 10 and HD controller 11 from the CPU 1 via the buffer 6, and the controller 10 and the HD controller 11 receive data from the respective components and read out data. Conversely, you will be able to write data. Further, the DMA controller 10 also outputs these designation signals RD and WR in the DMA transfer state. The relationship between these signals and the functions and operations of each component will be described later.

The DMA controller 10 outputs a DMA enable signal DMAENB as "1" when performing DMA transfer between each component. As a result, the output of the AND gate 14 to which this signal DMAENB is applied via the inverter 16 becomes "0",
Enabling signal E is applied to the buffer 6 and transceiver 7.
is given as "0", and data and addresses cannot be exchanged between the CPU section and the DMA unit. At this time, if a "1" signal is given to the AND gate 15 from the decoder 13, the output of the AND gate 15 becomes "1" and the wait signal WAIT is supplied to the CPU 1.

That is, when the CPU 1 is giving a predetermined signal to the decoder 13 to open the buffer 6 and the transceiver 7 in order to manage the DMA unit, that is, when the CPU 1 is giving a predetermined signal to the decoder 13 to open the buffer 6 and the transceiver 7, that is, when the CPU 1 is giving a predetermined signal to the decoder 13 at one input terminal of the AND gate 14, " 1
"When the signal is being supplied (CPU1 is supplying the buffer 9-1
~9-3, when outputting an address signal for accessing any of the DMA controller 10, HD controller 11, and audio input/output devices 8-1 to 8-3, the decoder 1
3 becomes active, and the output to one input terminal of each of AND gates 14 and 15 becomes "1"), and when the DMA transfer starts, a wait (WAIT) is applied to the CPU 1, and the DMA transfer is executed with priority. After the wait is released, the operation of the CPU 1 is restarted.

[0039] Conversely, the DMA controller 10
When executing DMA transfer, CPU1, for example,
Even if an attempt is made to access the MA controller 10, a wait signal WAIT is applied from the AND gate 15 and the CP
The execution cycle of U1 will be extended in the middle, and the buffer 6 and transceiver 7 will be closed during that time.

In the end, the CPU 1 can access each component of the DMA unit in the following ways: 1. The CPU 1 issues addresses for accessing each component of the DMA unit. 2. Signal DMAENB is inactive (“0”
) In other words, the data bus of the DMA unit is free. When the two conditions of
Processing can proceed without considering whether or not to access the unit.

Further, when the CPU 1 wants to immediately change the operating state of the DMA unit in response to a key input or control data trigger, the CPU 1 requests the DMA controller 10 to change the operating state of the DMA unit no matter what state the DMA controller 10 is in. A command DMAEND for interrupting DMA transfer can be output (this is given to the DMA controller 10 as an END signal).

<Configuration of Main Parts of DMA Controller 10> Next, an example of the configuration of the DMA controller 10 will be described. The DMA controller 10 has a transfer capability in which one bus cycle lasts several hundred nanoseconds. Therefore, the time required to transfer sampling data for three tracks is 1 to 2 microseconds.

When the sampling frequency fs is 48 KHz, the interval of one sampling time is approximately 21 microseconds, and most of the sampling time interval is the interval between the buffers 9-1 to 9-3, the HD controller 11, and the hard disk 12. It becomes possible to use the time for data transfer and programming of each component from the CPU 1.

Now, the main structure of the specific example is shown in FIG. This DMA controller 10 has an address buffer 1 on the input side (IN) connected to the address bus.
01 and an output side (OUT) address buffer 102. The contents specified by the register selector 103 change depending on the address signal applied to the address buffer 101 on the input side, and a desired register existing in the address register 104 and the control register 105 is specified.

The address register 104 and control register 105 have areas for four channels CH1 to CH4, and the channels CH1 to CH3 are located in the buffer 9.
A register for performing DMA transfer between -1 to 9-3 and audio input/output devices 8-1 to 8-3, and is a register for channel C.
H4 is a register for performing DMA transfer between a designated buffer among the buffers 9-1 to 9-3 and the hard disk 12.

The registers for each channel CH1 to CH4 in the address register 104 are stored in the corresponding buffer 9-1.
~9-3 and an area for storing at least the current address and start address of the designated buffer, and each channel CH1~ of the control register 105.
For example, control data specifying the direction of DMA transfer is stored in the CH4 area.

The contents of the address register 104 and control register 105 can be input/output to/from the data bus via the data buffer 106. A timing control logic 107, a service controller 108, and a channel selector 109 control each of these components.

The service controller 108 has a hard logic or microprogram control configuration, and receives signals from the timing control logic 107, audio input/output devices 8-1 to 8-3, and the HD controller 1.
The DMA request signals DRQ1 to DRQ4 from 1 and the CPU
Receives the DMA interruption command END (DMAEND) from 1 and responds (acknowledges) to each of the above components.
In addition to outputting signals DAK1 to DAK4 and a DMA enabling signal DMAENB indicating that DMA transfer is in progress, it issues various commands to the timing control logic 107 and outputs a channel select signal to the channel selector 109. The channel selector 109 selectively specifies a register corresponding to each channel CH1 to CH4 among the address register 104 and the control register 105.

The timing control logic 107 receives the designation signal CS from the decoder 13, the control signal from the control register 105, and the control signal from the service controller 108, and controls the input/output of the address buffer 102 and the data buffer 106. , operates the address incrementer 110 to increment the current address register of the designated channel in the address register 104.

<Overall Operation of CPU 1> The operation of this embodiment will be described below. Flowcharts showing the operation of the CPU 1 are shown in FIGS. 3 and 4. This is based on a program (software) stored in the program ROM 2. FIG. 3 shows the main routine, and FIG. 4 shows an interrupt routine executed in response to the arrival of the interrupt signal INT from the HD controller 11. .

First, in FIG. 3, the CPU 1 starts the main routine in response to power-on, and proceeds to step 3-
0 (hereinafter simply referred to as 3-0), various initial states are set. Then, in 3-1, key input is received, and 3
-2, determine what mode is set.

When the CPU 1 determines that the current play/record mode is selected, the process proceeds from 3-2 to 3-3 and sequentially selects and specifies the three tracks, and then proceeds to 3-4 to select and specify the operation mode of each track using the keyboard 4. In step 3-5, it is determined which operation, A/D conversion or D/A conversion, each audio input/output device 8-1 to 8-3 performs via the buffer 6 and decoder 13. The IOWR is applied and set while sequentially sending out the designation signal CS. For example, assume that Tr1 is in the play state (therefore, in the D/A conversion operation state), and Tr2 and Tr3 are in the record state (therefore, in the A/D conversion operation state). Figure 8
A conceptual diagram of the general operation when such a mode is set is shown in FIG.

Then, in 3-5, the buffer 9- for each Tr1 to Tr3 is sent to the DMA controller 10.
Initialize addresses 1 to 9-3. In other words, the address buffer 101, register selector 103, channel selector 109, etc. in FIG.
Initial setting data is input and set via the data buffer 106 while specifying each register (address register 104, control register 105) of CH3.

Here, the buffers 9-1 to 9-3 are used cyclically as ring buffers, and in the initial state, the start address and current address of each buffer 9-1 to 9-3 are (FIG. 8 schematically shows the state in which the start address and current address of each buffer 9-1 to 9-3 are stored and controlled in the address register 104 of CH1 to CH3. ).

[0055] Next, the CPU 1 executes the process 3-6,
Disk access pointers corresponding to each track Tr1 to Tr3 of the hard disk 12 existing in the work memory area in the RAM 3 are initialized (FIG. 8 shows the relationship between the storage area of the hard disk 12 and the disk access pointer). ).

Next, the CPU 1 controls each audio input/output device 8-1.
The A/D conversion operation or D/A conversion operation of ~8-3 is started (3-7). Subsequently, in 3-8, the HD controller 11 issues a software interrupt and issues a program request for data transfer between the hard disk 12 and any of the buffers 9-1 to 9-3.
must issue an interrupt INT to CPU1)
Executes the same process as when (described later).

Specifically, the operation according to the flowchart shown in FIG. 4 is executed in step 3-8. for example,
In this case, for Tr1, in order to DMA transfer digital signal data from the hard disk 12 to the buffer 9-1, T is used as a channel of the DMA controller 10.
Determine channel CH1 corresponding to r1 (4-1)
.

Next, the start address of this CH1 (
3-5) as the start address of CH4 (4-2). The operation on the DMA controller 10 side at this time will be described later. Next, in this case, the number of data transfers is calculated from the start address and current address of CH1 (4-3). now,
Since it is in the initial state, no data has been transferred to the buffer 9-1 regarding Tr1, and therefore,
Hard disk 1 in all memory areas of buffer 9-1
You can transfer data from 2. Of course, if there are multiple tracks at the time of play, the digital audio data stored in advance must be transferred from the hard disk 12 to multiple buffers at an early stage. It is also possible to perform DMA transfer for each track. Alternatively, the play/record operation may be started synchronously after full data is transferred from the hard disk 12 to the necessary buffers 9-1 to 9-3 in advance.

Next, in 4-4, in this case CH1
Copy the contents of the current address to the start address of CH4. In this case, the initial address becomes the start address.

[0060] In this way, the CPU 1 uses 4-1 to 4-4.
After performing each setting/control for the DMA controller 10, the process proceeds to step 4-5, where the disk access pointer of the current Tr1 is retrieved from the working memory of RAM3, and further, at step 4-6, the DMA controller 10
The operating mode of Tr1 (current play mode) obtained according to the contents of the CH1 area of the control register 105, the disk access pointer for this Tr1, and the data transfer from the hard disk 12 to the buffer 9-1 determined in 4-3. The HD controller 11 is programmed according to the number. The operation on the HD controller 11 side at this time will be described in detail later.

As a result, the HD controller 11 requests the DMA controller 10 to perform DMA transfer in the direction from the hard disk 12 to the buffer 9-1 (DR).
EQ), and the DMA controller 10 outputs the corresponding D
MA transfer will be executed. This operation will also be explained in detail later.

[0062] Subsequently, in 4-7, CPU1
The disk access pointer of Tr1 in the working memory of M3 is updated to the value that the disk access pointer will take as a result of executing the above-described transfer process. In other words, as can be seen from the above explanation, all data transfer between the hard disk 12 and the buffer 9-1 will be executed by the DMA controller 10, and the CPU 1 will transfer data between the hard disk 12 and the buffer 9-1.
The value that the access pointer of the hard disk 12 takes when the MA transfer is completed is set in 4-7. Then, the main routine (FIG. 3) is returned.

As will become clear from the explanation that follows, once the first interrupt routine (FIG. 4) is started and the HD controller 11 is operated once, every time the transfer of the data block specified by the CPU 1 is completed, , an interrupt is made from the HD controller 11 (the INT signal is
1), what CPU 1 does is record/
It only determines whether the playback operation has ended, whether there has been a key input, or whether a trigger specified in the control data has been activated.

[0064] That is, in 3-9, the CPU 1 refers to the disk access pointer (RAM3) and judges whether or not the memory area has been exceeded, that is, whether or not it has ended (3-10). If YES, each audio Input/output device 8-
Stops A/D conversion and D/A conversion operations of 1 to 8-3 (3-
11) and return to 3-1. If NO, the key input state is referred to (3-12), and if there is no change, the process returns to step 3-9 to check the disk access pointer, and the following steps 3-9 to 3-13 are repeated.

Then, if there is any change in 3-13, the process advances from 3-13 to 3-14, and the CPU 1
In order to temporarily suspend MA transfer and make new settings,
DMA stop command to controller 10 (DMAEN
D) is output. Next, follow the new input instructions, etc.
DMA controller 10, audio input/output devices 8-1 to 8-
3 is programmed (3-15), the program proceeds to 3-16 to restart the DMA operation, and after executing the interrupt routine of FIG. 4 in the same manner as 3-8 described above, the program returns to 3-9.

In this way, during play/record, the CPU 1 performs the initial settings for 3-4 to 3-8, and then performs the initial settings for 3-9, 3-10, 3-12, 3-13, and so on. 3-
14 to 3-16 repeatedly, and change instructions (for example, pause (A/D) for a certain track) on the keyboard 4.
, D/A interruption) or punch-in/out (A/D
, D/A operation switching), etc.), or in response to changes in control data obtained during editing, immediately interrupts DMA transfer control, changes the program, and then executes the same process again. works.

At step 3-2, if the CPU 1 determines that it is currently in the control track mode, the process proceeds from step 3-2 to step 3-17, where it converts the audio data stored in the hard disk 12 into an event. Converting to an event means dividing continuous audio data on the time axis into multiple parts by manual specification, etc., and assigning an event number to identify each divided audio data (event) and data indicating the divided section (start point and end point). The event number, start point, and end point are registered in the event address table (EAT) in RAM3. The start point and end point correspond to the start address and end address of the hard disk 12 where the event is stored. Examples of event address tables are shown in FIGS. 16, 26 and 28. The event address table will be explained later with reference to FIGS. 11, 12, 16, 26, and 28.

[0068] When the event creation is completed, at 3-18, the individual control track (ICT
) is created. ICT is made up of event identification information (event numbers) included in an event address table (EAT) arranged in the order of event reproduction for each track. The ICT creation process will be explained later in Figure 1.
8 and FIG. 19. Further, an example of ICT will be described later with reference to FIG. 20.

When the creation of the individual control track (ICT) is completed, the total event (TE) is designated at 3-19 based on a manual designation operation or the like. TE refers to each segment of data when ICT for multiple tracks is segmented into multiple segments on the time axis. TE designation means that the TE is given identification information (for example, TE1
, TE2, etc.) and total event table (TE2, etc.).
T). TET includes the start time and end time of each TE, as will be explained later with reference to FIG. 24.

When the designation of the total event (TE) is completed, a total control track (TCT) is created and executed at 3-20. What is TCT?
The identification information of E is arranged in the playback order. T
When the CT is executed, the event identification information (event number) and its arrangement included in the ICT are rewritten according to the TCT. Regarding TCT processing, see Figure 22 later.
Explain with reference to. Further, an example of TCT will be explained later with reference to FIG. 23. When the end of the control track mode is detected at 3-21, CPU1
In step 1, key input is checked again.

[0071] In 3-2, if the CPU 1 determines that it is currently in the edit (EDIT) mode, the process from 3-2 to 3
- Proceed to step 22, and decide which track and point to edit, and what kind of editing you want to do (for example, shift the timing of the sound recorded at a specified point for a certain period of time, make corrections, etc.)
The CPU 1 determines whether the content is to be deleted) and executes various editing operations (3-23). Although this editing work will not be described in detail, it includes programs for reading access points from the hard disk 12 for the HD controller 11 and DMA controller 10, transfer to the RAM 3, R
Various editing operations using the AM3, re-storing of the edited digital audio data onto the hard disk 12, designation of access points, etc. are executed under the control of the CPU 1. When the end of the editing work is detected in 3-24, the CP
U1 checks the key input again at 3-1.

<Operations of the audio input/output devices 8-1 to 8-3> Next, the operating states of the audio input/output devices 8-1 to 8-3 will be described with reference to FIG. This flowchart may be based on microprogram control or hard logic control, and various function implementation means can be selected.

Now, in 5-1, it is judged whether the designation signal CS of the audio input/output device has arrived (active) from the CPU 1, and if YES, 5-
In step 2, the CPU 1 sets the operating state (record, play, stop, etc.). This is done in response to steps 3-5 and 3-15 in the main routine of the CPU 1 in FIG.

[0074] Then, when the determination in 5-1 is NO, in 5-3 the audio input/output devices 8-1 to 8 are
5-3 to 5-4.
~ Proceed to the process of 5-9, and when it is determined that the play state is in progress, the process of 5-
Proceed to steps 10 to 5-15.

First, the operation of the audio input/output devices (in this case, audio input/output devices 8-2 and 8-3) set to the record state will be explained. In step 5-4, it is determined whether the sampling time has come, and this step 5-4 is repeated until the sampling time has come. The sampling time may be determined by providing a hard timer in each of the audio input/output devices 8-1 to 8-3, or by providing a common hard timer and determining the sampling time according to the output of each audio input/output device. You may make it work. As will be understood from the later explanation, each audio input/output device 8-1 to 8-3
It is also possible to have different sampling frequencies.

Now, if YES is determined in step 5-4, the applied analog audio signal is sampled and held (S/H) and A/D converted. Next, 5
-6, the DMA controller 10
The transfer request DRQ is activated and output.

The DMA controller 10 receives this request signal DRQ and outputs a response signal DAK to perform DMA transfer (detailed operation in this case will be described later).
. Therefore, the audio input/output devices 8-1 to 8-3 (in this case, the audio input/output device 8-2 or 8-3 in the record state)
If the judgment in 5-7 is YES, proceed to 5-8 and
The digital audio data obtained by /D conversion is output to the data bus and sent to the corresponding buffers 9-1 to 9-3 (in this case, buffers 9-2 or 9-3). Then, in step 5-9, the DMA transfer request DRQ is made inactive. Therefore, in the present case, the audio input/output devices 8-2 and 8-3 convert the externally applied analog audio signal into a digital audio signal every sampling period, and send the analog audio signal to the DMA controller 10 as described later. to the current addresses of buffers 9-2 and 9-3 respectively specified by
reference).

If it is determined that the play state is reached in 5-3, the process proceeds to 5-10, activates the DMA transfer request DRQ to the DMA controller 10, waits for the arrival of the response signal DAK from the DMA controller 10, and then proceeds to 5-10. −
11) Import digital audio data on the data bus (
5-12), make the above request DRQ inactive (
5-13). The operation of the DMA controller 10 at this time will be described later, but in this case, as shown in FIG. ) will be input and set to the audio input/output device 8-1 through the above operations. Then, it is determined whether the sampling time has come (5-14). Detection of the arrival of this sampling time is the same as described in 5-4.

[0079] If 5-14 is YES, 5-1
Proceeding to step 5, the analog audio signal is output to the outside after performing D/A conversion and low-pass filtering.

The operations at one sampling time in the case of the record state and the case of the play state have been explained above, but after the completion of each process in 5-9 and 5-15, the process returns to 5-1, and in the same manner, the operations are performed one after another in the same manner. and execute processing for the sampling time.

FIG. 9 shows an operation time chart of the audio input/output devices 8-1 to 8-3. In this case, the audio input/output device 8-1 of Tr1 is in the play mode, and the sampling time t and During sampling time t+1, a sampling request (DRQ) is generated, and the buffer 9 is
-1 to the audio input/output device 8-1, and a D/A conversion operation is performed in synchronization with sampling time t+1.

On the other hand, in this case, the audio input/output devices 8-2 and 8-3 of Tr2 and Tr3 are in record mode, and A/D conversion is performed in synchronization with sampling time t or t+1. , thereafter, a DMA transfer command is output to the DMA controller 10. and D
MA transfer is performed in the order of Tr2 and Tr3 (if there are simultaneous DMA requests, the priority is CH1>CH2>CH3)
>CH4) is executed, and the audio input/output devices 8-2 and 8-3 are transferred to the buffers 9-2 and 9-3.
Data will be transferred to.

<Operation of DMA Controller 10> Next, the operation of the DMA controller 10 will be described with reference to FIG. 6. The flowchart of FIG. 6 may represent that the service controller 108 of FIG. 2 operates under microprogram control, or the DMA controller 10 may realize its functions using hard logic.

First, at 6-1, the designation signal CS from the CPU 1 has arrived (is active).
If YES, it is determined whether the read signal RD or the write signal WR is given from the CPU 1. If the read signal RD is the read signal RD, the process proceeds to 6-3 and the address signal given via the address bus is The contents of registers 104 and 105 specified by
If so, the process proceeds to 6-4, where desired data is input and set to the designated register via the data bus. This 6
-3 and 6-4 processes are 3 of the main routine of CPU1.
-5, 3-15, etc. Therefore, 6-4
Through the process described above, desired data is set in each of the registers 104 and 105 in FIG.

[0085] Then, DMA from CPU1 like this
When the access and programming to the controller 10 is completed, the designated signal CS becomes inactive, and the signals from 6-1 to 6
The process will proceed to -5.

6-5, each audio input/output device 8-1 to 8
- Whether DMA transfer requests DRQ1 to DRQ3 have come from HD controller 11,
(DRQ4) is received, and if a request is received from either, proceed to 6-6 and send the DMA enable signal DMA.
Set ENB to “1” (active) and connect the address bus and data bus in the DMA unit to DMA controller 1.
0 exclusively, and does not accept access from CPU1.

[0087] Subsequently, in the case of a plurality of requests, channels are selected according to the priority order of channels CH1 to CH4 (6-7). For example, in the example of FIG. 9, immediately after sampling, the audio input/output devices 8-2 and 8 of Tr2 and Tr3
The data transfer request from Tr-3 is made at the same time, but since Tr2 has a higher priority, the DMA transfer for CH2 is performed first. Also, as will be understood in the later explanation, CH4
has the lowest priority, so when data is being transferred between the hard disk 12 and one of the buffers 9-1 to 9-3, one of the audio input/output devices 8-1 to
When a data transfer request is made from 8-3, the latter data transfer is performed with priority first.

Next, the current address (address register 10
4) is output to the address bus (6-8). Then, control register 1 of the selected channel (currently, for example, CH2)
Referring to the contents of 05, decide in which direction the DMA transfer should be performed (6-9), and if the transfer is from buffers 9-1 to 9-3 to other elements (I/O), start from 6-10. 6-11
Proceeding to step 9-1, the read signal RD is given to the selected buffer among the buffers 9-1 to 9-3, and conversely, the transfer from other elements (I/O) to the buffers 9-1 to 9-3 is performed. If so, proceed to 6-12 and send the write signal WR to the buffer concerned.
give.

Thereafter, the answer signal DAK is activated (6-13). As a result, in this case, the audio input/output device 8-2 of Tr2 sends the sampled audio data to the data bus through the processes 5-7 and 5-8 (FIG. 5), and uses the current data in the buffer 9-2. The DMA controller 10 writes into the address area (see FIG. 8).

At 6-14, since the data transfer has been completed, the above read signal RD or write signal WR and answer signal D
AK is made inactive, and the contents of the current address (in the address register 104 in FIG. 2) of the channel (now CH2) are incremented by 1 at 6-15. By this operation 6-15, each time new sampled audio data is written into the buffers 9-1 to 9-3, or each time new audio data is read out, the count is incremented. After the process of 6-15, the process returns to 6-1.

In the previous state (see FIG. 9), Tr2 and T
A data transfer request is made to the DMA controller 10 from the audio input/output devices 8-2 and 8-3 with r3,
Since data transfer has been executed only for Tr2 so far, YES is determined in the subsequent step 6-5. Below, regarding Tr3, data transfer in the direction from the audio input/output device 8-3 to the buffer 9-3 is performed from 6-7 to 6-
10, 6-12 to 6-15 in the same manner as in the above case.

[0092] When such data transfer is completed, 6-5
Proceeding to 6-16, the DMA enable signal is set to "0" (inactive) to stop the DMA controller 10 from monopolizing the data bus and address bus in the DMA unit, so that access from the CPU 1 can be accepted. Make it.

Regarding Tr2 and Tr3, the audio input/output devices 8-2 and 8-3 respectively correspond to the buffers 9-2 and 9.
Tr1 has been explained about data transfer from the buffer 9-1 to the audio input/output device 8-1.
Data transfer to is performed by the DMA controller 10.

As shown in FIG. 9, between sampling times t and t+1, the audio input/output device 8-1 corresponding to Tr1 sends the request signal DRQ to the DMA controller 10.
(Figure 5, 5-10).

In response, the DMA controller 10 executes steps 6-5 to 6-7 in the same way as in the above case, and
8, address data indicating the address to be read from buffer 9-1 is provided via the address bus. By executing steps 6-9 and 6-10, the process advances to 6-11, where the read signal RD is applied to the buffer 9-1 this time, and the process proceeds to 6-11.
At step 13, the answer signal DAK is set to "1".

As a result, the digital audio data at the designated address of buffer 9-1 is transferred to Tr1 via the data bus.
The audio data will be transferred to and taken in by the audio input/output device 8-1. After that, after processing 6-14 and 6-15, 6-1
Return to

The DMA controller 10 also transfers data between the hard disk 12 and the buffers 9-1 to 9-3. In this case, the address register 104 and control register 105 of channel CH4 are used. This operation is performed by the CPU1 interrupt routine (
4), the settings/control operations 4-1 to 4-4 for the DMA controller 10 and the HD controller 1
After programming operations 4-5, 4-6 for 1 are executed.

CP for this DMA controller 10
In response to U1 setting/control operations 4-1 to 4-4, DM
The A controller 10 performs the processes 6-3 and 6-4. That is, the CPU 1 determines the track to which data is to be transferred this time using channel CH4, and sets the start address of the buffer corresponding to that track (that is, the next address of the block data from which data was transferred between the buffer and the hard disk 12 last time) on CH4. Set the current number of data transfers for this track in the start address register (inside the address register 104 in FIG. 2), and set the start address and current address (address incremented after the previous data transfer was performed between the hard disk 12).
The CPU 1 obtains the difference between the two tracks and copies the current address for this track to the start address.

The CPU 1 sequentially transfers data between the buffers 9-1 to 9-3 corresponding to the track in operation and the hard disk 12 for each track, and transfers the previous data for each track. Data transfer follows the transfer (block transfer). In the example of FIG. 8, for example, for Tr1, from the hard disk 12, the illustrated start address (CH1) and current address (CH1
) will now transfer the amount of data corresponding to the blank area between the tracks (although the direction of data transfer is reversed for other tracks, it is clear that similar control is used). In addition, play mode buffer (9-1 applies)
In the record mode buffer (corresponding to 9-2 and 9-3), the shaded area corresponds to the data portion into which voice input has been made.

The CPU 1 then programs the HD controller 11 through steps 4-5 and 4-6, and then generates an actual transfer request from the HD controller 11 to start DMA transfer.

When the DMA controller 10 detects a transfer request from the HD controller 11 in 6-5, it performs the steps 6-6 to 6-6 in the same way as in the above case.
After executing step 9, it is determined in step 6-10 whether the request is for data transfer from the buffers 9-1 to 9-3 to the hard disk 12 or from the hard disk 12 to the buffers 9-1 to 9-3. If the former, then 6-11
If the latter, proceed to 6-12, then 6-13 to 6-1
5. Execute each process. At this time, with one transfer operation,
For example, since one sample of digital audio data is transferred, the operations 6-5 to 6-15 are repeated a plurality of times to perform block transfer. The data transfer between the hard disk 12 and the buffers 9-1 to 9-3 is largely related to the operation of the HD controller 11, and will be further explained later.

[0102] When the DMA transfer is completed, the request signals DRQ1 to DRQ4 no longer arrive, and the signals 6-5 to 6-16
Then, the DMA enable signal DMAENB is set to "0" (inactive).

<Operation of HD Controller 11> Next, the operation of the HD controller 11 will be described with reference to FIG. This HD controller 11 may be based on hard logic or microprogram control.
In any case, the function of the operation flow shown in FIG. 7 is realized.

First, it is determined whether the designation signal CS is provided from the CPU 1 (7-1). This is given by the interrupt routine of the CPU 1 (4-5, 4-6 in FIG. 4). If NO, the process returns to the original state, but if YES, the process proceeds to 7-2, where it is determined whether the read signal RD or write signal WR is provided from the CPU 1.
When reading, the specified data inside the HD controller 11 (
address register contents, etc.) via the data bus.
Output to U1.

Further, when the write signal WR is being applied, the process proceeds from 7-2 to 7-4, where the data transfer direction between the buffer to be DMA transferred and the hard disk 12 is set on channel CH4 of the DMA controller 10, 7-
In step 5, the access point of the hard disk 12 to be accessed is set. This is based on the disk access pointer of the track that the CPU 1 obtains from the RAM 3 (FIG. 4, 4-5).

Subsequently, in 7-6, the number of transfer data (the number of digital audio data) is set in the internal counter of the HD controller 11. This number of transferred data is obtained at 4-6 in the interrupt routine of the CPU 1.

In this way, by executing steps 7-4 to 7-6, the HD controller 1 is activated under the control of the CPU 1.
1 is programmed, and then the HD controller 11
Request data transfer to MA controller 10 (
7-7). As can be understood from this, CPU1
is the interrupt signal INT from the HD controller 11.
When received, it corresponds to the next track (that is, if T
Assuming that r1 to Tr3 are all in operation, Tr1, Tr2,
Tr3, Tr1...) DMA transfer settings and control are executed for the DMA controller 10, and the HD controller 11 is programmed. After that, the CPU 1 separates from the HD controller 11 and the DMA controller 10, and
The mutual interaction causes actual DMA transfer to be performed.

[0108] The HD controller 11 selects 7 after 7-7.
-8, and the reply signal DA is sent from the DMA controller 10.
Repeat steps 7-8 until CK (DAK4) is received (see Figure 6, 6-13).

If the judgment in step 7-8 is YES, the process advances to step 7-9, and by the operation of CH4 of the DMA controller 10,
One sample of digital audio data is transferred, and 7-
The transfer counter set in step 6 is counted down by 1 (7-10). In the subsequent step 7-11, it is determined whether data transfer for a preset number of transfer data has been completed according to the contents of the transfer counter, and if NO, the process returns to step 7-8. Therefore, in the DMA controller 10, until the transfer of the set number of data (block transfer) from the HD controller 11 is completed, the transfer request DRQ is
4 in succession, the processes 6-5 to 6-15 (Fig. 6) are executed in accordance with this transfer request, and in response, the HD controller 11 side executes the processes 7-8 to 7-11.
Execute the process.

[0110] When it is determined in 7-11 that the transfer is complete, the process proceeds to 7-12, where the DM is transferred from the HD controller 11.
Data transfer request DRE to the A controller 10
Q (DRQ4) is set to "0" (inactive). Then, in order to transfer data between the hard disk 12 and any of the buffers 9-1 to 9-3 regarding the next track, the HD controller 11 gives an interrupt signal INT to the CPU 1 (7-13). As described above, in response to this, the CPU 1 executes the interrupt routine (FIG. 4).

<Hard disk 12 and buffer 9-1~
Data transfer operation between hard disk 12 and buffers 9-1 to 9-3> Through the above explanation, data transfer between hard disk 12 and buffers 9-1 to 9-3 can be understood.
10, a DMA request is made to the DMA controller 10, and how the DMA controller 10 responds to the request in a time-sharing manner will be described below.

As already mentioned, in the setting state shown in FIG. 8, Tr1 is in the play state, Tr2, Tr
3 is in a record state, and data transfer requests from the respective audio input/output devices 8-1 to 8-3 to the buffers 9-1 to 9-3 are sent to the DMA controller at every sampling time (fs in FIG. 10). It will be done in 10.

[0113] This means that the CPU 1
While programming (4-5, 4-6 in Figure 4,
7-4 to 7-7) in FIG. 7 also occur. When the DMA controller 10 receives a data transfer request from the audio input/output devices 8-1 to 8-3, the DMA controller 10 sends the DMA enable signal DMA as described above.
Output ENB (6-6 in Figure 6), and HD by CPU1.
Interrupting programming of controller 11 (WAIT)
Then, after the DMA transfer by each channel CH1 to CH3 is completed, it is restarted (see FIG. 10).

[0114] Furthermore, even when data transfer between the hard disk 12 and the buffers 9-1 to 9-3 is performed sequentially by DMA transfer by CH4, each of the audio input/output devices 8-1 to 8-3 is for each sampling time (Fig. 1
A data transfer request is made to fs 0).

[0115] At this time, in the DMA controller 10,
Channels with high priority (C
Data transfer of H1 to CH3) is performed first. During this time, the HD controller 1 is transferred to the DMA controller 10.
Data transfer request DRQ4 continues to be output from 1 (
(See FIGS. 7 and 7-7) However, since the reply signal DAK4 is not returned from the DMA controller 10, the next data transfer is waited (steps 7-8 are repeated).

Therefore, macroscopically, the DMA controller 10 has Tr1, Tr2, T
The DMA transfer (block transfer) between the hard disk 12 of r3 and the buffers 9-1 to 9-3 is repeated, but microscopically, even during programming to the HD controller 11 and during actual DMA transfer (CH4 DMA transfer (single transfer) between the buffers 9-1 to 9-3 and the audio input/output devices 8-1 to 8-3 is performed on CH1 at each sampling timing. It will be executed by each channel of ~CH3, and A/D conversion at each sampling timing,
It is designed to be able to handle D/A conversion sufficiently in terms of speed.

<Recording and Editing Work> FIG. 11 shows the operation of the embodiment of FIG. 1 over time, and FIG. 12 shows the interrelationships of various processes of the embodiment of FIG. First, in 11-1, 11-2, and 11-3, when track selection, recording, and punch-in/out operations are performed as necessary, the original recording track (ORT), event address table (EAT), and original track schedule(
OTS) is automatically created. The ORT is composed of event identification information (event numbers) arranged in accordance with the recording/playback order, and is stored in the RAM 3. As mentioned above, EAT is event identification information (event number)
and the storage location of the event on the hard disk 12 (original track number, start point (start address), and end point (end address)), and is stored in the RAM 3. The OTS is a table containing recording/playback start times initially set for each event or after punch-in/out operations, and is stored in the RAM 3.

As shown in FIG. 12, the storage areas for Tr1, Tr2, and Tr3 of the hard disk 12 are located at addresses 00000 to 09999, addresses 10000 to 19999, and addresses 2000, respectively.
0 to 29999, and assuming that events 1 to 11 are stored at the addresses of the hard disk 12 shown in FIG. 13, the EAT will be as shown in FIG. In addition, E
An E in the AT attribute column indicates that no grouping or division has occurred since the event was first recorded. FIG. 14 shows an example of the storage state of the hard disk 12 of FIG. 13 and an ORT corresponding to the EAT of FIG. 16. The reason why the positions of events 8 and 9 are swapped in Figures 13 and 14 is that event 8 was recorded earlier than event 9, but event 9 punched in (11-3
), event 9 is played earlier than event 8 in the playback order. Further, Blank in FIG. 14 indicates that the silent portion is defined as blank.

FIG. 15 shows an OT corresponding to the ORT in FIG.
An example of S is shown. As mentioned above, track selection (11-
1), recording (11-2) and punch-in/out (1)
EAT is automatically generated according to 1-3), but eventization (11-4) can be performed manually.
You can also create an EAT manually.

FIG. 17 shows an example of manual event specification processing. That is, one example of this is to specify the start point and end point by pressing some operation switch while the event is being played back in real time. When the reproduction of the audio data is started (17-1), the CPU 1 determines whether there is a key input that designates eventization (17-2). When eventization is specified, CPU1 transfers the buffer (9-1
, 9-2 or 9-3),
The start address on the time axis of the hard disk 12 is calculated by referring to the number of bytes of data transferred from the hard disk 12 to the buffer (17-3). This start address is then set as the start point of the designated event number (17-4). The end point can also be specified using similar arithmetic operations, but the explanation will be omitted.

Another method for manually specifying an event is to specify the range of the event on the time axis on the ICT (individual control track).

FIG. 18 shows an example of the ICT creation process of 11-5 in FIG. This process assumes that the time is known, and first, the CPU 1 displays the time axis and the end point En-1 of the previous event on the display device 5 (18-1). Next, the editor (user) operates the keys on the keyboard 4 to specify the input track, input event, and start point (18-2). next,
CPU1 starts at the start point S specified in 18-2.
Compare n with the end point En-1 of the previous event, and if the former is greater than the latter, write the start point time and event number in the individual track schedule (ITS) (18-4), and from the EAT. Calculate the end point En (18-5). 18-
3, start point S specified in 18-2
If m is less than or equal to the end point En-1 of the previous event, it waits for a new input track, input event, and start point to be specified. The processes 18-1 to 18-5 are continued until the editor inputs a termination command via the keyboard 4, and ICT and ITS are created.

FIG. 20 shows the IC created in this way.
An example of T is shown. As described above, the ICT is made up of event identification information (event numbers) included in the EAT arranged in the event playback order for each track. ICT-1, ICT-2, and ICT-3 in FIG. 20 correspond to Tr1, Tr2, and Tr3, respectively. ICT is the ORT in FIG. 14 modified according to the editor's selection (key operation).

FIG. 21 shows an example of the ITS created as a result of the ICT processing shown in FIG. ITS is a table that records the playback start time of each event for each track,
It is stored in RAM3.

FIG. 19 shows another example of the ICT creation process of 11-5 in FIG. In this process, the CPU 1 first displays the time axis on the display device 5 (19-1). next,
The CPU 1 displays the input track number and event number on the display device 5 (19-2). Next, the editor operates the keys on the keyboard 4 to specify the input track number and input event number (19-3). Next, the CPU 1 determines whether adding an event or inserting an event has been selected from the keyboard 4 (19-4). When the CPU 1 determines that addition of an event has been selected, it calculates the end point from the EAT (19-5), and writes this end point to the ITS as the playback start time of the added event (19-6).
).

When the CPU 1 determines at 19-4 that event insertion has been selected, it accepts the designation of the insertion position from the keyboard 4 (19-7). Next, C.P.
U1 calculates the start point and end point of the insertion location from the EAT (19-8), writes the playback start time of the inserted event to the ITS, and calculates the playback time of the events after the inserted event. Rewrite (19-9). The processes 19-1 to 19-9 are continued until the CPU 1 determines (19-10) that a termination command has been input from the keyboard 4, and the ICT and I
A TS is created.

[0127] When the ICT creation (11-5) in Fig. 11 is completed, next, the total control track (TCT)
Designation (11-6) is performed. TCT is 3- in Figure 3.
20 and as shown in FIG. 23, the TE identification information (TE numbers, TE-1 and TE-2 in the example of FIG. 23) are arranged in the playback order. be. Furthermore, as explained in relation to 3-19 in FIG. 3, and as shown in FIG. 23, TE refers to ICT for multiple tracks (3 tracks in the example of FIG. 23).
The TE designation refers to each segmented data when it is segmented into multiple pieces (two pieces in the example of FIG. 23) on the time axis.
Identification information for the TE (in the example of Figure 23, TE-1 and TE
-2) and is registered in the total event table (TET). The TET is configured with a TE number, start time, and end time for each TE, as shown in FIG. The major difference between TET and EAT is that EAT has information indicating the storage location of the hard disk 12 (original track, start point, and end point), as shown in FIG. The point is that it does not have information indicating such a position on the disk 12, but only has information regarding the time axis on the ICT.

In connection with the creation of TET in FIG. 24, FIG.
The total track schedule (TT) as shown in
S) is created. The TTS has information indicating the playback time of each TE. Each TE can be played any number of times, and in the example of FIG. 25, TE-1 is played twice in a row. TET and T
The difference between TS is that TET has the position of each TE's ICT on the time axis, whereas TTS has playback time information of each TE. Therefore, TET has only one piece of time information for each TE (start time and end time are considered to be one piece of time information), whereas TTS can have any number of pieces of time information for each TE. .

[0129] In this way, the TCT specification in Fig. 11 is performed (
11-6), Once the TTS is created, the Total Control Track (TCT) is then executed (11-7
). When the TCT is executed, the EAT and ITS are automatically modified.

FIG. 22 shows an example of TCT creation execution processing. First, the CPU 1 displays the ICT time axis on the display device 5, and the editor uses the keyboard 4 based on the displayed time axis.
The TE is registered via the TE (22-1). This results in
A TET as shown in FIG. 24 is created. Next, when the editor specifies TTS, that is, specifies the playback order and number of times of TE-1 and TE-2, CPU1
calculates the playback times of TE1 and TE2 and automatically generates a TTS as shown in FIG. 25 (22-2)
. At the same time, a TCT as shown in FIG. 23 is automatically generated.

Next, when the editor inputs a TCT execution command via the keyboard 4 (22-3), the CPU
1 searches for an event that has data on the start point or end point of the TE and is neither the start point nor the end point (22-4), and if such an event exists, divides the event at the TE boundary. Create an event (22-5). Also, CPU
1 searches for events that are the same event as a result of grouping (22-6). If there is such an event, the CPU 1 executes the process specified by the user (editor) (22-7), and if there is no such event, it executes grouping and writes it to the EAT (22-8). Next, the CPU 1 rewrites each ICT and its ITS by adding data by inserting events (22-9), and when this is completed, TET and TTS are no longer needed, so they are cleared (22-10).
).

When the TCT creation execution process as shown in FIG. 22 is performed, as shown in FIG. 23, the individual control track ICT-1 for three tracks,
ICT-2 and ICT-3 are ICT-1', ICT
-2' and ICT-3' respectively, and the Individual Track Schedule (ITS)
has been updated from the ITS in Figure 21 to the ITS in Figure 27, and the event address table (EAT) has been updated from the ITS in Figure 21 to the ITS in Figure 27.
The EAT shown in FIG. 26 or 28 is updated from the EAT shown in FIG. The EAT in FIG. 26 is the case where the grouping in 22-8 in FIG. 22 is not performed, and the EAT in FIG.
T is the case when grouping is performed. G in the attribute column of FIG. 28 means grouping; for example, event 5 indicates that events 12 and 13 are grouped. In addition, in the EAT of FIGS. 26 and 28, events 14 and 15 are the result of dividing event 7 (i.e.,
This is an event created as a result of the processing in step 22-5).

[0133] Thereafter, when the user inputs a reproduction command via the keyboard 4, the CPU 1 refers to ICT-1', ICT-2', and ICT-3' of FIG. 23 (stored in the RAM 3). , according to the order of the events arranged in these tables, generate the address on the hard disk 12 of the event to be played by referring to the EAT of FIG. 26 or FIG. 28 (stored in RAM 3), and The event is played back by accessing the hard disk 12 via the HD controller 11 at the playback time shown in the ITS in FIG.

As described above, in the embodiments shown in FIGS. 1 to 28, editing can be performed by specifying an event, so there is no need to access the disk 12 each time for editing.

<Other Embodiments> Although one embodiment of the present invention has been described in detail above, the present invention can be modified in various ways, examples of which are shown in FIG.

FIG. 29 shows three tracks of DMA units Tr1 to Tr3 using two sets of DMA units according to the above embodiment.
This is an example of a 6-track digital multi-track recorder configured by a DMA unit and 3-track DMA units Tr4 to Tr6. In other words, the number of multi-tracks can be increased by adding more DMA units.

In FIG. 29, a CPU 1' is connected to each unit via a control bus, an address bus, and a data bus to control and manage six tracks. Furthermore, interrupt signals INT0 and INT1 indicating completion of data transfer with the hard disk are given to the CPU 1' from each DMA unit.

The ROM 2' and RAM 3' store programs and data that have been changed in response to the doubling of the number of tracks, as in the previous embodiment.

As the wait (WAIT) signal for the CPU 1', signals from the DMA units Tr1 to Tr3 and signals from the DMA units Tr4 to Tr6 are applied via the OR gate 200.

[0140] Since the other configurations and operations are similar to those of the above embodiment, no further explanation is necessary.

[0141] The present invention can also be used as a type of digital multi-track recorder that has an audio input/output device that inputs and outputs audio signals at a fixed sampling rate, as well as a type that can change the sampling frequency of each audio input/output device. good. When the sampling frequency of each audio input/output device is changed depending on the scale frequency (a sampling clock is generated by a VCO, a digital oscillator, etc.), the entire device becomes a polyphonic sampler (sampling electronic musical instrument). In this case, the sampling clock of each audio input/output device during reproduction (play) will be varied depending on the performance operation.

Furthermore, by setting different sampling frequencies for each track, it is possible to perform track control with a high degree of freedom, such as by assigning a low sampling frequency to tracks that do not require high frequencies, thereby reducing data capacity.

FIG. 30 shows the CPU 1 of FIG. 1 shown in FIG.
CPU1 that can be adopted in place of the interrupt routine of
Here is an example of another interrupt routine. When the interrupt routine shown in FIG. 30 is employed, a playback schedule table is stored in the RAM 3 shown in FIG. 1, as one configuration example. The reproduction schedule table is a table that includes the start address and end address on the disk 12 of each of a plurality of events arranged in reproduction order, and is provided for each track. FIG. 31 shows an example of a playback schedule table for track 1 corresponding to the event address table of FIG. 26.

To explain the interrupt routine of FIG. 30, first, for example, regarding Tr1, hard disk 1
In order to DMA transfer digital audio data of, for example, event 1 from Tr2 to buffer 9-1, channel CH1 corresponding to Tr1 is selected as the channel of DMA controller 10 (30-1). Also, the current address and start address are read from the CH1 area of the address register 104 of the DMA controller 10, and the number of possible data transfers from or to the buffer 9-1 (during recording, the data in the buffer 9-1 is The amount of full area, that is, the number of data that can be transferred from buffer 9-1, and the amount of free space in buffer 9-1, that is, the number of data that can be transferred to buffer 9-1 during playback) is calculated (
30-1).

Next, it is determined whether the track (here, track Tr1) is in recording mode or playback mode (30-
2). If it is the recording mode, the DMA controller 10 and HD controller 11 are programmed to transfer data from the buffer 9-1 to the HD controller 10 (30-8). More specifically, programming for the DMA controller 10 is performed by copying the start address of CH1 to the start address and current address of CH4. The current address of CH4 increases every time a unit amount of data is transferred from the buffer 9-1 to the HD controller 11. Programming for the HD controller 11 involves reading the disk access pointer of Tr1 from the working memory of RAM3, and using this pointer and the buffer 9- calculated in step 30-1.
1 to the HD controller 11, and
This is done according to the mode (recording mode) detected in step 30-2.

As a result, in this case, the HD controller 11 requests the DMA controller 10 to perform DMA transfer from the buffer 9-1 to the hard disk 12 (
DREQ), and the DMA controller 10 executes the corresponding DMA transfer. Next, CPU1
updates the disk access pointer to the value that will be obtained as a result of executing the transfer process described above (30-9).
. That is, all data transfer between the buffer 9-1 and the hard disk 12 will be executed by the DMA controller 10 after this, and the CPU 1 will set the address of the hard disk 12 at the time this DMA transfer is completed in the disk access pointer. Set it.

At 30-2 in FIG. 4, when it is determined that the playback mode is selected, the CPU 1 calculates the number of remaining data in the current table element in the playback schedule table to which the disk access pointer in the RAM 3 belongs (30-3). . As mentioned above, the playback schedule table is also shown in Figure 3.
1, each event to be played is configured to have one table element consisting of one start address and one end address.

[0148] The disk access pointer in RAM3 indicates the storage location of the audio data currently being reproduced by the audio input/output device 8-1, 8-2, or 8-3 (8-1 in this example). This indicates the beginning of the data block stored in the hard disk 12 to be transferred next to the buffer 9-1, 9-2, or 9-3 (9-1 in this example). Now, if the value of the disk access pointer is (520), the table element to which this pointer belongs is the table element corresponding to event 1 in the example of FIG. In this case, the number of remaining data is 799-(520-1)=28
It is 0.

Next, in 30-4, the number of remaining data just calculated is compared with the number of transferable data calculated in 30-1, and if the number of transferable data is larger, the data indicated by the table element is is transferred to buffer 9-1 (3
0-5). Now, as mentioned above, if the value of the disk access pointer is (00520), the number of remaining data is 280, and the number of data transferable is 500, then since 280<500, the address of the disk 12 indicated by the disk access pointer is 00520 to 280. The audio data stored in each address is transferred to the buffer 9-1.

Data transfer from the disk 12 to the buffer 9-1 is performed by programming the DMA controller 10 and HD controller 11. Programming for the DMA controller 10 is performed by copying the start address of CH1 to the start address and current address of CH4. The current address of CH4 increases every time a unit amount of data is transferred from the hard disk 12 to the buffer 9-1. Programming for the HD controller 11 is based on the value of the disk access pointer ((00520) in this example), 30-3.
This is performed based on the number of remaining data of the current table element calculated in step 30-2 (280 in this example) and the mode detected in step 30-2 (playback mode in this example).

As a result, the HD controller 11 requests the DMA controller 10 to perform a DMA transfer from the hard disk 12 to the buffer 9-1 (outputs DREQ), and the DMA controller 10 executes the corresponding DMA transfer. It turns out. Subsequently, the CPU 1 updates the disk access pointer to the value that should be obtained as a result of executing this transfer process (30-6). In the example above (see Figure 31), the disk access pointer is updated to (00800) and the next table element (in the example in Figure 31, the second table element from the top) is updated to (00800).
Move to the table element of the th event 12). The number of data that can be transferred to the buffer 9-1 is also updated (in this example, it is 220).

[0152] Then, return to step 30-3 again,
Calculate the remaining data number of the current table element of the playback schedule table to which the disk access pointer belongs, that is, event 12 (in this example, from 00800 to 0119
Up to 9, so 400). Next, the number of remaining data (400)
and the number of data transferable to buffer 9-1 (220) are compared (30-4). In this case, the number of remaining data is greater than the number of data that can be transferred, so proceed from 30-4 to 30-7 and move from address 00800 to 2 of the hard disk 12.
20 pieces of data are transferred. Further, the process advances to 30-9, and the disk access pointer is updated to 001020. Then, the process returns to the main routine (FIG. 3).

FIG. 32 shows the buffer 9-1 during playback when the interrupt routine of CPU 1 in FIG. 30 is adopted.
, 9-2 and 9-3 are shown. Now, the audio input/output devices 8-1, 8-2, and 8-3 are all in playback mode, and as shown in FIG. 32(a), the buffers 9-1, 9
-2 and 9-3 have free space at the same position due to the playback of audio data (assuming that audio data is stored in the shaded area in the figure) . Since the priority order is Tr1>Tr2>Tr3,
First, data is transferred from the hard disk 12 to the free area P of the buffer 9-1 corresponding to Tr1. When the transfer is completed, as shown in FIG. 32(b), the buffer 9-1
The current address is taken as the start address. Note that during this time, the already stored audio data is read out and transferred to the audio input/output device 8-1. Next, T
Data is transferred from the hard disk 12 to the free area Q of the buffer 9-2 corresponding to r2. When the transfer is completed, the current address of the buffer 9-2 is set as the start address, as shown in FIG. 32(c). Also, during this time, the already stored audio data is transferred to the audio input/output device 8.
-2. Next, buffer 9 corresponding to Tr3
Data is transferred from the hard disk 12 to the free area R of −3. When the transfer is completed, the current address of the buffer 9-3 is set as the start address, as shown in FIG. 32(d). During this time, the already stored audio data is transferred to the audio input/output device 8-3.

Next, in the free area S of the buffer 9-1 corresponding to Tr1, the audio data stored at addresses 520 to 799 of the hard disk 12, that is, part of the data of event 1, and the data at address 0 of the hard disk 12 are stored.
It is assumed that the audio data stored from 0800 to 001020, that is, part of the data of event 12, is transferred in this order. This transfer operation is shown below in Figures 30 and 31.
This will be explained with reference to FIG.

First, the channel CH1 corresponding to Tr1 is selected as the channel of the DMA controller 10 (30-1 in FIG. 30). In addition, the DMA controller 10
The current address and start address are read from the CH1 area of the address register 104, and the number of possible data transfers to the buffer 9-1, that is, the buffer 9-
The amount of free space S of 1 is calculated (30-1 in FIG. 30). In this example, it is 500.

Next, it is determined whether the track Tr1 is in the recording mode or the playback mode (30-2 in FIG. 30). Since the mode is playback mode here, the CPU 1 calculates the remaining data count of the current table element in the playback schedule table of FIG. 31 to which the disk access pointer in the RAM 3 belongs (30-3 in FIG. 30). Now, if the disk access pointer is (520), the table element to which this pointer belongs is the top table element in FIG. 31, and the number of remaining data is 799-(520-1)=280.

Next, at 30-4 in FIG. 30, the remaining data count 280 just calculated is compared with the possible data transfer count 500 calculated at 30-1 in FIG. 30, and since the latter is larger than the former, Part of the audio data, ie, event 1, stored at 280 addresses from the disk address (520) indicated by the disk access pointer is transferred to the buffer 9-1 (30-5 in FIG. 30).

Data transfer from the disk 12 to the buffer 9-1 is performed by programming the DMA controller 10 and the HD controller 11. D
Programming for the MA controller 10 is performed using CH
1 start address (area S shown in FIG. 32(d)
This is done by copying the start address of CH4) to the start address and current address of CH4. CH
The current address of 4 is incremented each time a unit amount of data is transferred from the HD controller 11 to the buffer 9-1. Programming for the HD controller 11 is as follows:
RAM3 disk access pointer value (520),
This is performed using the remaining data count 280 of the current table element calculated in 30-3 of FIG. 30 and the mode (playback mode) detected in 30-2 of FIG.

As a result, the HD controller 11 requests the DMA controller 10 to perform a DMA transfer from the hard disk 12 to the buffer 9-1 (outputs DREQ), and causes the DMA controller 10 to execute the corresponding DMA transfer. It turns out. Next, CPU1 sets the current pointer to the value (
00800). As a result, the process moves to the second table element of the playback schedule table in FIG. 31, and the number of data transferable data is updated to 220 (FIG. 30
30-6).

[0160] Then, return to step 30-3 again,
The number of remaining data in the current table element (second table element) of the reproduction schedule table to which the disk access pointer (00800) belongs is calculated. Here, 11
99-(800-1)=400.

Next, this remaining data number 400 is compared with the possible data transfer number 220 to the buffer 9-1 (
4-4). Here, the number of remaining data is larger, so
30-7, the address 00 of the hard disk 12
800 to 220 audio data, i.e. event 12
A portion of the data is transferred to buffer 9-1. This data transfer is performed by programming the DMA controller 10 and HD controller 11 as described above.

[0162] Thereafter, data is transferred to buffers 9-2 and 9-3 corresponding to tracks Tr2 and Tr3, and after these are completed, data is transferred again to buffer 9-1 corresponding to track Tr1. It will be done.

As described above, by providing a reproduction schedule table as shown in FIG. 31, events to be reproduced can be easily switched. Regarding this playback schedule table, the same function can be realized by reading out the above-mentioned individual control track ICT or individual track schedule ITS (FIG. 27) in combination with the event address table EAT (FIG. 28). There is no need to provide a special reproduction schedule table such as .

[0164]

According to the first aspect of the invention, audio data can be edited by specifying an event, and there is no need to access the address of the audio data storage means such as a disk each time.

According to the invention of claim 2, by referring to the control track, confirming the arrangement order of the events on the time axis, and reading out the event address table in accordance with this order, the audio data storage means for each event is stored. Storage addresses can be generated in playback order and the necessary playback can be performed.

According to the third aspect of the invention, since the event can be read out from the audio data switching means while checking the start address and condo address of each event arranged in the order in which it should be played, it is possible to switch the playback of the event. can be done easily.

According to the invention of claim 4, in addition to the effects obtained by the invention of claim 1, necessary reproduction can be performed for each track.

[0168] According to the fifth aspect of the present invention, it is no longer necessary to manually rewrite the event identification information and the arrangement thereof in the individual control track each time when a large editing change is made.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of a digital recorder of the present invention.

FIG. 2 is a block diagram showing a specific example of main parts of the DMA controller 10 of FIG. 1.

FIG. 3 is a flowchart showing the main routine of the CPU in FIG. 1;

FIG. 4 is a flowchart showing an interrupt routine of the CPU in FIG. 1;

5 is a flowchart showing the operation of the audio input/output devices 8-1 to 8-3 in FIG. 1. FIG.

FIG. 6 is a flowchart showing the operation of the DMA controller in FIG. 1;

FIG. 7 is a flowchart showing the operation of the HD controller in FIG. 1;

8 is a conceptual diagram showing the overall operation of the digital recorder of FIG. 1. FIG.

[Figure 9] D/A, A/D conversion operation for each track, DM
It is a time chart showing A transfer.

FIG. 10 is a time chart showing the state of DMA transfer between a hard disk and a buffer.

FIG. 11 is a flowchart showing the operation of the embodiment of FIG. 1 over time.

FIG. 12 is an explanatory diagram showing the interrelationship of each part of the embodiment of FIG. 1;

FIG. 13 is an explanatory diagram showing storage locations of events in a hard disk.

[Figure 14] Original control track (ORT)
It is an explanatory view showing an example.

[Figure 15] Original track schedule (OTS)
It is an explanatory view showing an example.

FIG. 16 is an explanatory diagram showing an example of an event address table (EAT).

FIG. 17 is a flowchart illustrating an example of manual event specification processing.

[Figure 18] Individual control track (
3 is a flowchart illustrating an example of a creation process of ICT.

FIG. 19 is a flowchart showing another example of ICT creation processing.

[Figure 20] Individual control track (
FIG. 2 is an explanatory diagram showing an example of ICT.

[Figure 21] Individual track schedule (
FIG. 2 is an explanatory diagram showing an example of ITS.

FIG. 22 is a flowchart illustrating an example of a total control track (TCT) creation/execution process.

FIG. 23 is an explanatory diagram showing the mutual relationship between TE, TCT, and ICT.

FIG. 24 is an explanatory diagram showing an example of a total event table (TET).

FIG. 25 is an explanatory diagram showing an example of a total track schedule (TTS).

FIG. 26 is an explanatory diagram showing an example of the EAT updated by executing the TCT in FIG. 22;

FIG. 27 is an explanatory diagram showing an example of ITS updated by executing the TCT in FIG. 22;

FIG. 28 is an explanatory diagram showing another example of the EAT updated by executing the TCT in FIG. 22;

FIG. 29 is a block diagram showing the configuration of another embodiment of the present invention.

30 is a flowchart showing an example of another interrupt routine for the CPU 1 that can be adopted in place of the interrupt routine for the CPU 1 in FIG. 1 shown in FIG. 4;

FIG. 31 is a flowchart showing an example of a reproduction schedule table.

FIG. 32 is a conceptual diagram showing the operation of a buffer during playback when the interrupt routine of FIG. 30 is adopted.

[Explanation of symbols]

1, 1' CPU 2, 2' ROM 3, 3' RAM 8-1, 8-2, 8-3 Audio input/output device 9-1, 9
-2, 9-3 Buffer 10 DMA controller 11 HD controller 12 Hard disk 13 Decoder 14, 15 AND gate 16 Inverter

Claims (5)

[Claims] 1. Audio input/output means for inputting and outputting audio data, audio data storage means for storing digital audio data supplied from the audio input/output means, and digital audio data stored in the audio data storage means. A digital recorder comprising means for storing an event address table including event identification information and storage locations formed by dividing audio data into a plurality of parts. 2. The digital recorder according to claim 1, further comprising means for storing a control track in which identification information of events included in the event address table is arranged in the order in which the events are played. 3. The digital recorder according to claim 1, further comprising means for storing a reproduction schedule table including a start address and an end address on the audio data storage means of each of a plurality of events arranged in reproduction order. 4. An audio device comprising: audio input/output means for performing audio input/output operations corresponding to a plurality of tracks; and a storage area for the plurality of tracks capable of storing digital audio data supplied from the audio input/output means. data storage means; means for storing an event address table including event identification information and storage locations formed by dividing the audio data stored in the audio data storage means into a plurality of parts; A digital recorder comprising means for storing individual control tracks in which event identification information is arranged in the event playback order for each track. 5. A total control track is created by arranging identification information of each divided individual control track in a playback order when the individual control track for a plurality of tracks is divided into a plurality of parts on the time axis. 5. The digital recorder according to claim 4, further comprising means for rewriting event identification information and an arrangement thereof included in said individual control track according to said total control track.