JPH04232684A - Digital recorder - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recorder capable of digitally recording, reproducing, and further editing audio signals and the like.

0002

2. Description of the Related Art It has been proposed to use an external recording device such as a large-capacity hard disk or a magneto-optical disk to record audio signals (for example, Japanese Patent Application No. 123788/1999 filed by the present applicant). In this case, the audio signal is A/
The analog signal is converted into a digital signal by a D converter and temporarily stored in a buffer memory. The digital data stored in the buffer memory is transferred to and recorded on the hard disk at predetermined timing. On the other hand, even during reading, the digital data read from the hard disk is temporarily stored in the buffer memory, read from the buffer memory at a predetermined timing, and input to the D/A converter. The audio signal converted from a digital signal to an analog signal by the D/A converter is supplied to a speaker or the like. By controlling the access address of the hard disk, it is possible to realize a device with advanced and flexible editing functions.

0003

In order to realize such a device at low cost, it is necessary to make the capacity of the RAM as a buffer memory for absorbing the overhead of disk access as small as possible. On the other hand, when editing, for example, if you specify looping playback a large number of times at extremely short time intervals, disk accesses will occur frequently, and a buffer memory with a small capacity will not be able to absorb the overhead of disk accesses. However, there was a problem in that the data transfer could not be completed in time, causing problems such as skipping in the sound during playback.

[0004] Furthermore, when editing, it is not possible to determine whether the editing is capable of absorbing the overhead, and when I actually played the sound and listened to it, it was determined that the overhead was not absorbed. There was an issue in which the editing operation had to be performed again if the

The present invention was developed in view of this situation, and it is possible to determine whether or not the overhead of an external recording device such as a hard disk or magneto-optical device can be absorbed for editing operations. It's about making it possible.

[0006]

[Means for Solving the Problems] A digital recorder of the present invention includes an external recording means for recording a digital signal, a temporary storage means for temporarily storing a digital signal reproduced from the external recording means, and a temporary storage means. A D/A conversion means that D/A converts the digital signal read out from the external storage means and outputs it to the outside, and a display indicating the degree of editing margin for the digital signal read out from the external storage means by displaying the storage status of the temporary storage means. It is characterized by comprising means.

[0007]

[Operation] In the digital recorder having the above structure, the storage status of digital signals in the storage means is displayed. Therefore, it is possible to determine whether the overhead of an external recording device such as a hard disk or magneto-optical disk can be absorbed for editing, and it is possible to easily make the user understand the degree of margin for editing.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the digital recorder of the present invention will be described below with reference to the drawings.

<Overall Configuration> FIG. 1 shows the overall configuration of an embodiment of the digital recorder of the present invention. In this embodiment, recording and playback of up to three tracks can be performed simultaneously. . As shown, the whole is CP
It is divided into a U section (the left part in the figure) and a DMA unit (audio recording/playback processing device) (the right part in the figure).

The CPU section includes a CPU 1, a program ROM 2 that stores a program (details will be described later) that defines the operation of the CPU 1, and an area 3 that stores various data.
RAM3 including an area for storing the current pointer of the track and a work area, and I/O of the CPU1.
It has a keyboard 4 which is a peripheral device connected to a port and includes various function keys, data input keys, etc., and a display device 5 which includes a CRT or LCD and its driver and performs various displays.

As will be described later, during real-time operation (recording/playback, etc.), the CPU 1 uses the DMA unit's address bus and data bus during free time as necessary.
It controls each component of the MA unit, and performs operations such as rearranging data blocks and manipulating disk access pointers during editing. From the keyboard 4, as described later, each track (hereinafter referred to as Tr) can be recorded/recorded.
You can set the playback mode, start, stop, locate, specify edit points, etc. Program ROM2, RAM
The address terminal of 3 is connected to the CPU 1 via the address bus.
An address signal is sent from the CPU 1, and its output terminal is connected to the CPU 1 or the transceiver 7 via a data bus.

That is, in order to connect the CPU section and the DMA unit, the buffer 6 and the transceiver 7 are connected to the DMA unit.
located within the unit. Buffer 6 is connected to CPU 1 via an address bus, and further connected to an address bus within the DMA unit. Transceiver 7 is a CPU
1 via a data bus, and further connected to a data bus within the DMA unit.

The DMA unit includes an audio input/output device 8-1 for Tr1 and an audio input/output device 8-2 for Tr2.
, Tr3 are provided with audio input/output devices 8-3, and analog audio signals can be input and output independently to each of them.

Inside each audio input/output device 8-1 to 8-3, in addition to a converter for selectively performing A/D conversion and D/A conversion, a low-pass filter for removing sampling noise, and a sampling filter are included. It includes a clock circuit that generates a clock at regular intervals. These audio input/output devices 8-
1 to 8-3, when the track is set to record state, the analog audio signal from the outside is appropriately filtered at each sampling period, and then the A/
D conversion is performed to obtain digital audio data. Conversely, if the track is set to the play state, the digital audio data read out in advance is D/D at each sampling period.
After A conversion and appropriate filtering, the signal is output as an analog audio signal.

[0015] Each audio input/output device 8-1 of Tr1 to Tr3
~8-3 are connected to the corresponding buffers 9- through the data bus.
1 (BUF1), buffer 9-2 (BUF2), and buffer 9-3 (BUF3), and exchange digital audio data.

The buffers 9-1 to 9-3 are Tr1 to T.
r3 respectively, and audio input/output devices 8-1 to 8-
3 is performed by a DMA controller 10 using a direct memory access (DMA) method.

Each of the audio input/output devices 8-1 to 8-3 is
During recording, the DMA controller 10 performs DMA transfer (single transfer) of digital data related to one sampling from the audio input/output devices 8-1 to 8-3 in the direction of the buffers 9-1 to 9-3 at the sampling period. (request) (sends DRQ signal (DRQ1 in Tr1, DRQ2 in Tr2, DRQ3 in Tr3)
)), DM
Response from A controller 10 (acknowledgement is T
DAK1 in r1, DAK2 in Tr2, D in Tr3
given from the DMA controller 10 as AK3)
Actual data transfer is then executed. During play, DMA transfer of digital data related to one sampling from the buffers 9-1 to 9-3 to the audio input/output devices 8-1 to 8-3 at the sampling period (single transfer)
A request is made from the audio input/output devices 8-1 to 8-3,
Data transfer is executed by the DMA controller 10 in the same way as in the case described above.

The buffers 9-1 to 9-3 have a capacity to store digital audio data once or multiple times, and for example, the RAM is divided into three into Tr1 to Tr3, and each ring buffer (last address and first address) is divided into three parts. By using it as a virtual connected buffer), FIF
It is configured to function as an O buffer.

Address designation for the buffers 9-1 to 9-3 is performed by a DMA controller 10 or the like via an address bus. That is, during DMA transfer, the address bus, data bus, and control signal line within the DMA unit are exclusively occupied by the DMA controller 10.

The buffers 9-1 to 9-3 are connected to a hard disk controller (hereinafter referred to as H) via a data bus.
Data is transferred to and from the hard disk 12 under the control of the hard disk 12 (hereinafter referred to as D controller) 11. The hard disk 12 and the HD controller 11 are connected via a data bus and a control signal line, and all read/write access to the hard disk 12 is performed by the HD controller 11.
It is done by. The hard disk 12 has Tr1 to Tr.
The DMA controller 10 has a storage area divided into three tracks of 3, and data transfer to and from buffers 9-1 to 9-3 is performed by a DMA controller 10. This causes an interrupt (
INT) to the CPU 1 and instructs the CPU 1 to transfer the next data block. CPU
1 is an interrupt signal IN from the HD controller 11.
When time T arrives, the DMA controller 10 and the HD controller 11 are set to a desired state or programmed, and then DMA transfer is performed. Details of this operation will be explained later.

During play, the DMA controller 10 reads out a pre-specified amount (for multiple sampling periods) of digital audio data from the hard disk 12, and then reads out a specified amount of digital audio data from one of the buffers 9-1 to 9-3. It operates to perform DMA transfer (block transfer) to the buffer, and during recording, reads a pre-specified amount (multiple sampling cycles) of digital audio data from the specified buffer and transfers it to the specified position on the hard disk 12. It operates to perform DMA transfer (block transfer).

[0022] This hard disk 12 and buffer 9-1
9-3, the HD controller 11 sends a request signal DRE to the DMA controller 10.
Q (received as DRQ4 on the DMA controller 10 side), and when transfer is possible, an answer signal DACK is output.
By receiving (outputting as DAK4 on the DMA controller 10 side), an actual transfer state is entered.

[0023] In this way, the DMA controller 10
3 channels between the audio input/output devices 8-1 to 8-3 of Tr1 to Tr3 and the buffers 9-1 to 9-3 (C
H1 to CH3) data transfer, and one channel (CH4 to be described later) data transfer between any of the sequentially selected buffers 9-1 to 9-3 and the hard disk 12, for a total of 4 channels. Performs divided data transfer operation.

In order to manage the functions and operations of each component in the DMA unit, the CPU 1 not only provides address signals to the buffer 6 via the address bus, but also sends designation signals for each component to the decoder 13 via the buffer 6. supply,
The respective designated signals CS are transmitted to each audio input/output device 8-1 to 8-.
3. Buffers 9-1 to 9-3, DMA controller 10
, is given to the HD controller 11. At the same time, various data are exchanged with the CPU 1 via the transceiver 7 and the data bus.

Furthermore, each audio input/output device 8-
A designation signal WR designating whether to enter the record state (write state) or play state (read state) is applied to the IOWR terminals 1 to 8-3 via the buffer 6.

In addition, each buffer 9-1 to 9-3, DMA
This designation signal (write signal) WR and another designation signal (read signal) RD are also given to the controller 10 and HD controller 11 from the CPU 1 via the buffer 6, and the controller 10 and the HD controller 11 receive data from the respective components and read out data. Conversely, you will be able to write data. Further, the DMA controller 10 also outputs these designation signals RD and WR in the DMA transfer state. The relationship between these signals and the functions and operations of each component will be described later.

The DMA controller 10 outputs a DMA enable signal DMAENB as "1" when performing DMA transfer between each component. As a result, the output of the AND gate 14 to which this signal DMAENB is applied via the inverter 16 becomes "0",
Enabling signal E is applied to the buffer 6 and transceiver 7.
is given as "0", and data and addresses cannot be exchanged between the CPU section and the DMA unit. At this time, if a "1" signal is given to the AND gate 15 from the decoder 13, the output of the AND gate 15 becomes "1" and the wait signal WAIT is supplied to the CPU 1.

That is, when the CPU 1 is giving a predetermined signal to the decoder 13 to open the buffer 6 and transceiver 7 in order to manage the DMA unit, that is, when the CPU 1 is giving a predetermined signal to the decoder 13 to open the buffer 6 and the transceiver 7, that is, when the CPU 1 is giving a predetermined signal to the decoder 13 to open the buffer 6 and the transceiver 7, 1
"When the signal is being supplied (CPU1 is supplying the buffer 9-1
~9-3, when outputting an address signal for accessing any of the DMA controller 10, HD controller 11, and audio input/output devices 8-1 to 8-3, the decoder 1
3 becomes active, and the output to one input terminal of each of AND gates 14 and 15 becomes "1"), and when the DMA transfer starts, a wait (WAIT) is applied to the CPU 1, and the DMA transfer is executed with priority. After the wait is released, the operation of the CPU 1 is restarted.

Further, conversely, the DMA controller 10
When executing DMA transfer, CPU1, for example,
Even if an attempt is made to access the MA controller 10, a wait signal WAIT is applied from the AND gate 15 and the CP
The execution cycle of U1 will be extended in the middle, and the buffer 6 and transceiver 7 will be closed during that time.

In the end, the reason why the CPU 1 can access each component of the DMA unit is as follows: (1) The CPU 1 issues an address for accessing each component of the DMA unit. (2) Signal DMAENB is inactive (“0”), that is, the data bus of the DMA unit is empty. When the following two conditions are satisfied, the CPU 1 can proceed with processing without considering when to access the DMA unit by the action of the gates 14 and 15, as described above.

Furthermore, when the CPU 1 wants to immediately change the operating state of the DMA unit in response to a key input or control data trigger, the CPU 1 requests the DMA controller 10 to change the operating state of the DMA unit no matter what state the DMA controller 10 is in. A command DMAEND for interrupting DMA transfer can be output (this is given to the DMA controller 10 as an END signal).

<Configuration of Main Parts of DMA Controller 10> Next, an example of the configuration of the DMA controller 10 will be described. D
The MA controller 10 has a transfer capability in which one bus cycle lasts several hundred nanoseconds. Therefore, the time required to transfer sampling data for three tracks is 1 to 2 microseconds.

When the sampling frequency fs is 48 KHz, the interval of one sampling time is approximately 21 microseconds, and most of the sampling time interval is the interval between the buffers 9-1 to 9-3, the HD controller 11, and the hard disk 12. It becomes possible to use the time for data transfer and programming of each component from the CPU 1.

Now, the main structure of the specific example is shown in FIG. This DMA controller 10 has an address buffer 1 on the input side (IN) connected to the address bus.
01 and an output side (OUT) address buffer 102. The contents specified by the register selector 103 change depending on the address signal applied to the address buffer 101 on the input side, and a desired register existing in the address register 104 and the control register 105 is specified.

The address register 104 and control register 105 have areas for four channels CH1 to CH4, and the channels CH1 to CH3 are located in the buffer 9.
-1 to 9-3, and channel CH4 is a register for performing DMA transfer between buffers 9-1 to 9-3.
This is a register for performing DMA transfer between a designated buffer and the hard disk 12.

The registers for each channel CH1 to CH4 in the address register 104 are stored in the corresponding buffer 9-1.
~9-3 and an area for storing at least the current address and start address of the designated buffer, and each channel CH1~ of the control register 105.
For example, control data specifying the direction of DMA transfer is stored in the CH4 area.

The contents of the address register 104 and control register 105 can be input/output to/from the data bus via the data buffer 106. A timing control logic 107, a service controller 108, and a channel selector 109 control each of these components.

The service controller 108 has a hard logic or microprogram control configuration, and receives signals from the timing control logic 107, audio input devices 8-1 to 8-3, and the HD controller 11.
DMA request signals DRQ1 to DRQ4 from CPU1
In addition to receiving the DMA interrupt command END (DMAEND) from the above, and outputting response (acknowledge) signals DAK1 to DAK4 to each of the above components and a DMA enabling signal DMAENB indicating that DMA transfer is in progress,
It issues various commands to the timing controller 107 and outputs a channel select signal to the channel selector 109. Channel selector 109
are address register 104, control register 1
Selectively specify the register corresponding to each channel CH1 to CH4 in 05.

The timing control logic 107 receives the designation signal CS from the decoder 13, the control signal from the control register 105, and the control signal from the service controller 108, and controls the input/output of the address buffer 102 and the data buffer 106. , operates the address incrementer 110 to increment the current address register of the designated channel in the address register 104.

<Overall Operation of CPU 1> The operation of this embodiment will be explained below. Flowcharts showing the operation of the CPU 1 are shown in FIGS. 3 and 4. This is based on the program (software) stored in the program ROM 2. FIG. 3 shows the main routine, and FIG. 4 shows the interrupt signal INT from the HD controller 11.
shows an interrupt routine that executes in response to the arrival of .

First, in FIG. 3, it is judged whether the mode set by the keyboard 4 is the play/record mode or the edit mode (
Step 3-1). If you are in edit mode, proceed to 3-2 and decide which track and point to edit, and what kind of editing you want to do (for example, shift the timing of a sound recorded at a specified point for a certain amount of time,
The CPU 1 determines whether to modify or delete the data, generates control data for that purpose, stores it in the RAM 3 (3-3), performs various editing operations, and then executes the 3-3 again.
Return to -1.

Although this editing work will not be described in detail, the HD
A read access point program from the hard disk 12 for the controller 11 and the DMA controller 10, transfer to the RAM 3, various edits using the RAM 3, re-storage of edited digital audio data to the hard disk 12, access point The designation etc. are executed under the control of the CPU 1.

Now, when the CPU 1 judges that the current mode is play/record mode, the process proceeds from 3-1 to 3-4, sets the operation mode of each of the three tracks according to input instructions on the keyboard 4, and then proceeds to 3-1. 5, A/D
Each audio input/output device 8 performs both conversion and D/A conversion operations.
-1 to 8-3 are executed, buffer 6, decoder 1
The setting is performed by sequentially sending out the designation signal CS through 3 and giving the IOWR. Now, for example, regarding Tr1, the play state (therefore the D/A conversion operation state), Tr1
2 and Tr3 are each in a record state (therefore, in an A/D conversion operating state). FIG. 9 shows a conceptual diagram of the general operation when such a mode is set.

Then, in 3-5, the buffer 9- for each Tr1 to Tr3 is sent to the DMA controller 10.
Initialize addresses 1 to 9-3. In other words, the address buffer 101, register selector 103, channel selector 109, etc. in FIG.
Initial setting data is input and set via the data buffer 106 while specifying each register (address register 104, control register 105) of H3.

Here, the buffers 9-1 to 9-3 are used cyclically as ring buffers, and in the initial state, the start address and current address of each buffer 9-1 to 9-3 are (FIG. 9 schematically shows the state in which the start address and current address of each buffer 9-1 to 9-3 are stored and controlled in the address register 104 of CH1 to CH3. ).

[0046] Next, the CPU 1 executes the process 3-6,
Initialize disk access pointers corresponding to each track Tr1 to Tr3 of the hard disk 12 located in the work memory area in the RAM 3 (FIG. 9 shows the relationship between the storage area of the hard disk 12 and the disk access pointer). ).

Next, the CPU 1 controls each audio input/output device 8-1.
Then, the A/D conversion operation or D/A conversion operation of 8-3 is started (3-7). Subsequently, in 3-8, the HD controller 11 issues a software interrupt to issue a program request for data transfer between the hard disk 12 and any of the buffers 9-1 to 9-3 (HD controller 1
1 executes the same process as when CPU 1 issues an interrupt INT (to be described later).

Specifically, the operation according to the flowchart shown in FIG. 4 is executed in step 3-8. for example,
In this case, for Tr1, in order to DMA transfer digital audio data from the hard disk 12 to the buffer 9-1, T is selected as a channel of the DMA controller 10.
Determine channel CH1 corresponding to r1 (4-1)
.

Next, the start address of this CH1 (
3-5) as the start address of CH4 (4-2). The operation on the DMA controller 10 side at this time will be described later. Next, in this case, the number of data transfers is calculated from the start address and current address of CH1 (4-3). now,
Since this is the initial state, no data has been transferred to the buffer 9-1 regarding Tr1, and therefore,
Hard disk 1 in all memory areas of buffer 9-1
You can transfer data from 2. Of course, if there are multiple tracks at the time of play, the digital audio data stored in advance must be transferred from the hard disk 12 to multiple buffers at an early stage. It is also possible to perform DMA transfer for each track one after another. Alternatively, after fully transferring data from the hard disk 12 to the necessary buffers 9-1 to 9-3,
Play/record operations may be started synchronously.

Next, in 4-4, in this case CH1
Copy the contents of the current address to the start address of CH4. In this case, the initial address becomes the start address.

[0051] In this way, the CPU 1 uses 4-1 to 4-4.
After performing each setting/control for the DMA controller 10, the process proceeds to step 4-5, where the disk access pointer of the current Tr1 is retrieved from the working memory of RAM3, and further, at step 4-6, the DMA controller 10
The operating mode of Tr1 (current play mode) obtained according to the contents of the CH1 area of the control register 105, the disk access pointer for this Tr1, and the data transfer from the hard disk 12 to the buffer 9-1 determined in 4-3. The HD controller 11 is programmed according to the number. The operation on the HD controller 11 side at this time will be described in detail later.

As a result, the HD controller 11 requests the DMA controller 10 to perform DMA transfer from the hard disk 12 to the buffer 9-1 (DR).
EQ), and the DMA controller 10 outputs the corresponding D
MA transfer will be executed. This operation will also be explained in detail later.

[0053] Next, in 4-7, CPU1
The disk access pointer of Tr1 in the working memory of M3 is updated to the value that the disk access pointer will take as a result of executing the above-described transfer process. In other words, as can be seen from the above explanation, all data transfer between the hard disk 12 and the buffer 9-1 will be executed by the DMA controller 10, and the CPU 1 will transfer data between the hard disk 12 and the buffer 9-1.
The value that the access pointer of the hard disk 12 takes when the MA transfer is completed is set in 4-7. Then, the process returns to the main routine (FIG. 3).

As will become clear from the explanation that follows, once the first interrupt routine (FIG. 4) is started and the HD controller 11 is operated once, every time the transfer of the data block designated by the CPU 1 is completed, , an interrupt is made from the HD controller 11 (the INT signal is
1), what CPU 1 does is record/
It only determines whether the playback operation has ended, whether there has been a key input, or whether a trigger specified in the control data has been activated.

That is, in step 3-9, the CPU 1 refers to the disk access pointer (RAM3) and judges whether the memory area is over or not, that is, whether the process has ended (
3-10), if YES, each audio input/output device 8-1
~8-3 A/D conversion and D/A conversion operations are stopped (3
-11), in the case of NO, refer to the control data and key input state (3-12), and if there is no change, return to the process of 3-9 to check the disk access pointer, and proceed from 3-9 to Repeat 3-13.

Then, if there is any change in 3-13, the process advances from 3-13 to 3-14, and the CPU 1
In order to temporarily suspend MA transfer and make new settings,
DMA stop command to controller 10 (DMAEN
D) is output. Next, follow the new input instructions, etc.
DMA controller 10, audio input/output devices 8-1 to 8-
3 is programmed (3-15), the program proceeds to 3-16 to restart the DMA operation, and after executing the routine of FIG. 4 as in 3-8 described above, the program returns to 3-9.

In this way, during play/record, the CPU 1 performs the initial settings for 3-4 to 3-8, and then performs the initial settings for 3-9, 3-10, 3-12, 3-13, and so on. 3-
Repeat steps 14 to 3-16 and give change instructions on the keyboard 4 (for example, pause (A/D,
D/A interruption) or punch-in-out (A/D,
In response to changes in control data obtained during editing (D/A operation switching, etc.) or changes in control data obtained during editing, it immediately interrupts DMA transfer control, changes the program, and then executes the same process again. do.

<Operation of audio input/output devices 8-1 to 8-3>
Next, with reference to FIG. 5, the operating states of the audio input/output devices 8-1 to 8-3 will be described. This flowchart may be based on microprogram control or hard logic control, and various function implementation means can be selected. Now, in 5-1, it is judged whether the designation signal CS of the audio input/output device has arrived (active) from the CPU 1, and if YES, 5-2
, the operating status (record, play,
stop, etc.) are set. This is done in response to steps 3-5 and 3-15 in the main routine of the CPU 1 in FIG.

[0059] Then, if the determination in 5-1 is NO, in 5-3 the audio input/output devices 8-1 to 8 are
5-3 to 5-4.
~ Proceed to the process of 5-9, and when it is determined that the play state is in progress, the process of 5-
Proceed to steps 10 to 5-15.

First, the operation of the audio input/output devices (in this case, audio input/output devices 8-2 and 8-3) set to the record state will be explained. In step 5-4, it is determined whether the sampling time has come, and this step 5-4 is repeated until the sampling time has come. Note that the sampling time may be determined by providing a hard timer in each of the audio input/output devices 8-1 to 8-3 and based on its output, or by providing a common hard timer and determining the sampling time according to the output of each audio input/output device. may be made to work. As will be understood from the explanation below, it is also possible to set the sampling frequencies of each of the audio input/output devices 8-1 to 8-3 to be different.

Now, if YES is determined in step 5-4, the applied analog audio signal is sampled and held (S/H) and A/D converted in step 5-5. Subsequently, in 5-6, the DMA transfer request DRQ is activated and output to the DMA controller 10.

The DMA controller 10 receives this request signal DRQ and outputs a response signal DAK to perform DMA transfer (detailed operation in this case will be described later).
. Therefore, the audio input/output devices 8-1 to 8-3 (in this case, the audio input/output device 8-2 or 8-3 in the record state)
If the judgment in 5-7 is YES, proceed to 5-8 and
The digital audio data obtained by /D conversion is output to the data bus and sent to the corresponding buffers 9-1 to 9-3 (in this case, buffers 9-2 or 9-3). Then, in step 5-9, the DMA transfer request DRQ is made inactive. Therefore, in the present case, the audio input/output devices 8-2 and 8-3 convert the externally applied analog audio signal into a digital audio signal every sampling period, and send the analog audio signal to the DMA controller 10 as described later. to the current addresses of buffers 9-2 and 9-3 respectively specified by
reference).

If it is determined that the play state is reached in 5-3, the process proceeds to 5-10, activates the DMA transfer request DRQ to the DMA controller 10, waits for the arrival of the response signal DAK from the DMA controller 10, and then proceeds to 5-10. 1
1), import digital audio data on the data bus (5)
-12), make the above request DRQ inactive (5
-13). The operation of the DMA controller 10 at this time will be described later, but in this case, as shown in FIG. ) is input and set to the audio input/output device 8-1 through the above operations. Then, it is determined whether the sampling time has come (5-14). Detection of the arrival of this sampling time is performed in the same manner as described in 5-4.

[0064] If 5-14 is YES, then 5-1
Proceeding to step 5, the analog audio signal is output to the outside after performing D/A conversion and low-pass filtering.

The operation at one sampling time in the case of the record state and the case of the play state has been explained above, but after the completion of each process of 5-9 and 5-15, return to 5-1, and proceed in the same manner. Execute processing for sampling times one after another.

FIG. 10 shows an operation time chart of the audio input/output devices 8-1 to 8-3. In this case, the audio input/output device 8-1 of Tr1 is in the play mode, and the sampling time t and A sampling request (DRQ) is generated between sampling time t+1, DMA transfer is performed from the buffer 9-1 to the audio input/output device 8-1 under the control of channel CH1 in the DMA controller 10, and the sampling request (DRQ) is generated at sampling time t+1. Synchronized with t+1, D/A
A conversion operation is performed.

Conversely, in this case, the audio input/output devices 8-2 and 8-3 of Tr2 and Tr3 are in record mode, and A/D conversion is performed in synchronization with sampling time t or t+1. After that, a DMA transfer command is output to the DMA controller 10, and the DMA transfer is performed in the order of Tr2 and Tr3 (the priority order when there are simultaneous DMA requests is CH1>CH2>CH3>CH4). (depending on the relationship) is executed, and data is transferred from the audio input/output devices 8-2, 8-3 to the buffers 9-2, 9-3.

<Operation of DMA controller 10> Next,
The operation of the DMA controller 10 will be explained with reference to FIG. The flowchart of FIG. 6 may represent that the service controller 108 of FIG. 2 operates under microprogram control, or the DMA controller 10 may realize its functions using hard logic.

First, at 6-1, the designation signal CS from the CPU 1 has arrived (is active).
If it is YES, it is determined in 6-2 whether the read signal RD or the write signal WR is given from the CPU 1, and if it is the read signal RD, it is determined in 6-3.
Proceeding to step 1, the contents of the registers 104 and 105 specified by the address signal given via the address bus are outputted via the data bus so that the CPU 1 can read them.
Conversely, if the write signal is WR, the process proceeds to 6-4, and desired data is input and set to the designated register via the data bus. The processes 6-3 and 6-4 correspond to processes 3-5 and 3-15 of the main routine of the CPU 1. Therefore, by the process 6-4, each register 1 in FIG.
Desired data will be set in 04 and 105.

[0070] Then, DMA from CPU1 like this
When the access and programming to the controller 10 is completed, the designated signal CS becomes inactive, and the signals from 6-1 to 6
The process will proceed to -5.

6-5, each audio input/output device 8-1 to 8
- Whether DMA transfer requests DRQ1 to DRQ3 have come from HD controller 11,
(DRQ4) is received, and if a request is received from either, proceed to 6-6 and send the DMA enable signal DM.
Set AENB to “1” (active) and connect the address bus and data bus in the DMA unit to DMA controller 1.
0 exclusively, and does not accept access from CPU1.

[0072] Subsequently, in the case of a plurality of requests, channels are selected according to the priority order of channels CH1 to CH4 (6-7). For example, in the example of FIG. 10, immediately after sampling, the audio input/output devices 8-2 of Tr2 and Tr3,
A data transfer request from 8-3 is made at the same time, but Tr
Since CH2 has a higher priority, DMA transfer of CH2 will be performed first. Also, as will be understood in the explanation later, C
Since H4 has the lowest priority, when data is being transferred between the hard disk 12 and one of the buffers 9-1 to 9-3, one of the audio input/output devices 8-1 to 9-3 is transferred.
When a data transfer request is made from 8-3, the latter data transfer is performed with priority first.

Next, the current address (address register 10
4) is output to the address bus (6-8). Then, control register 1 of the selected channel (currently, for example, CH2)
Referring to the contents of 05, decide in which direction the DMA transfer should be performed (6-9), and if the transfer is from buffers 9-1 to 9-3 to other elements (I/O), start from 6-10. 6-11
Proceeding to step 9-1, the read signal RD is given to the selected buffer among the buffers 9-1 to 9-3, and conversely, the transfer from other elements (I/O) to the buffers 9-1 to 9-3 is performed. If so, proceed to 6-12 and send the write signal WR to the buffer concerned.
give.

Thereafter, the answer signal DAK is activated (6-13). As a result, in this case, the audio input/output device 8-2 of Tr2 sends the sampled audio data to the data bus through the processes 5-7 and 5-8 (FIG. 5), and outputs the sampled audio data to the buffer 9-2. The DMA controller 10 will write to the area of the current address (Fig. 9
reference).

At 6-14, since the data transfer has been completed, the above read signal RD or write signal WR and answer signal D
AK is made inactive, and at 6-15, the contents of the current address (inside the address register 104 in FIG. 2) of the channel (currently CH2) are incremented by 1. By the operation 6-15, each time new sampled audio data is written into the buffers 9-1 to 9-3, or each time new audio data is read out, the count is incremented. After the process of 6-15, the process returns to 6-1.

In the previous state (see FIG. 10), a data transfer request is made to the DMA controller 10 from the audio input/output devices 8-2 and 8-3 of Tr2 and Tr3.
Since data transfer has been executed only for Tr2 so far, YES is determined in the subsequent step 6-5. Regarding Tr3 below, data transfer from the audio input/output device 8-3 to the buffer 9-3 is performed from 6-7 to 6-6.
-10, 6-12 to 6-15 in the same manner as in the above case.

[0077] When such data transfer is completed, 6-5
Proceeding to 6-16, the DMA enable signal is set to "0" (inactive) to stop the DMA controller 10 from monopolizing the data bus and address bus in the DMA unit, so that access from the CPU 1 can be accepted. Make it.

Regarding Tr2 and Tr3, the audio input/output devices 8-2 and 8-3 respectively correspond to the buffers 9-2 and 9.
Tr1 has been explained about data transfer from the buffer 9-1 to the audio input/output device 8-1.
Data transfer to is performed by the DMA controller 10.

As shown in FIG. 10, between sampling times t and t+1, the audio input/output device 8-1 corresponding to Tr1 sends the request signal DR to the DMA controller 10.
Q is output (Fig. 5, 5-10).

In response, the DMA controller 10 executes steps 6-5 to 6-7 in the same way as in the above case, and
8, address data indicating the address to be read from buffer 9-1 is provided via the address bus. By executing steps 6-9 and 6-10, the process advances to 6-11, where the read signal RD is applied to the buffer 9-1 this time, and the process proceeds to 6-11.
At step 13, the answer signal DAK is set to "1".

As a result, the digital audio data at the designated address of buffer 9-1 is transferred to Tr1 via the data bus.
The audio data will be transferred to and taken in by the audio input/output device 8-1. After that, after processing 6-14 and 6-15, 6-1
Return to

The DMA controller 10 also transfers data between the hard disk 12 and the buffers 9-1 to 9-3. In this case, the address register 104 and control register 105 of channel CH4 are used. This operation is performed by the CPU1 interrupt routine (
4), the settings/control operations 4-1 to 4-4 for the DMA controller 10 and the HD controller 1
After programming operations 4-5, 4-6 for 1 are executed.

CP for this DMA controller 10
In response to U1 setting/control operations 4-1 to 4-4, DM
The A controller 10 performs the processes 6-3 and 6-4. That is, the CPU 1 determines the track to which data is to be transferred this time using channel CH4, and sets the start address of the buffer corresponding to that track (that is, the next address of the block data from which data was transferred between the buffer and the hard disk 12 last time) on CH4. Set the current number of data transfers for this track in the start address register (inside the address register 104 in FIG. 2), and set the start address and current address (address incremented after the previous data transfer was performed between the hard disk 12).
The CPU 1 obtains the difference between the two tracks and copies the current address for this track to the start address.

The CPU 1 sequentially transfers data between the buffers 9-1 to 9-3 corresponding to the track in operation and the hard disk 12 for each track, and transfers the previous data for each track. Data transfer follows the transfer (block transfer). In the example of FIG. 9, for example, for Tr1, from the hard disk 12, the illustrated start address (CH1) and current address (CH1
) The amount of data corresponding to the blank area (the area not shaded) will be transferred (the direction of data transfer is reversed for other tracks, but it is clear that the same control is used). be). Note that in the play mode buffer (corresponding to 9-1), the blank part corresponds to the data part that has already been audio output, and in the record mode buffer (9-1 corresponds to
-2 and 9-3), the shaded area corresponds to the data portion into which voice input was made.

[0085] After programming the HD controller 11 through steps 4-5 and 4-6, the CPU 1 generates an actual transfer request from the HD controller 11 to start DMA transfer.

When the DMA controller 10 detects a transfer request from the HD controller 11 in 6-5, it executes steps 6-6 to 6-9 in the same manner as above, and then transfers the data to the buffers 9-1 to 9-9. 3 to hard disk 12
Is it a request for data transfer in the direction or a request for data transfer in the direction from the hard disk 12 to the buffers 9-1 to 9-3?6
-10, and if the former is the case, the process goes to 6-11; if the latter, the process goes to 6-12, and then each process from 6-13 to 6-15 is executed. At this time, one transfer operation transfers, for example, one sample of digital audio data, so
Repeat this operation 6-5 to 6-15 multiple times,
A block transfer is made. Regarding data transfer between the hard disk 12 and the buffers 9-1 to 9-3, the HD
Since the operation of the controller 11 is also greatly related, it will be further explained later.

Then, when the DMA transfer is completed, the request signals DRQ1 to DRQ4 no longer arrive, and the signals 6-5 to 6-16
Then, the DMA enable signal DMAENB is set to "0" (inactive).

<Operation of HD Controller 11> Next, the operation of the HD controller 11 will be explained with reference to FIG. This HD controller 11 may be controlled by hard logic or by microprogram control, and in either case, the operation flow shown in FIG. 7 is functionally realized.

First, it is determined whether the designation signal CS is provided from the CPU 1 (7-1). This is given by the interrupt routine of the CPU 1 (4-5, 4-6 in FIG. 4). If NO, it returns to the original state, but if YES, it returns to 7-
Proceeding to step 2, it is determined whether the read signal RD or write signal WR has been given from the CPU 1, and at the time of reading, the designated data (contents of the address register, etc.) inside the HD controller 11 is transferred to the data bus in step 7-3. It is output to CPU1 via the CPU1.

Further, when the write signal WR is being applied, the process proceeds from 7-2 to 7-4, where the data transfer direction between the buffer to be DMA transferred and the hard disk 12 is set on channel CH4 of the DMA controller 10, 7-
In step 5, the access point of the hard disk 12 to be accessed is set. This is based on the access pointer for the track that the CPU 1 obtains from the RAM 3 (see Figure 4).
4-5).

Subsequently, in 7-6, the number of transfer data (the number of digital audio data) is set in the internal counter of the HD controller 11. This number of transferred data is obtained at 4-6 in the interrupt routine of the CPU 1.

In this way, by executing steps 7-4 to 7-6, the HD controller 1 is activated under the control of the CPU 1.
1 is programmed, and then the HD controller 11
Request data transfer to MA controller 10 (
7-7). As can be understood from this, CPU1
is the interrupt signal INT from the HD controller 11.
When received, it corresponds to the next track (that is, if T
Assuming that r1 to Tr3 are all in operation, Tr1, Tr2,
Tr3, Tr1, . . . ) DMA transfer settings and control are executed on the DMA controller 10, and the HD controller 11 is programmed. Thereafter, the CPU 1 separates from the HD controller 11 and DMA controller 10 and causes them to perform actual DMA transfer through mutual interaction.

[0093] The HD controller 11 selects 7 after 7-7.
-8, and the reply signal DA is sent from the DMA controller 10.
Steps 7-8 are repeated until CK (DAK4) is received (see FIG. 6, 6-13).

If the judgment in 7-8 is YES, the process advances to 7-9, and by the operation of CH4 of the DMA controller 10,
One sample of digital audio data is transferred, and 7-
The transfer counter set in step 6 is counted down by 1 (7-10). In the following 7-11, it is judged whether the data transfer for the preset number of transfer data has been completed according to the contents of the transfer counter, and if NO, the process is repeated in 7-11.
- Return to 8. Therefore, the DMA controller 10 will continue to receive transfer requests DRQ4 from the HD controller 11 until the transfer of the set number of data (block transfer) is completed, and according to this transfer request, the 6-
Processes 5 to 6-15 (FIG. 6) are executed, and in response, the HD controller 11 side executes processes 7-8 to 7-11.

[0095] When the end of the transfer is determined in 7-11, the process proceeds to 7-12, where the DM is transferred from the HD controller 11.
Data transfer request DRE to the A controller 10
Q (DRQ4) is set to "0" (inactive). Then, in order to transfer data between the hard disk 12 and any of the buffers 9-1 to 9-3 regarding the next track, the HD controller 11 gives an interrupt signal INT to the CPU 1 (7-13). As described above, in response to this, the CPU 1 executes the interrupt routine (FIG. 4).

<Hard disk 12 and buffer 9-1~
Data transfer operation between the hard disk 12 and the buffers 9-3> Through the above explanation, data transfer between the hard disk 12 and the buffers 9-1 to 9-3 can be understood.
11, how a DMA request is made to the DMA controller 10 and how the DMA controller 10 responds to the request in a time-sharing manner will be described below.

As already mentioned, in the setting state shown in FIG. 9, Tr1 is in the play state, Tr2, Tr
3 is in a record state, and data transfer requests from the respective audio input/output devices 8-1 to 8-3 to the buffers 9-1 to 9-3 are sent to the DMA controller at every sampling time (fs in FIG. 11). It will be done in 10.

[0098] This means that the CPU 1
While programming (4-5, 4-6 in Figure 4,
7-4 to 7-7) in FIG. 7 also occur. When the DMA controller 10 receives a data transfer request from the audio input/output devices 8-1 to 8-3, the DMA controller 10 sends the DMA enable signal DMA as described above.
Output ENB (6-6 in Figure 6), and HD by CPU1.
Interrupting programming of controller 11 (WAIT)
Then, after the DMA transfer by each channel CH1 to CH3 is completed, it is restarted (see FIG. 11).

[0099] Also, when data transfer between the hard disk 12 and the buffers 9-1 to 9-3 is performed sequentially by DMA transfer by CH4, each of the audio input/output devices 8-1 to 8-3 is for each sampling time (Fig. 1
A data transfer request is made to fs 1).

[0100] At this time, in the DMA controller 10,
Channels with high priority (C
H1 to CH3) data transfer is performed. During this time, the data transfer request DRQ4 continues to be output from the HD controller 11 to the DMA controller 10 (see FIG.
(see 7-7) However, since the reply signal DAK4 is not returned from the DMA controller 10, the next data transfer is waited (7-8 is repeated).

Therefore, macroscopically, the DMA controller 10 has Tr1, Tr2, T
The DMA transfer (block transfer) between the r3 hard disk 12 and the buffers 9-1 to 9-3 is repeated, but microscopically, during the programming to the HD controller 11 and during the actual DMA transfer (CH4 )
DMA transfer (single transfer) between the buffers 9-1 to 9-3 and the audio input/output devices 8-1 to 8-3 is performed on CH1 to CH3 at each sampling timing even during idle mode or idle mode. A/D conversion and D/D conversion are performed at each sampling timing.
It is designed to be able to cope with A conversion sufficiently in terms of speed.

<Display of Margin> Next, the display of margin will be explained with reference to the flowchart of FIG. This interrupt routine is used as a timer interrupt at a rate of several tens to hundreds of milliseconds during recording, play, or editing. The CPU 1 transfers data from the address register 104 of the DMA controller 10 to the buffer 9 at 8-1.
Read the start address and current address from -1 to 9-3. Next, from the start address and current address read in 8-2, buffers 9-1 to 9
-3 margin (effective capacity) is calculated. This margin is
In a buffer that is performing a playback operation, it can be expressed as the amount of ungenerated data (the amount of data that has already been written but has not yet been read) relative to the total capacity of the buffer. Furthermore, in a buffer that is performing a recording operation, it can be expressed as the unrecorded amount (capacity of an area to which no data has been written yet) relative to the total capacity of the buffer. In either case, this margin means that the current address is C
, when the start address is S and the total capacity of the buffer is N, when the current address is larger than the start address, it is expressed as (N-(C-S))/N, and when the start address is larger than the current address, It can be expressed as (SC)/N. When the margin is determined in this manner, the CPU 1 displays the margin on the display device 5 in 8-3.

FIG. 12(a) shows an example of this display. In this example, the margin for each of the buffers 9-1 to 9-3 (tracks Tr1 to Tr3) is expressed as a bar graph on a real-time basis. The shorter the bar of the bar graph, the smaller the margin, and the longer the bar, the larger the margin. As shown in FIG. 12(b), this margin is
It reaches a maximum when data is written from 2 or when data is transferred to the hard disk 12, and thereafter gradually decreases as time passes. Then, when data is transferred to and from the hard disk 12 again, the margin increases again. Such operations will be repeated.

Returning to FIG. 8, after such a display is made at 8-3, the process proceeds to 8-4, where the margin data at that time is stored in the RAM 3 and saved for use after the operation. Therefore, this margin data can be used as a reference when re-editing the audio data.

[0105] In this way, the load on the buffer varies with the playback operation after editing, but when recording while playing edited data, the load on the playback buffer changes. Since the entire DMA transfer operation causes fluctuations to each buffer, such as changes in the load on the recording buffer, the buffer status of the recording operation can also be displayed in real time.

Although it is possible to actually output the reproduced audio when displaying the margin, the audio may be muted so that only the margin can be checked. Further, in FIG. 12(a), the buffer margin is represented by a bar graph, but for example, when the buffer margin falls below a predetermined threshold value,
It is also possible to make the corresponding LED light up. Furthermore, in addition to the hard disk, other media such as a magneto-optical disk may be used as the external storage device.

[0107]

As described above, according to the digital recorder of the present invention, the storage status in the temporary storage means caused by editing work, that is, the load on the temporary storage means, in other words, the margin is displayed on the display means. Malfunctions may occur by notifying the user of edits that cannot be absorbed by the temporary storage device due to frequent accesses to the external storage device, and prompting the user to abandon the edit, make changes, or rearrange the data in the external storage device. It is possible to prevent this from happening.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital recorder of the present invention.

FIG. 2 is a block diagram showing the configuration of an embodiment of the DMA controller in FIG. 1;

FIG. 3 is a flowchart explaining the operation of FIG. 1;

FIG. 4 is a flowchart explaining the operation of FIG. 1;

FIG. 5 is a flowchart explaining the operation of FIG. 1;

FIG. 6 is a flowchart explaining the operation of FIG. 1;

FIG. 7 is a flowchart illustrating the operation of FIG. 1;

FIG. 8 is a flowchart explaining the operation of FIG. 1;

FIG. 9 is a conceptual diagram showing the overall operation of the embodiment of FIG. 1;

[Figure 10] D/A and A/D conversion operations for each track and D
3 is a time chart showing MA transfer.

[Figure 11] DM between hard disk device and buffer
3 is a time chart showing the state of A transfer.

FIG. 12 is a diagram illustrating margin.

[Explanation of symbols]

1 CPU 2 ROM 3 RAM 8-1 to 8-3 Audio input/output device 9-1 to 9-3 Buffer 10 DMA controller 11 HD controller 12 Hard disk

Claims (1)

[Claims] 1. External recording means for recording a digital signal; temporary storage means for temporarily storing the digital signal reproduced from the external recording means; and a digital signal read from the temporary storage means. D/A conversion means for converting the digital signal into A/A and outputting it to the outside; and display means for displaying the storage status of the temporary storage means to indicate the editing margin for the digital signal read from the external storage means. Digital recorder.