JPH042129A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a via hole finer than the opening of a mask by changing a working gas and continuously conducting first and second high-frequency etching by using the same device. CONSTITUTION:A via lower hole 5, size of which is formed in accordance with an opening 4 and from which a wiring layer 1 is exposed, is formed to an inter-layer insulating film 2 on the wiring layer 1 through anisotropic etching by using a mask 3, and the mask 3 is removed. The upper side face of the lower hole 5 is removed in an inclination, in which an upper opening is widened, through first high-frequency etching using the mixed gas of argon and oxygen as a working gas while an insulator 6 deposited on the lower side face of the lower hole 5 and also formed on a base is shaped. A device conducting first RF etching is employed continuously, and the insulator 6 on the base of the lower hole 5 is removed through second RF etching using Ar as a working gas. According to said process, a desired via hole 7, a lower opening 7a of which is smaller than the opening 4 of the mask 3, an upper side face of which is tilted and an upper opening 7b of which is larger than the opening 4, is formed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method of manufacturing a semiconductor device, and in particular, to a method of forming a via hole in an interlayer insulating film between wiring layers of a multilayer structure. With the aim of providing a manufacturing method that can effectively form fine via holes, when forming via holes in an interlayer insulating film on a wiring layer, etching with a mask is applied to increase the size of the interlayer insulating film. The upper part of the lower hole is formed by forming a lower via hole in which the wiring layer is exposed following the opening of the mask, and by a first high-frequency etching using a mixed gas of inert gas and oxygen as the working gas. The step of removing the side surface so that the upper opening widens, forming an insulator that is deposited on the lower side surface of the prepared hole and also occurring on the bottom surface, and the second high-frequency etching using an inert gas as the working gas, removing an insulator on the bottom surface of the via hole, the via hole is configured to have a lower opening smaller than the opening of the mask, and the first and second high frequency etching steps include:
It is configured to be performed continuously using the same device.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a via hole provided in an interlayer insulating film between multilayer wiring layers.

With the recent demand for miniaturization of devices, wiring layers have become multilayered and fine patterns are also required. Via holes provided in the interlayer insulating film between wiring layers also need to be miniaturized.

[Conventional technology]

Conventionally, the via hole is formed by etching a resist mask having an opening for forming a via hole on an interlayer insulating film. Therefore, the via hole has a size that follows the above-mentioned opening.

Therefore, in order to make the via holes smaller, it is necessary to make the openings in the resist mask smaller.

On the other hand, the openings in the resist mask are formed by pattern exposure and development, and the size thereof is controlled by the exposure pattern. The exposure method includes an optical exposure method in which a pattern of an optical mask is transferred, and an electron beam exposure method in which drawing is performed directly with a focused electron beam.

[Problem to be solved by the invention]

However, in the optical exposure method, since ultraviolet rays are generally used, pattern formation with a size of about 1 to 2 μm is the limit of miniaturization due to diffraction phenomena. Furthermore, although the electron beam exposure method allows formation of a finer pattern than the optical exposure method, the time required for exposure is extremely long because the pattern is filled in with minute spots of the electron beam.

An object of the present invention is to provide a manufacturing method that can form via holes that are effectively smaller than the openings in the mask so that a mask formed by an optical exposure method can be used.

[Means to solve the problem]

In order to achieve the above object, the manufacturing method of the present invention includes the steps of forming a via hole in an interlayer insulating film on a wiring layer.
A step of forming a via hole in the interlayer insulating film by etching using a mask, the size of which follows the opening of the mask, and exposing the wiring layer; and a step of using a mixed gas of an inert gas and oxygen as a working gas. removing the upper side surface of the pilot hole so that the upper opening widens by first high-frequency etching, and forming an insulator that is deposited on the lower side surface of the pilot hole and also generated on the bottom surface; and a step of removing the insulator on the bottom surface by a second high-frequency etching using an active gas as a working gas, thereby forming the via hole so that the lower opening is smaller than the opening of the mask. It is said that

Further, the first and second high-frequency etchings are performed successively using the same device.

[For production]

The present inventor has discovered that in the first high-frequency etching, the upper side surface of the pilot hole is removed with an incline to widen the upper opening, and that insulation is deposited on the lower side surface of the pilot hole and is also generated on the bottom surface. We discovered a phenomenon in which objects are formed. A portion of this insulator removed from the interlayer insulating film adheres to the deposited area and is oxidized by the oxygen plasma of the working gas, and the wiring layer exposed at the bottom of the pilot hole is exposed to the oxygen. It is thought to be formed by oxidation in plasma.

The present invention focuses on the fact that the above-mentioned phenomenon causes the size of the lower part of the prepared hole to be smaller than the opening of the mask, and the present invention focuses on the fact that the above-mentioned phenomenon causes the size of the lower part of the prepared hole to be smaller than the opening of the mask. This makes it possible to form a via hole that is effectively smaller than the opening.

That is, in this via hole, the lower opening, which is smaller than the aperture of the mask, enables correspondence to the fine pattern of the lower wiring layer, and the upper opening, which is larger than the opening due to the slope of the upper side surface, corresponds to the upper wiring layer. To improve step coverage when forming layers.

The first and second high-frequency etching can be carried out successively using the same device due to the composition of the working gas, and it is practically desirable to do so.

〔Example〕

Examples of via hole formation according to the present invention will be described below. There are four examples as described below, and Fig. 1(a)
-(C) are side sectional views for collectively explaining the steps of these examples.

In the figure, 1 is a wiring layer using a Si substrate as a wiring layer, 2 is a PSG interlayer insulating film, 3 is a resist mask, 4 is an opening in the mask 3, 5 is a via hole pre-hole, 6 is an insulator, 7
is a via hole, 7a is a lower opening of via hole 7, 7
b is the upper opening of the via hole 7.

First, referring to (a), by anisotropic etching using a mask 3 having an opening 4 for forming a via hole, a wiring layer is formed on the interlayer insulating film 2 on the wiring layer 1 so that the size follows the opening 4. 1
A via hole pilot hole 5 is formed to expose the mask 3, and the mask 3 is removed.

Next, referring to (b), argon (Ar) and oxygen (0
By the first high frequency etching (RF etching) using a mixed gas of An insulator 6 is also formed.

Next, referring to (C), a second RF etching process using Ar as a working gas is performed by continuing to use the apparatus that performed the first RF etching.
The insulator 6 on the bottom of the prepared hole 5 is removed by F etching. This second RF etching can be performed by stopping the supply of Ot and continuing the supply of Ar after the first RF etching.

Through the above steps, the lower part a is smaller than the opening 4 of the mask 3, the upper side surface is inclined, and the lower part b is made smaller than the opening 4 of the mask 3.
A desired via hole 7 is formed which is larger than the above.

Details of the first to fourth embodiments carried out by the above-mentioned steps are as follows.

(1) First example ■ Thickness of interlayer insulating film 2: 21.58 m Size of opening 4: 0.9 μmφ ■ Conditions for first RF etching RF power: 780 W Ar flow rate: 60 SCCMO□ flow rate
53CCM pressure
2 +nTorr processing time: 120 s
ec■ Second RF etching conditions RF power: 780W Ar flow rate 655CCM pressure
2IIITOrr processing time ・
10 sec ■ Dimensions of via hole 7 Bottom to bottom lower a: 0.66 μm φ Top opening lower b: 1.1 to 1.2 am φ (2) Second embodiment ■ Interlayer insulating film 2 thickness 21.58 m Opening Size of 4: 2.0. czw+ φ■ 1st
RF etching conditions RF power: 780W Ar flow rate '603CCMOt flow rate
' 5SCCM pressure °
2...Torr processing time: 120 se
c■ Second RF etching conditions RF power: 780W Ar flow rate '65 SC0M pressure
°2mTorr Processing time ・ 10 sec Dimensions of via hole 7 Bottom-to-bottom lower a: 1.81 μmφ Top-to-bottom lower B: 2.2 to 2.3 um φ (3) Third embodiment ■ Thickness of interlayer insulating film 2 21.58m Size of opening 4 = 0.9μmφ ■ First RF etching conditions RF power = 240w Ar flow rate ' 60 SCCM02 flow rate 5 SC0M pressure
2III Torr processing time: 360
sec■ Second RF etching conditions RF power: 240 W ^rAr flow rate '65 SC0M pressure
2mTorr processing time ・
30 sec ■ Dimensions of via hole 7 Bottom to bottom lower a: 0.61 μm φ Top to bottom lower b: 1.1 to 1.2 am φ (4)
Fourth Example ■ Thickness of interlayer insulating film 2: 1.5 μm Size of opening 4: 20.9 μmφ ■ First RF etching conditions RF power: 240 W Ar flow rate 60 SCCMO□ flow rate
5 SC0M pressure:
3.5 mTorr processing time: 200
sec■ Second RF etching conditions RF power: 240W Ar flow rate 655CCM pressure
: 3.5 mTorr processing time
18 sec ■ Dimensions of via hole 7 Lower part a: 0.63 μmφ Upper open lower part b: 1.1 to 1.2 umφ From the above examples, the dimension of lower part a is mainly based on the first RF etching. It can be seen that control can be achieved by varying the RF power and pressure.

In addition, in the above-mentioned RF etching, if a halogen-based gas is used instead of Ar, the shape of the via hole 7 will deteriorate, and if a deposition gas is used, the reproducibility will deteriorate.
Preferably, the gas is limited to an inert gas such as Ar.

Further, in the above embodiment, the wiring layer 1 is made of Si and the interlayer insulating film 2 is made of PSG, but based on the principle of the present invention, the wiring layer is made of poly-Si, metal, silicide, etc., and the interlayer insulation film 2 is made of PSG. It is also effective if the film is any commonly used film other than PSG. It goes without saying that the wiring layer may be formed on the semiconductor substrate itself.

〔Effect of the invention〕

As explained above, the present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for forming a via hole in an interlayer insulating film between wiring layers of a multilayer structure. It becomes possible to easily form a via hole that is fine and has good step coverage, which has the effect of facilitating response to device miniaturization.

[Brief explanation of drawings]

FIGS. 1(a) to 1(C) are side sectional views for explaining the steps of the embodiment. In the figure, 1 is a wiring layer, 2 is an interlayer insulating film, 3 is a mask, 4 is an opening in the mask, 5 is a via hole bottom hole, 6 is an insulator, 7 is a via hole, 7a is a lower opening of the via hole, 7b is the upper opening of the via hole.

Claims (1)

[Claims] 1) When forming a via hole in an interlayer insulating film on a wiring layer, by etching with a mask applied, the wiring layer is exposed so that the size of the hole in the interlayer insulating film follows the opening in the mask. A step of forming a pilot hole for the via hole to open the hole, and a first high-frequency etching using a mixed gas of inert gas and oxygen as the working gas, remove the upper side surface of the pilot hole to a slope where the upper opening widens, and A step of forming an insulator that is deposited on the lower side surface of the pilot hole and also generated on the bottom surface, and a step of removing the insulator on the bottom surface by a second high-frequency etching using an inert gas as a working gas. A method for manufacturing a semiconductor device, characterized in that a via hole is formed so that a lower opening is smaller than an opening in the mask. 2) The method of manufacturing a semiconductor device according to claim 1, wherein the first and second high-frequency etching are performed successively using the same device.