JPH04215341A - Data reception timing correction device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reception timing correction device, and more specifically, the present invention relates to a data reception timing correction device, and more specifically, to a transmission line that transmits a digital signal (coding system is, for example, a time division multiplex system) in a loop. , when each station installed in the middle of the transmission path adopts an independent synchronization method, data reading errors due to address conflicts caused by fluctuations in the arrival time of each frame composed of the digital signals mentioned above can be prevented. The present invention relates to a data reception timing correction device that is provided to prevent such problems.

0002

2. Description of the Related Art Each station provided on the above-mentioned loop-shaped transmission line employs an independent synchronization system, is equipped with a clock for synchronization, and constantly generates a synchronization signal. In particular, the master station (hereinafter referred to as "master"), which has the role of creating data and sending it out in a frame, uses the above synchronization signal to determine when to generate data and put it in a frame, and when to send it back in one cycle. The timing for receiving and reading the data is determined.

0003

[Problem to be solved by the invention] In this case, if the time at which the frame goes around the transmission path and returns is accurately determined, the above timing error will not occur, and data processing without error can be performed. However, if there is some degree of fluctuation in the round trip time, address conflicts may occur, and the returned frame cannot be correctly determined, resulting in data reading errors.

[0004] To explain this using drawings, FIG.
It will look like Figure 3. FIG. 2 shows a loop-shaped transmission line, a master M provided on this transmission line, and a plurality of slave stations (hereinafter referred to as "slaves") S1, S2,
S3 and S4 are shown. Each station is equipped with a clock CLK that generates a synchronization signal. Figure 3 is a diagram showing the temporal relationship between frames. Frames that leave master M are shown in (a), and frames that return to master M after a round are shown in (b) and (c). . Normally, a time fluctuation ΔT occurs between the frame leaving the master M and the frame returning to the master M, and this fluctuation ΔT is determined by the threshold value ΔT as shown in the figure (c).
If outside Tc, the data can be reproduced correctly, but the same figure (b
), the time fluctuation ΔT is the threshold value ΔTc
If it enters, the data will be transferred to another frame and an error will occur.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a data reception timing correction device that can always read data correctly even if there is a fluctuation that falls within the threshold value as described above. .

[0006]

[Means for Solving the Problems] In order to achieve the above object, the data reception timing correction device of the present invention includes a delay means for delaying a digital signal by a certain period of time after completing one circuit and returning the digital signal. a switching means for switching between the digital signal delayed by the delaying means and the digital signal before the delay is applied, and a frame composed of one of the digital signals selected by the switching means and the digital signal transmitted from the local station; The timing comparison means compares the time difference with the constructed frame, and the switching control means switches the switching means based on the result of the comparison by the timing comparison means.

[0007]

[Operation] According to the data reception timing correction device having the above configuration, when a digital signal returns after completing one cycle without time fluctuation, the frame composed of the returned digital signal and the digital signal transmitted from the local station are Since the timing matches the frame constituted by the signal, the switching control means sets the switching means to a state without delay.
Alternatively, it can be set to a state with a delay, and the data can be read accurately as is.

[0008] Furthermore, if there is a temporal fluctuation in the returned digital signal (as each station employs an independent synchronization system, some fluctuation usually occurs), the comparison means The switching control means detects an incompatibility in the time difference between the frame made up of the returned digital signal and the frame made up of the digital signal transmitted from its own station, so the switching control means switches the switching means to a delay state or It is possible to switch to a state without. Therefore, data processing can be performed by shifting the fluctuations contained in the returned digital signal to a timing where address conflicts do not occur through switching operations, making it possible to prevent data reading errors. .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples will be explained in detail below with reference to the accompanying drawings showing examples. In the first embodiment, the delay means of the master is composed of a shift register, and the master has a photodetector 1 that detects the optical signal input from the slave, and a photodetector 1 that detects the optical signal input from the slave, as shown in FIG. A shift register 2 that applies a fixed time delay to the electrical signal (this delay time is large relative to assumed time fluctuations, but sufficiently small relative to one frame time; for example, a delay of about 20 bits); The electrical signal delayed by this shift register 2,
a selector 3 for switching between the electric signal and the electric signal before applying the delay;
A receiver 4 that converts the output signal of the selector 3 into serial/parallel, a first-in first-out buffer memory 5 that stores the output signal of the receiver 4 for a certain period of time, and a buffer memory 5.
It has a transmitter 6 that converts the output from the transmitter 6 into parallel/serial, and an optical converter 7 that converts the output signal of the transmitter 6 into an optical signal and sends it to the next slave. a timing error detection unit 8 that compares the time difference between a frame composed of one of the electrical signals and a frame composed of a digital signal transmitted from the own station, and causes the selector 3 to perform switching based on the comparison result; has.

The photodetector 1 uses an ordinary photodiode (PD), and the optical converter 7 uses a light emitting diode (LED). Shift register 2, receiving section 4, transmitting section 6
, a MOS-RAM, a CCD, or the like is used for the buffer memory 5, and a flip-flop or the like is used for the selector 3. The timing error detection unit 8 detects the time difference between the two frames. Specifically, the timing error detection unit 8 extracts the header (the part indicating the beginning of the frame) included in the code composed of the electrical signal output from the selector 3, The time difference with the beginning of the transmission frame specified by a built-in clock (not shown) is measured, and the time difference is determined as a predetermined threshold value 〓T.
It may be determined whether the number is greater or less than c, or an error will occur if the code composed of the electrical signal output from the selector 3 is decoded using the master's built-in clock (not shown). It may be determined whether or not the

When the timing error detection unit 8 determines that the time difference is less than the threshold value 〓Tc as described above, or when an error occurs, it sends a logical code indicating this to the selector 3, and the shift register 2, the delayed electrical signal and the electrical signal before the delay are switched. As a result, even when there is a possibility that the frame returned to the master has temporal fluctuations and does not match the transmission timing, the selector 3 is switched and the shift register 2
This mismatch can be prevented by delaying the shift register 2 or removing the delay by the shift register 2.

Of course, if the timing error detection unit 8 does not make the above determination, the selector 3 is not switched. In the second embodiment, the master delay means is constructed with a long-distance optical fiber, and as shown in FIG.
The optical signal from the previous slave is split by the optical splitter 11, one is sent as is to the photodetector 13, the other is delayed and sent to the photodetector 14 through the long distance optical fiber 12, and both photodetectors 13 , 14 are connected to the selector 3. Other parts with the same symbols as in Figure 1 are 1
This function is the same as that of the second embodiment, and the explanation thereof will be omitted.

Therefore, the second embodiment differs from the first embodiment only in that the delay is realized by an optical fiber instead of a shift register, and like the first embodiment, the master Even if there is a time fluctuation in the frame that is returned and there is a possibility that it does not match the transmission timing, switch the selector 3 and connect the optical fiber 1.
This mismatch can be prevented by delaying the optical fiber 12 or removing the delay caused by the optical fiber 12.
The correct signal can be reproduced.

[0014]

As described above, according to the data reception timing correction device of the present invention, if there is temporal fluctuation in the digital signal that has returned after one round, it can be delayed by a certain period of time, By not applying the voltage, it is possible to escape from the influence of this fluctuation, so that data can always be read accurately and data can be transmitted reliably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram inside a master showing a first embodiment.

FIG. 2 is a schematic configuration diagram of a loop transmission path.

FIG. 3 is a diagram showing the relationship between transmitted and received frames.

FIG. 4 is a block diagram inside a master showing a second embodiment.

[Explanation of symbols]

2 Shift register 3 Selector 4 Receiving section 6 Transmission section 8 Timing error detection section 12 Delay optical fiber

Claims (1)

[Claims] Claim 1: When each station installed in the middle of a transmission line that transmits digital signals in a loop adopts an independent synchronization method, each frame constituted by the digital signal is This data reception timing correction device is provided to prevent data reading errors due to generated temporal fluctuations, and includes a delay means for delaying a digital signal by a certain period of time after completing one circuit, and the delay means A switching means for switching between a delayed digital signal and a digital signal before delay is applied, and a frame composed of one of the digital signals switched by the switching means and a digital signal transmitted from the own station. A data reception timing correction device comprising: timing comparison means for comparing a time difference with a frame; and switching control means for causing the switching means to perform switching based on the comparison result by the timing comparison means.