JPH042162A - read-only storage - Google Patents

Abstract

PURPOSE:To provide a highly packed read-only memory of high performance by forming a self-aligned lightly-doped or heavily-doped region under each gate electrode to make MIS FETs each having either a high or low threshold voltage. CONSTITUTION:A first MIS FET includes a p-type doped region 3, while a second MIS FET includes a corresponding p-type doped region 3 including p<+> region 4 near a gate electrode 8. These MIS FETs are combined to form a read-only memory, in which the two kinds of FETs are corresponding to binary information. Two adjacent FETs share a gate electrode 8, and two adjacent FETs share an n<+> drain (5a or 5b). Alternate n<+> drain regions (5a or 5b) are connected to the same bit line. In such a MIS FET structure, two adjacent bits share a common fine gate.

Description

[Detailed Description of the Invention] [Summary] A drain region is provided in a semiconductor substrate on one side of a gate electrode,
A first structure having a structure in which a low concentration impurity region of a conductivity type opposite to that of the drain region is provided along the peripheral edge of the drain region, and a source region is provided extending from directly below the gate electrode to the bottom of the low concentration impurity region. and a second MIS field effect transistor having a structure in which the low concentration impurity region immediately below the gate electrode of the first MIS field effect transistor and in the vicinity thereof is replaced with a high concentration impurity region of the same conductivity type. is used as a memory cell that corresponds to two values of information, and the layout of the memory cell is
The gate electrodes of two MIS field effect transistors are made common, the drain regions of two adjacent MIS field effect transistors are also made common, and every other drain region can be connected with the same bit line. High integration is achieved by forming a fine gate electrode common to two bits, and high integration is achieved by forming a fine drain region common to two bits. In addition, the MIS can be easily formed with two types of threshold voltages by using two types of high and low impurity regions.
A read-only memory device that enables higher performance by forming field-effect transistors.

[Industrial Field of Application] The present invention relates to an MIS type semiconductor integrated circuit, and more particularly to a highly integrated read-only memory device comprising fine memory cells.

Conventionally, a read-only memory device (where selected bit lines and selected word lines are set to high level and non-selected bit lines and non-selected word lines are It is read as a low level, and the corresponding bit is an MIS with a low threshold voltage.
NOR which conducts and outputs a low level in the case of a field effect transistor, and outputs a high level without conducting if the corresponding bit is a MIS field effect transistor with a high threshold voltage.
Regarding the read-only memory device), it was possible to achieve high integration by making the drain regions of two adjacent MIS field effect transistors common, and the source regions of two adjacent MIS field effect transistors also common. However, since the gate electrodes of two adjacent MIS field effect transistors could not be made common and the surface layout area of the source region could not be omitted, the problem of becoming an obstacle to further higher integration became noticeable. ing. Therefore, there is a need for a means for forming a read-only memory device comprising highly integrated memory cells that does not require a surface layout area of the source region.

[Prior Art] FIGS. 4(a) and 4(b) are schematic diagrams of a conventional read-only storage device, in which (a) is a plan view, (b) is a sectional view taken along the line A-A,
51 is a p-type silicon substrate, 52 is an n+ type source region,
53 is a p-type impurity region, 54 is a p-type impurity region, 55
The n+ type drain region 56 is a field insulating film (element isolation region), 57 is a gate oxide film, and 58 is a gate electrode (
(word line), 59 is an oxide film for impurity blocking, 60 is a phosphosilicate glass (PSG) film, 61 is an electrode contact window, 6
Reference numeral 2 indicates an AI wiring (bit line), and reference numeral 63 indicates a memory cell (for 2 bits).

In the figure, memory cells consisting of MIS field effect transistors having a common n+ type drain region 55 adjacent to one side and a common n+ type source region 52 adjacent to the other side are arranged in a matrix. It shows some of the things that are done. However, each MIS field effect transistor has a different impurity concentration under the gate electrode (p-type impurity region 53 or p++ impurity region 54). It constitutes a read-only storage device that corresponds to information. Two adjacent MIS field effect transistors can have a common n-type drain region, and two adjacent MIS field-effect transistors can have a common n-type source. Since the area can be shared, a considerable degree of integration has been achieved, but there is a drawback that an area is always required to form an n0 type source region for 2 bits, which hinders further increase in integration.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are that, as shown in the conventional example, it is possible to make the drain regions of two adjacent MIS field effect transistors common; MIS
Although field-effect transistors can have a common source region, they can be highly integrated, but since an area for forming a source region is required for every 2 bits, it has been difficult to achieve even higher integration.

"Means for Solving the Problems" The above problems are caused by a gate electrode provided on a semiconductor substrate of one conductivity type via a gate insulating film, and a gate electrode of an opposite conductivity type provided on the semiconductor substrate on one side of the gate electrode. a high concentration drain region, a low concentration impurity region of one conductivity type provided along the peripheral edge of the drain region, and a low concentration impurity region of one conductivity type extending from directly below the gate electrode to the bottom of the low concentration impurity region of one conductivity type. a first MIS field effect transistor comprising a low concentration source region of opposite conductivity type;
A second MIS field effect transistor consisting of an impurity region of one conductivity type in which a low concentration impurity region directly below the gate electrode of the field effect transistor and in the vicinity thereof is highly concentrated is arranged and connected in correspondence with binary information. This problem is solved by the read-only storage device of the present invention.

[Function] That is, in the read-only memory device of the present invention, a drain region is provided in the semiconductor substrate on one side of the gate electrode, and a low concentration impurity region of a conductivity type opposite to that of the drain region is provided along the periphery of the drain region. , and a first MIS field effect transistor having a structure in which a source region is provided extending from directly below the gate electrode to the bottom of the low concentration impurity region;
A second MIS field effect transistor has a structure in which the low concentration impurity region immediately below the gate electrode and in the vicinity of the MIS field effect transistor is replaced with a high concentration impurity region of the same conductivity type, and the second MIS field effect transistor corresponds to binary information. Used as a memory cell, and the layout of the memory cell is set to two adjacent M
The IS field effect transistors may have a common gate electrode, two adjacent MIS field effect transistors may have a common drain region, and every other drain region may be connected to the same bit line. Therefore, an MIS having a fine gate electrode common to two adjacent bits
High integration is achieved by forming a field effect transistor, and high integration is achieved by forming a MIS field effect transistor that has a fine drain region common to two adjacent bits. Since it can be formed under the gate electrode, it is possible to form a MIS field effect transistor that does not require the surface layout area of the source region, resulting in high integration. Since a region can be formed, it is possible to easily form a MIS field effect transistor having two types of threshold voltages, high and low, thereby making it possible to improve performance. In other words, a read-only storage device with extremely high integration and high performance can be obtained.

[Example] The present invention will be specifically explained below with reference to illustrated embodiments.

FIGS. 1(a) and 1(b) are schematic diagrams of a first embodiment of the read-only storage device of the present invention, in which (a) is a plan view, and (b)
) is a cross-sectional view taken along the arrow A-A, 1 is a p- of about 10"cl-'
type silicon substrate, 2 is an n-type source region of about 10 c-, 3 is a p-type impurity region of about 10 c-, 4 H1
p-type impurity region of about 0''cta-', 5a-1o
Odd-numbered n-type drain regions of about 20CI, 5
b is an even-numbered n-type drain region of about 1020cal-5, 6 is a field insulating film (element isolation region) of about 600 nm, 7 is a gate oxide film of about 18 nge, 8
is a gate electrode (word line) of about 300 rilN, 9
is an oxide film for impurity blocking of about 35 nm, and 10 is 6
00 nn+ phosphosilicate glass (PSG) film, 11 has a diameter of 1.00 nn+. The first electrode contact window is about LLII, 12 is the first layer A1 wiring (bit line) about Q5/Am, and 13 is a memory cell (for 2 bits).

In the figure, a gate electrode 8, an n-type drain region (5a or sb) formed on one side of the gate electrode 8,
The p-type impurity region 3 (which becomes the semiconductor substrate and channel region of a normal MIS field effect transistor) formed along the n-type drain region (5a or 5b) and the p-type impurity region 3 from below the gate electrode 8 n formed by extending to
of the p-type impurity region 3 formed in the first MIS field-effect transistor, below the gate electrode 8 and in the vicinity thereof, a higher concentration p+ type impurity region is formed. 4 and a second MIS field effect transistor corresponding to binary information, the first and second MIS field effect transistors are selectively arranged in a matrix. It shows some of the In order to realize a highly integrated memory cell layout, two adjacent MIS field effect transistors have a common gate electrode 8, and two adjacent MIS field effect transistors have an n+ type drain region (5a or 5b) are also common, and every other n-type drain region (5a or 5b
) are connected by the same bit line. Therefore, it is possible to achieve high integration by forming a MIS field effect transistor having a fine gate electrode common to two adjacent bits, and also to form a MIS field effect transistor having a fine drain region common to two adjacent bits. In addition, since all the source regions can be formed under the drain region and the gate electrode, it is possible to form a MIS field effect transistor that does not require the surface layout area of the source region. Since a low concentration or high concentration impurity region can be formed in a part of the self-concentration line under the electrode, it is possible to easily form a MIS field effect transistor having two types of threshold voltages, high and low, thereby making it possible to improve performance. .

FIGS. 2(a) and 2(b) are schematic diagrams of a second embodiment of the read-only storage device of the present invention, in which (a) is a plan view, and (b)
) is a sectional view taken along the line A-A, 1 to 13 are the same as in Figure 1,
14 is an insulating film between the first layer AI wiring/second layer AI wiring, 15
16 indicates a second electrode contact window, and 16 indicates a second layer AI wiring (bit line).

In the figure, the odd-numbered n0-type drain regions 5a are connected to the first layer A1/wiring (bit line) 12 via the first electrode contact window 11, and the even-numbered n0-type drain regions 5b are connected to the first layer A1/wiring (bit line) 12 through the first electrode contact window 11. The second embodiment has the same structure and configuration as the first embodiment except that it is connected to the second layer A1 wiring (bit line) 16 through the second electrode contact window 15. In this embodiment, compared to the first embodiment, there is no particular need for a layout interval between the -th layer AI wiring (bit line) 12 and the second layer A1 wiring (bit line) 16, so Since the memory cell size can be reduced, higher integration is possible.

Next, an embodiment of the method for manufacturing a read-only storage device according to the present invention will be described with reference to FIGS. 3(a) to 3(C) and FIG. 1. However, only the manufacturing method for forming the read-only storage device of the present invention will be described here, and the description of the manufacturing method for forming various elements (transistors, resistors, capacitors, etc.) mounted on general semiconductor integrated circuits will be omitted. do.

FIG. 3(a) A p-type silicon substrate 1 is coated with an oxide film of about 3 On- and 10
Next, the nitride film is etched using a resist (not shown) as a mask layer using a normal photolithography technique.Then, the resist is removed.Then, a normal photolithography technique is used. Using a resist (not shown) as a mask layer, phosphorus is ion-implanted to define the n-type source region 2. The resist is then removed. (2) is used as a mask layer, boron ions are implanted to define a p-type channel stopper region (not shown).Then, the resist is removed.Next, oxidation is performed at 900°C for about 110 hours to form a field of about 600 nm. An oxide film 6 (not shown) is formed.Then, unnecessary underlying nitride film and oxide film are removed by etching.

Figure 3(b) Next, about 181 gate oxide films 7 are grown.

Next, a polycrystalline silicon film containing impurities and having a thickness of about 300 nm is grown by chemical vapor deposition. Next, the polycrystalline silicon film is selectively etched using a resist (not shown) as a mask layer using a conventional photolithography technique to form a gate electrode 8. Then the resist is removed.

FIG. 3(C) Next, using a normal photolithography technique and using a resist (not shown), a gate electrode 8, and a field oxide film 6 (not shown) as mask layers, arsenic ions are implanted to form an n+ type. Tray areas 5a, 5b) are defined. Then the resist is removed.

Next, using a conventional photolithography technique, using a resist (not shown), a gate electrode 8, and a field oxide film 6 (not shown) as mask layers, low concentration boron ions are implanted to control a low threshold voltage. Then, an n-type impurity region 3 which becomes a semiconductor substrate region is defined. Then the resist is removed. Next, using a conventional photolithography technique, using a resist (not shown), a gate electrode 8, and a field oxide film 6 (not shown) as mask layers, ions of boron at a high concentration are selectively implanted to form a high threshold value. The resist 9 defining the p-type impurity region 4 for controlling voltage is then removed. Next, heat treatment is performed in an N2 atmosphere to form an n-type drain region (5a, 5b), an n-type impurity region 3, and a p-type impurity region 4.

Figure 1 Next, unnecessary portions of the gate oxide film 7 are removed by etching.

Next, by applying conventional techniques, an oxide film 9 for impurity blocking and a phosphosilicate glass (PSG) film 10 are grown, each impurity region is activated and the depth is controlled by high-temperature heat treatment, and an electrode contact window 11 is formed. The A1 wiring 12 is formed, etc., and the read-only storage device is completed.

In the above embodiment, the n-type impurity region formed on the p-type semiconductor substrate is used as the source region, but an n-type semiconductor substrate may be used and the semiconductor substrate itself may be used as the source region.

As shown in the embodiments above, according to the read-only memory device of the present invention, it is possible to form a MIS field effect transistor having a fine gate electrode common to two adjacent bits, thereby achieving high integration. High integration can be achieved by forming a MIS field effect transistor that has a fine drain region common to 2 bits, and all source regions can be formed under the drain region and under the gate electrode, which reduces the surface layout area of the source region. High integration is achieved by forming an unnecessary MIS field effect transistor, and in addition, it is possible to form a low-concentration or high-concentration impurity region as a self-concentration line in a part under the gate electrode, so it can easily have two types of threshold voltages: high and low. By being able to form a MIS field effect transistor, higher performance can be achieved.

[Effects of the Invention] As explained above, according to the present invention, in a read-only memory device using an MIS type semiconductor device, formation of a fine gate electrode common to two bits and a fine drain region common to two bits is possible. and high accumulation due to the formation of a source region that does not require surface layout area (compared to the conventional example, the memory cell area is 75% in the case of the first embodiment with respect to the rule of gate length IP■), (60% in the case of the second embodiment) Also, since a low concentration or high concentration impurity region can be formed as a self-concentration line in a part under the gate electrode, two types of threshold voltages, high and low, can be easily set. MI with
Since an S field effect transistor can be formed, performance can be improved. In other words, a read-only storage device with extremely high integration and high performance can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are schematic diagrams of a first embodiment of a read-only storage device of the present invention, and FIGS. 2(a) and (b) are schematic diagrams of a second embodiment of a read-only storage device of the present invention. 3(a) to 3(C) are process cross-sectional views of an embodiment of the manufacturing method for a read-only storage device of the present invention, and FIG. 4(a) is a schematic diagram of FIG.
)(b) is a schematic diagram of a conventional read-only storage device. In the figure, 1 is a p-type silicon substrate, 2 is an n-type source region, 3 is an n-type impurity region, 4 is a p-type impurity region, 5a is an odd-numbered n-type drain region, and 5b is an even-numbered n-type impurity region. 10-shaped drain region, 6 is a field insulating film (element isolation region), 7 is a gate oxide film, 8 is a gate electrode (word line), 9 is an oxide film for impurity blocking, 10 is a phosphosilicate glass (PSG) film, 11 is the first electrode contact window, 12 is the first layer A1 wiring (bit line), 13 is the memory cell (2 pin I-minute), and 14 is the first layer A
1 wiring/second layer A1 inter-wiring insulating film, 15 is the second electrode contact window, and 16 is the second layer AI wiring (bit line).

Claims (2)

[Claims] (1) A gate electrode provided on a semiconductor substrate of one conductivity type via a gate insulating film, a high concentration drain region of the opposite conductivity type provided on the semiconductor substrate on one side of the gate electrode, and a periphery of the drain region a low concentration impurity region of one conductivity type provided along the bottom of the low concentration impurity region of one conductivity type, and a low concentration source region of the opposite conductivity type extending from directly below the gate electrode to the bottom of the low concentration impurity region of one conductivity type. The first MI consisting of
An S field effect transistor and a second MIS field effect transistor consisting of an impurity region of one conductivity type in which the low concentration impurity region directly below and in the vicinity of the gate electrode of the first MIS field effect transistor is highly concentrated. A read-only storage device characterized in that it is connected in an array corresponding to the binary values of. (2) The read-only storage device according to claim 1, wherein the source region is made of the semiconductor substrate itself.