JPH042168A - Mos type field effect transistor and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art Problems to be Solved by the Invention Means for Solving the Problems Working Example A side sectional view of a first embodiment of the structure; Figure 1) Structure 2
(FIG. 2) Process sectional view of the first embodiment of the method. (FIG. 3) Process sectional view of the second embodiment of the method. (FIG. 4) Effects [Summary] Regarding improvements to MOS field effect transistors and their manufacturing methods, especially improvements to p-channel MOS field effect transistors having a surface channel and their manufacturing methods, prevention of short channel effects when short channels are made, and high speed The purpose of the present invention is to provide a pMOSFET structure and a method for manufacturing the same, in which a stable threshold voltage is achieved and a stable threshold voltage is obtained. It has a p-type drain region, and a gate electrode made of p-type silicon disposed to cover the separated portion of the source region and the drain region with a gate insulating film interposed therebetween, and the surface of the p-type silicon gate electrode is , an MO5 type electric field having a structure in which the p-type silicon gate electrode is covered with a phosphorous-doped n-type silicon layer via a diffusion barrier layer made of a high-melting point metal or its silicide provided on the upper surface or the entire surface of the p-type silicon gate electrode. a step of forming a gate insulating film on an effect transistor and an n-type semiconductor substrate, an n-type silicon layer and a first diffusion barrier layer made of a high melting point metal or a silicide thereof, on the gate insulating film; Phosphorus-doped first n
step of sequentially depositing the silicon layer and the phosphorus-doped first layer;
further patterning the n-type silicon layer, the first diffusion barrier layer, and the n-type silicon layer in the shape of a gate electrode, and forming at least a side surface of the gate electrode shape pattern with a phosphorus-doped second n-type silicon layer. 1. A method for manufacturing a MOS field effect transistor having a structure including a covering step.

[Industrial application field]

The present invention relates to a MOS field effect transistor and a method of manufacturing the same, and more particularly to an improvement of a P-channel MOS field effect transistor having a surface channel and a method of manufacturing the same.

In recent years, the degree of integration of LSIs has been increasing further, and miniaturization of elements is also required for P-channel MOS field effect transistors (pMOSFETs), which are mainly used in peripheral circuits such as logic and memories.

Therefore, when devices are miniaturized, there is a need for a pMOSFET that is resistant to deterioration in source-drain breakdown voltage due to short channel effects and that provides stable threshold characteristics.

[Conventional technology]

In a pMOSFET, the mobility of holes, which are carriers, is small, so when a surface channel type is used and surface scattering of carriers is added, the operating speed is lower than that of an nMOSFET.
It is significantly slower than ET. Therefore, conventional pMOS
In FETs, buried channel type devices have generally been used, which eliminate surface scattering of carriers and reduce operating speed delays.

FIG. 5 is a schematic cross-sectional view of the buried channel type pMOSFET, in which 51 is an n-type silicon (Si) substrate;
2 is a field oxide film, 53 is an n1-type channel stopper, 54 is a gate oxide film, 55 is an n-type poly-Si gate electrode, 56 is a p-type buried channel layer, 57S is a p-type source region, and 57D is a p+-type drain Show area.

However, in the pMOSFET having the buried channel, the highly doped source and drain regions 57S,
Since the buried channel layer 56 of the same conductivity type as 57D is in direct contact with the source and drain region 57S of high concentration.
, 57D, majority carriers (h) leak into the channel region 56 as shown in the figure, and the effective channel length (c
h) is narrowed, so when the device is made into a short channel, the distance between the bleeding regions becomes extremely close,
The source-drain breakdown voltage is very likely to decrease due to punch-through. Therefore, conventionally, as shown in FIG. 6, an n-
By providing a type punch-through stopper 58 to form a pn junction at the end portions of the source and drain regions 57S and 57D on the channel region side, and depleting the inside of the n-type punch-through stopper 58, the source-drain breakdown voltage is improved. was planned.

However, in this structure, when the FET is turned on, the effective channel portion and source and drain regions 57S
, 57D are interposed between each other due to the depletion layer formed by the n-type punch through stop flange 58, resulting in an increase in channel resistance and a corresponding decrease in operating speed.

[Problem to be solved by the invention]

As mentioned above, in the buried channel type pMOSFET that has been conventionally used in the pMOSFET, when making a short channel, in order to prevent the source/drain breakdown voltage from decreasing due to punch-through, the source and drain regions and the channel It is necessary to provide a punch-through stopper between the parts, and the presence of this punch-through stopper increases the channel resistance and reduces the operating speed accordingly. It has been difficult to achieve improvements simultaneously.

Therefore, the present invention provides a structure of a p-MOS FET that prevents performance deterioration due to the short-channel effect even when the channel is short-channeled, increases speed, is resistant to metal contamination, and provides a stable threshold voltage, and its structure. The purpose is to provide a manufacturing method.

[Means to solve the problem]

The above problem is solved by forming a pair of P-type source region and p-type drain region that are formed apart from each other on the surface of an n-type semiconductor substrate, and a gate insulating film between the source region and the drain region. and a gate electrode made of P-type silicon disposed over the surface of the P-type silicon gate electrode.
The MOS type field effect according to the present invention is covered with a phosphorus-doped n-type silicon layer via a diffusion barrier layer made of a high-melting point metal or its silicide provided on the upper surface or the entire surface of the p-type silicon gate electrode. a step of forming a gate insulating film on the transistor or n-type semiconductor substrate;
a step of sequentially depositing an n-type silicon layer, a first diffusion barrier layer made of a refractory metal or its silicide, and a phosphorous-doped first n-type silicon layer on the gate insulating film; a step of further patterning the first n-type silicon layer, the first diffusion barrier layer, and the n-type silicon layer into the shape of a gate electrode; This problem is solved by a method for manufacturing a MOS type field effect transistor according to the invention, which includes a step of covering with a type silicon layer.

[For production]

In the pMOSFET according to the present invention, a short channel is achieved in order to improve the operating speed. In order to eliminate the phenomenon that the short channel length is extremely shortened and fluctuated due to leakage of majority carriers from the source and drain regions, a surface channel method is adopted and the channel region is made n-type. This forms a junction at the interface between the channel region and the P' type source and drain regions. Furthermore, the source and drain regions are made extremely shallow so that the electric field from the gate electrode extends to a depth equivalent to the bottom surface of the source and drain regions in the channel region, so that the electric field from the source and drain junctions into the channel region is made extremely shallow. The expansion of the depletion layer is suppressed, thereby preventing punch-through and preventing deterioration of the source-drain breakdown voltage.

In addition, by doing the above, no high resistance region is interposed between the channel part and the source and drain regions during operation.
In addition, since the channel is shortened, the speed can be increased.

In the above-mentioned surface channel type pMOSFET, the gate electrode needs to be p-type in order to avoid an increase in the dark voltage due to the difference in work functions and to obtain high conductivity. The p'' type gate electrode is formed by introducing a high concentration of boron (B) into the gate electrode material.

However, unlike phosphorus (P), which is introduced in high concentration into the Si layer of the gate electrode material in order to make the gate n-type in nMOSFET, boron (B) is a gettering agent for contaminants such as alkaline earth metals. Has no function. Therefore, in a surface channel type pMOSFET in which a gate electrode made of p-type Si is formed, the contaminants that enter during a process such as a resist process do not gettered to the gate electrode but enter the gate insulating film. , which causes the problem of varying the dark voltage (Vth).

Therefore, in the present invention, the surface of the gate electrode made of p-type Si is covered with an n-type Si layer doped with phosphorus CP', which has a gettering effect, through a barrier layer that prevents solid phase diffusion of impurities. By gettering the contaminants here, the contaminants are prevented from entering the gate insulating film, thereby preventing fluctuations in vth that tend to occur in surface channel type pMOSFETs.

Thus, it has a short channel, a high source-drain breakdown voltage, and a stable pM.

A 5FET is formed.

[Example〕 The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic side sectional view of a first embodiment of the structure of the present invention;
FIG. 2 is a schematic side sectional view of a second embodiment of the structure of the present invention;
Figures 3(a) to (a) are cross-sectional views of the process of the first embodiment of the method of the present invention, and Figure 4 is a cross-sectional view of the process of the second embodiment of the method of the present invention. Objects are indicated by the same reference numerals.

FIG. 1 is a schematic side sectional view showing a first embodiment of a pMOSFET according to the present invention.

In this structure, l is an n-type channel stopper with a specific resistance of 10 Ω cm3, 4 is a gate oxide film grown with a thickness of about 150 cm, and 5 is a gate oxide film with a B concentration of about 1020 cm-3, a thickness of 2000 cm, and a gate length. P with a width of about 1 μm in the direction
6 is a tan-grown tensile silicide (WS i 2) layer with a thickness of about 200 to 500, for example, which becomes a diffusion barrier for phosphorus (P) and B, and 7 is a 10"c
8S is a phosphorous-doped n-type poly-Si layer with a P concentration of about 300 to 1000 layers and an impurity source concentration of 1.
0110l9", an O4" type source region with a depth of about 1500 mm, 8D a $1 type drain region with the same impurity concentration and depth as the source region, 9 a silicon dioxide (Sio
□) interlayer insulating film, 10 is a phosphosilicate glass (PSG) interlayer insulating film, 11 is a contact window, 12S is an aluminum (A
A) and the like, and 120 similarly represents a drain wiring.

As shown in this figure, the pMOSFET of the present invention has a surface channel type, and has a p-type poly-Si gate electrode 5.
has a structure in which the surface is covered with an n''' type poly-Si layer 7 doped with a high concentration of phosphorus (P) via a WSiz layer 6 disposed on the entire surface and serving as a barrier for impurities. .

In addition, in the second embodiment of the structure, as shown in FIG. is p
A WSi2 layer 6^ serving as a barrier to impurities is interposed only on the upper surface of the 'type poly-Si gate electrode 5. Other parts are the same as in the first embodiment. In this structure, since there is no WSi layer between the side surface part of the p''' type poly-Si gate electrode 5 and the phosphorous-doped n'-type poly-Si layer 7, there is no interaction between phosphorus and boron in this part. Diffusion occurs, but the above 2
The ratio of the area of the side surface of the thin P-type poly-Si gate electrode 5 to the entire surface of the gate electrode is small, and the Vth due to the diffusion of phosphorus from this portion into the gate electrode 5 is small.
There are almost no fluctuations.

Next, the first manufacturing method of the pMOSFET having the structure according to the present invention will be explained with reference to FIGS. 3(a) to 3(a).
(This will be explained in detail with reference to powder.

Refer to FIG. 3(a) When forming a pMOSFET according to the present invention, an oxidation-resistant film pattern (not shown) is used as a mask on an n-type Si substrate 1 having a resistivity of about 100 cm and a surface orientation of 100). , phosphorus (P''') at 5QKeV
By selectively implanting ions to a thickness of about 0 cm-, and performing selective oxidation (commonly known as Lacos) using the same oxidation-resistant film pattern as a mask, a thickness of about 5,000 cm was formed to define the device area DA.
A 7-field oxide film 2 and an n-type channel stopper 3 below it are formed.

Refer to FIG. 3(b). After dry oxidizing the device area DA for about 200 hours (not shown), P+ was oxidized to 2Xl013CT at 4QKeV.
After ion implantation of about 11-2, the dry oxide film is removed, and a new gate oxide film 4 with a thickness of about 150 mm is formed by dry oxidation.

Here, the n-type threshold adjustment region (
A channel dose region) 10 is formed.

Referring to FIG. 3(C), a poly-Si layer 105 with a thickness of about 2,000 layers is deposited on the substrate by CVD, and boron (B"") with a thickness of about 2XIOIscm-2 is deposited on this by ion implantation.
A first WSi layer with a thickness of about 500 layers is doped thereon, and then sputtered on top of it to serve as a diffusion barrier for impurities.
Layer 6A is deposited on top of it by CVD to a thickness of 1
Approximately 000 people deposited the first coating poly-Si layer 107A, and then deposited the first coating poly-Si layer 107A diphosphorus (
P") is ion-implanted at 20 KeV to about IXIO"cm-", and then annealed at 800°C for about 60 minutes.

Here, the gate poly-Si layer 105 becomes p type, and the first
The covering poly layer 1078 becomes the phosphorous-doped first n'' type poly-Si layer 78.

Refer to FIG. 3(d). Next, the above three layers are patterned using a normal photolift, and a first W layer is placed on the P+ type poly-Si gate electrode 5.
Through the Si2 layer 6A, the phosphorus-doped first n° type poly-Si
A gate pattern is formed in which layers 78 are laminated.

Refer to FIG. 3(e). Next, a second WSi layer 6 with a thickness of about 300 nm is deposited on the substrate on which the gate pattern is formed by sppacking.
B is deposited, and then 10' of phosphorus is deposited on it by CVD method.
A second n+ type poly-Si layer 7B doped to about 9 to 10<2>O<-3> is deposited.

The phosphorus-doped second n-type polySt layer 7B may be formed by solid phase diffusion from a spin-on glass containing phosphorus after depositing a non-doped polySi layer.

Refer to FIG. 3(f). Next, by etching the entire surface by reactive ion etching using, for example, a chlorine (C1) gas, the phosphorus-doped second n" type poly-Si layer 7B and the second WSi2 layer below it are etched. Layer 6B is selectively etched away to expose gate oxide film 4.

Here, a second WS is applied to the side surface of the P+ type poly-Si gate electrode 5.
i, a phosphorus-doped second n-type poly-Si layer 7B is residually deposited in the form of a sidewall through the layer 6B, and the entire surface is covered with W.
A gate structure corresponding to the first embodiment of the above structure is formed, which is covered with a phosphorous-doped n-type poly-Si layer 7 (78 and 7B) via a Si layer 6 (6A and 6B).

After homogenizing the exposed gate oxide film 4 by performing additional oxidation of about 50λ as usual after referring to FIG.
8 and 7B) using the P-poly-Si gate electrode 5 as a mask, apply BF2'' to I
``cm-'' dose, and then CVD method to a thickness of 2 cm.
A glabellar insulating film 9 is formed with a thickness of about 4,000 in, then an O8PSG interlayer insulating film 10 with a thickness of about 4,000 in is formed by CVD, a source and drain contact window 11 is formed by photolithography, and then a
The above contact window 1 was formed by performing reflow treatment at 900°C.
The side surface of 1 is formed into a slope shape. During this reflow process, the implanted BFz'' is activated and redistributed to form an O2' source region 8S and a p' type drain region 8D to a depth of approximately 1,500.

Thereafter, for example, A! A source wiring 12S and a drain wiring 120 are formed, and a pMOSFET corresponding to the first embodiment of the above structure is completed.

Furthermore, the pMOSFET having the second structure according to the present invention shown in the second example of the structure is the same as the second structure according to the present invention.
or the third method.

That is, in the second method, in the step corresponding to FIG. 3(e) in the first embodiment of the manufacturing method, as shown in FIG. The first n-type poly-Si layer 7 is inserted through the first WSi2 layer 6A.
On the substrate having the gate pattern on which A is laminated, the second
Without depositing a WSiz layer of
An n-type poly-Si layer 7B is deposited. The subsequent steps are the same as in the first embodiment.

In the pMOSFET according to the present invention formed by the manufacturing method according to the present invention as shown in the examples above, p
The surface of the ゛-type gate electrode is doped with a high concentration of phosphorus.
It is covered with a type Si layer. Therefore, contaminants such as alkaline earth metals that invade during the process are
The amount of the above-mentioned contaminants that are gettered by phosphorus in the i-layer and invades into the gate insulating film is significantly reduced. Therefore, when a short channel is formed, fluctuations in the dark value voltage (vth) that are noticeable due to the presence of the above-mentioned contaminants are prevented, and the pM having a short channel is prevented.

The reliability of 5FET is improved.

〔Effect of the invention〕

As described above, according to the present invention, variations in characteristics of a pMOSFET whose operating speed is improved by shortening the channel can be prevented. Therefore, the present invention is effective in improving the yield and reliability of integrated circuits that use pMOSFETs and are highly integrated and operate at high speeds.

[Brief explanation of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of the structure of the present invention, FIG. 2 is a schematic side sectional view of a second embodiment of the structure of the present invention, and FIGS. 3(a) to (6) 4 is a cross-sectional view of the process of the first embodiment of the method of the present invention, FIG. 4 is a cross-sectional view of the c1 process of the second embodiment of the method of the present invention, and FIG. 5 is a schematic cross-sectional view of a conventional buried channel pMOSFET. be. FIG. 6 is a schematic cross-sectional view of a conventional buried channel type pMOSFET having a punch-through stopper. In the figure, 1 is an n-type St substrate, 2 is a field oxide film, 3 is an n-channel stopper, 4 is a gate oxide film, 5 is a P"-type poly-Si gate electrode, 6 is a WSi layer, and 7 is a phosphorus-doped layer. n" type poly-Si layer, 8S is a p" source region, 8Ω is a p" type drain region 9 is a 5i02 interlayer insulating film, 10 is a psc interlayer insulating film, 11 is a contact window, 12S is a source wiring, 12D is a drain wiring show.

Claims (4)

[Claims] (1) A pair of p-type source region and p-type drain region formed apart from each other on the surface of an n-type semiconductor substrate, and a part covering the separated part of the source region and the drain region with a gate insulating film interposed therebetween. and a gate electrode made of p-type silicon disposed in such a manner that the surface of the p-type silicon gate electrode is made of a high melting point metal or its silicide provided on the upper surface or the entire surface of the p-type silicon gate electrode. A MOS field effect transistor characterized in that it is covered with a phosphorous-doped n-type silicon layer via a diffusion barrier layer. (2) forming a gate insulating film on an n-type semiconductor substrate, and forming a p-type silicon layer, a first diffusion barrier layer made of a high melting point metal or its silicide, and doped with phosphorus on the gate insulating film. a step of sequentially depositing a first n-type silicon layer; a step of collectively patterning the phosphorus-doped first n-type silicon layer, the first diffusion barrier layer, and the p-type silicon layer into a gate electrode shape; A method for manufacturing a MOS field effect transistor, comprising the steps of: covering at least a side surface of the gate electrode shape pattern with a phosphorous-doped second n-type silicon layer. (3) The step of covering at least the side surfaces of the gate electrode shape pattern with a phosphorous-doped second silicon layer comprises a high melting point metal or its silicide on the surface of the gate electrode shape pattern and the exposed gate insulating film. A second diffusion barrier layer and a phosphorous-doped second n-type silicon layer are sequentially deposited, and the phosphorus-doped second n-type silicon layer and the second diffusion barrier layer are selectively removed by etching the entire surface. selectively only on the side surfaces of the gate electrode shape pattern.
3. The method of manufacturing a MOS field effect transistor according to claim 2, further comprising the step of leaving the phosphorus-doped second n-type silicon layer in the form of a sidewall through the diffusion barrier layer. (4) The step of covering at least the side surfaces of the gate electrode shape pattern with a phosphorous-doped second n-type silicon layer includes the step of covering at least the side surfaces of the gate electrode shape pattern with a phosphorous-doped second n-type silicon layer on the surface of the gate electrode shape pattern and the exposed gate insulating film. A type silicon layer is deposited, and the phosphorus-doped second n-type silicon layer is selectively removed by etching the entire surface, and the phosphorus-doped second n-type silicon layer is selectively etched only on the sides of the gate electrode shape pattern. 3. The method of manufacturing a MOS field effect transistor according to claim 2, further comprising a step of leaving the silicon layer in the form of sidewalls.