JPH04217324A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04217324A
JPH04217324A JP2403640A JP40364090A JPH04217324A JP H04217324 A JPH04217324 A JP H04217324A JP 2403640 A JP2403640 A JP 2403640A JP 40364090 A JP40364090 A JP 40364090A JP H04217324 A JPH04217324 A JP H04217324A
Authority
JP
Japan
Prior art keywords
barrier metal
bump
resist
bumps
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2403640A
Other languages
Japanese (ja)
Inventor
Hirohiko Morita
森田 博彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2403640A priority Critical patent/JPH04217324A/en
Publication of JPH04217324A publication Critical patent/JPH04217324A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the filming property of a resist in etching of the barrier metal existing in the layer below a bump, after formation of the bump. CONSTITUTION:Negative resist is applied thick on a silicon substrate 1, where a barrier metal 5 is made, and the negative resist is overexposed to form a resist 7, whose cross section is reversely tapered, and with this resist 7 as a mask, a bump 6 is made by electrolytic plating method. Then, the barrier metal 5 is selectively etched. The overetching of the barrier metal right below the bump 6 can be prevented, and the contact area between the bump 6 and the barrier metal 5 widens enough, and the adhesive strength of the bump 6 improves. Furthermore, corrosion by the etchant of an aluminum pad 3 is prevented and the yield rate and the reliability improve.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、半導体装置の製造方
法に関し、特にバンプの形成方法に係るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming bumps.

【0002】0002

【従来の技術】近年、半導体集積回路の高集積化・高密
度化・多ピン化に伴い、半導体集積回路の実装において
、従来のワイヤ・ボンディング技術に代わり、バンプを
用いたTAB(Tape Automated Bon
ding)技術が用いられている。バンプ形成方法には
いろいろあるが、その一つに電解メッキ法がある。電解
メッキ法によるバンプの形状は、マッシュルーム型が主
流であったが、近年の高集積化・高密度化・多ピン化に
伴いパッドピッチを縮小する傾向にあり、メッキ時に横
広がりの無いストレート形状のバンプの開発が盛んにな
ってきている。
[Background Art] In recent years, as semiconductor integrated circuits have become more highly integrated, denser, and have more pins, TAB (Tape Automated Bond) using bumps has been used instead of conventional wire bonding technology in the mounting of semiconductor integrated circuits.
ding) technology is used. There are various methods for forming bumps, one of which is electrolytic plating. The shape of bumps produced by electrolytic plating was mainly mushroom-shaped, but in recent years there has been a trend toward smaller pad pitches due to higher integration, higher density, and increased number of pins. The development of bumps is becoming more popular.

【0003】以下、従来の方法により形成されたストレ
ート形状のバンプ(以下「ストレートバンプ」という)
について説明する。図2(a) はストレート形状のバ
ンプ形成後の断面図であり、1はシリコン基板、2は絶
縁膜、3はアルミパッド、4は保護膜、5はバリアメタ
ル、16はストレートバンプである。ストレートバンプ
16は、厚膜レジストでパターンニングされたマスクで
電解メッキ法により形成され、その断面形状は、図2(
a) に示すように側壁がほぼ垂直となる。
[0003] Hereinafter, straight bumps formed by conventional methods (hereinafter referred to as "straight bumps")
I will explain about it. FIG. 2(a) is a cross-sectional view after straight bumps are formed, and 1 is a silicon substrate, 2 is an insulating film, 3 is an aluminum pad, 4 is a protective film, 5 is a barrier metal, and 16 is a straight bump. The straight bump 16 is formed by electrolytic plating using a mask patterned with a thick film resist, and its cross-sectional shape is shown in FIG.
a) The side walls are almost vertical as shown in .

【0004】0004

【発明が解決しようとする課題】しかしながら垂直な側
壁を有するストレートバンプ16の下層にあるバリアメ
タル5を選択エッチングするために、通常のフォトリソ
グラフィ技術により、レジストをパターンニングすると
、図2(b) に示すように、ストレートバンプ16部
でのレジスト18の被膜特性が悪くなり、バリアメタル
5を選択エッチングする際に、図2(c) に示すよう
に、ストレートバンプ16直下のバリアメタル5がオー
バーエッチングされたり、さらにエッチング液がアルミ
パッド3部まで侵入しアルミパッド3がエッチングされ
腐食3aが発生するという問題があった。
However, in order to selectively etch the barrier metal 5 underlying the straight bump 16 having vertical sidewalls, when a resist is patterned using a normal photolithography technique, as shown in FIG. 2(b). As shown in FIG. 2(c), the film characteristics of the resist 18 at the straight bump 16 portion deteriorate, and when selectively etching the barrier metal 5, the barrier metal 5 directly under the straight bump 16 is over-etched, as shown in FIG. 2(c). There was a problem in that the aluminum pad 3 was etched and the etching solution penetrated into the aluminum pad 3, etching the aluminum pad 3 and causing corrosion 3a.

【0005】この発明の目的は、上記問題を解決するた
めに、バンプ形成後、バンプ下層にあるバリアメタルの
エッチング時におけるレジストの被膜特性を改善するこ
とのできる半導体装置の製造方法を提供することである
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the film characteristics of a resist during etching of a barrier metal under a bump after forming a bump. It is.

【0006】[0006]

【課題を解決するための手段】この発明の半導体装置の
製造方法は、バリアメタルを形成した半導体基板上にバ
ンプを形成する工程とバリアメタルを選択エッチングす
る工程とを含むものである。バンプを形成する工程は、
半導体基板上にネガ型レジストを厚く塗布し、このネガ
型レジストをオーバー露光し、断面が逆テーパー状のレ
ジストパターンを形成し、このレジストパターンをマス
クとして電解メッキ法によりバンプを形成するものであ
る。
A method of manufacturing a semiconductor device of the present invention includes the steps of forming bumps on a semiconductor substrate on which a barrier metal is formed and selectively etching the barrier metal. The process of forming bumps is
A negative resist is applied thickly onto a semiconductor substrate, the negative resist is overexposed, a resist pattern with a reverse tapered cross section is formed, and bumps are formed by electrolytic plating using this resist pattern as a mask. .

【0007】[0007]

【作用】この発明の構成によれば、バリアメタルを形成
した半導体基板上にネガ型レジストを厚く塗布し、この
ネガ型レジストをオーバー露光し、断面が逆テーパー状
のレジストパターンを形成し、このレジストパターンを
マスクとして電解メッキ法によりバンプを形成すること
により、その後のバリアメタルを選択エッチングする時
におけるレジストの被膜特性を改善することができる。
[Operation] According to the structure of the present invention, a negative resist is applied thickly to a semiconductor substrate on which a barrier metal is formed, and this negative resist is overexposed to form a resist pattern with a reversely tapered cross section. By forming bumps by electrolytic plating using a resist pattern as a mask, it is possible to improve the film characteristics of the resist during subsequent selective etching of the barrier metal.

【0008】[0008]

【実施例】この発明の一実施例について図面を参照しな
がら説明する。図1はこの発明による半導体装置の製造
方法を示す工程順断面図である。まず、図1(a) に
示すように、シリコン基板1上に絶縁膜2,アルミパッ
ド3および保護膜4の形成を終了した後、例えばTi,
Pt,W,Pd等を5000〜8000Å蒸着して2〜
3層からなるバリアメタル5を形成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a step-by-step sectional view showing a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1(a), after forming an insulating film 2, an aluminum pad 3, and a protective film 4 on a silicon substrate 1, for example, Ti,
Pt, W, Pd, etc. are deposited to a thickness of 5,000 to 8,000 Å and
A barrier metal 5 consisting of three layers is formed.

【0009】つぎに、ネガタイプの厚膜レジストを膜厚
15〜20μm塗布する。そして、パターン形成時に露
光時間を通常より長く(オーバー露光)して、断面形状
が図1(b) に示すように、逆テーパー状のレジスト
7になるようにする。つぎに、レジスト7をマスクとし
て、Auの電解メッキ液にて電解メッキすることにより
、Auメッキ後のバンプ6の断面形状は、図1(c) 
に示すように、順テーパーになる。
Next, a negative type thick film resist is applied to a thickness of 15 to 20 μm. Then, during pattern formation, the exposure time is made longer than usual (overexposure) so that the cross-sectional shape of the resist 7 becomes inversely tapered as shown in FIG. 1(b). Next, by electrolytically plating with an Au electrolytic plating solution using the resist 7 as a mask, the cross-sectional shape of the bump 6 after Au plating is as shown in FIG. 1(c).
As shown in the figure, it becomes a forward taper.

【0010】その後、レジスト7を除去し、バリアメタ
ル5のエッチング用として、フォトリソグラフィ技術に
よりパターンニングしたレジスト8を形成する(図1(
d) )。そして、バリアメタル5を選択エッチングし
て、レジスト8を除去する(図1(e) )。
Thereafter, the resist 7 is removed, and a resist 8 patterned by photolithography is formed for etching the barrier metal 5 (see FIG. 1).
d) ). Then, the barrier metal 5 is selectively etched to remove the resist 8 (FIG. 1(e)).

【0011】以上のようにこの実施例によれば、バンプ
6の断面形状を順テーパーとすることにより、レジスト
8(図1(d) )の被膜特性がよく、バンプ6の下部
までレジスト8が十分覆われ、バンプ6の直下のバリア
メタル5のオーバーエッチングが防止でき、バンプ6と
バリアメタル5の接触面積も十分広くなりバンプ6の接
着強度が向上する。さらに、アルミパッド3のエンチン
グ液による腐食という不良もなくなり、歩留りや信頼性
が向上する。
As described above, according to this embodiment, by making the bump 6 have a forward tapered cross-sectional shape, the film characteristics of the resist 8 (FIG. 1(d)) are good, and the resist 8 extends to the bottom of the bump 6. The bumps 6 are sufficiently covered, preventing over-etching of the barrier metal 5 directly under the bumps 6, and the contact area between the bumps 6 and the barrier metal 5 is sufficiently wide, so that the adhesive strength of the bumps 6 is improved. Furthermore, defects such as corrosion of the aluminum pad 3 due to the etching liquid are eliminated, and yield and reliability are improved.

【0012】0012

【発明の効果】この発明の半導体装置の製造方法は、バ
リアメタルを形成した半導体基板上にネガ型レジストを
厚く塗布し、このネガ型レジストをオーバー露光し、断
面が逆テーパー状のレジストパターンを形成し、このレ
ジストパターンをマスクとして電解メッキ法によりバン
プを形成することにより、その後のバリアメタルを選択
エッチングする時におけるレジストの被膜特性を改善す
ることができる。この結果、バンプ直下のバリアメタル
のオーバーエッチングが防止でき、バンプとバリアメタ
ルの接触面積も十分広くなりバンプの接着強度が向上す
る。さらに、アルミパッドのエンチング液による腐食と
いう不良もなくなり、歩留りや信頼性が向上する。
[Effects of the Invention] The method for manufacturing a semiconductor device of the present invention is to apply a thick negative resist onto a semiconductor substrate on which a barrier metal is formed, overexpose the negative resist, and form a resist pattern with a reversely tapered cross section. By forming bumps by electrolytic plating using this resist pattern as a mask, it is possible to improve the film characteristics of the resist when selectively etching the barrier metal afterwards. As a result, over-etching of the barrier metal directly under the bump can be prevented, and the contact area between the bump and the barrier metal is also sufficiently widened, improving the adhesive strength of the bump. Furthermore, defects such as corrosion of the aluminum pad due to the etching liquid are eliminated, improving yield and reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】この発明による半導体装置の製造方法を示す工
程順断面図である。
FIG. 1 is a step-by-step sectional view showing a method for manufacturing a semiconductor device according to the present invention.

【図2】従来の半導体装置の製造方法およびその問題点
を説明するための工程順断面図である。
FIG. 2 is a process-order cross-sectional view for explaining a conventional method of manufacturing a semiconductor device and its problems.

【符号の説明】[Explanation of symbols]

1    シリコン基板 5    バリアメタル 6    バンプ 7    レジスト 1 Silicon substrate 5 Barrier metal 6 Bump 7 Resist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  バリアメタルを形成した半導体基板上
にネガ型レジストを厚く塗布し、このネガ型レジストを
オーバー露光し、断面が逆テーパー状のレジストパター
ンを形成し、このレジストパターンをマスクとして電解
メッキ法によりバンプを形成する工程と、前記バリアメ
タルを選択エッチングする工程とを含む半導体装置の製
造方法。
1. A negative resist is applied thickly to a semiconductor substrate on which a barrier metal has been formed, and this negative resist is overexposed to form a resist pattern with a reversely tapered cross section. Using this resist pattern as a mask, electrolysis is performed. A method for manufacturing a semiconductor device, including the steps of forming bumps by plating and selectively etching the barrier metal.
JP2403640A 1990-12-19 1990-12-19 Manufacture of semiconductor device Pending JPH04217324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2403640A JPH04217324A (en) 1990-12-19 1990-12-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2403640A JPH04217324A (en) 1990-12-19 1990-12-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04217324A true JPH04217324A (en) 1992-08-07

Family

ID=18513367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2403640A Pending JPH04217324A (en) 1990-12-19 1990-12-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04217324A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260803A (en) * 1999-01-05 2000-09-22 Citizen Watch Co Ltd Semiconductor device and manufacturing method thereof
JP2007073919A (en) * 2005-09-06 2007-03-22 Tanemasa Asano Protrusion electrode manufacturing method and baking apparatus and electronic apparatus used therefor
JP2013045843A (en) * 2011-08-23 2013-03-04 Kyocera Corp Electrode structure, semiconductor element, semiconductor device, thermal head, and thermal printer
WO2018123626A1 (en) * 2016-12-26 2018-07-05 日本ゼオン株式会社 Negative resist composition for protruding electrode and method for manufacturing protruding electrode
JP2020177977A (en) * 2019-04-16 2020-10-29 パナソニックIpマネジメント株式会社 Manufacturing method of semiconductor devices

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000260803A (en) * 1999-01-05 2000-09-22 Citizen Watch Co Ltd Semiconductor device and manufacturing method thereof
JP2007073919A (en) * 2005-09-06 2007-03-22 Tanemasa Asano Protrusion electrode manufacturing method and baking apparatus and electronic apparatus used therefor
JP2013045843A (en) * 2011-08-23 2013-03-04 Kyocera Corp Electrode structure, semiconductor element, semiconductor device, thermal head, and thermal printer
WO2018123626A1 (en) * 2016-12-26 2018-07-05 日本ゼオン株式会社 Negative resist composition for protruding electrode and method for manufacturing protruding electrode
JP2020177977A (en) * 2019-04-16 2020-10-29 パナソニックIpマネジメント株式会社 Manufacturing method of semiconductor devices

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