JPH0421942B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interleave circuit in a PCM device.

Interleaving refers to a method of changing the arrangement of data during recording to disperse long burst-like errors during playback. With this method, mean value interpolation etc. can be easily applied and correction noise can be reduced.

By the way, in magnetic recording, it is known that burst errors are more dominant than random errors. In the case of the burst error described above, the error occurs in consecutive words, and the effects of pre-holding and mean value interpolation are weakened. Therefore, if the word arrangement is changed in the recording system and recorded, and then restored to the original arrangement in the reproduction system, it is possible to convert the error into a sharp error and increase the effect of correction.

FIG. 1 shows an interleave circuit in a conventional PCM device. In Figure 1, 1A, 1
B and 1C are 11-bit counters for memory addresses, and 2 is a ROM (Read Only) for interleaving.
3 is a NAND gate, and 4 is an inverter. Clock terminal of counter 11A mentioned above
CK is supplied with a clock from terminal _T1 .
For example, when a VTR is used as a recording/reproducing system, this clock is used to control data blocks arranged in 1H intervals in a pseudo video signal in which a PCM signal is converted into a signal format similar to a standard television signal. Our sampled signal words L ₁ , R ₁ , L ₂ ,
This is a signal consisting of R ₂ , L ₃ , R ₃ and error correction words P and Q. In addition, the clock terminal CK of the counters 1B and 1C has an output Q _C from the counter 1A.
(Supplied via the inverter 4.The above-mentioned clear terminal CL of the counter 1A is connected to the above-mentioned terminal _T1 .
L ₁ , R ₁ , L ₂ , R ₂ , L ₃ , R ₃ , P, Q supplied to
The pulse that is output once every time is supplied as a clear pulse from terminal _T2 . Also, counter 1
The output of the NAND gate 3 which inputs the outputs Q _B and Q _D of the counter 1C is supplied to the clear terminal CL of the counters B and 1C. This is for clearing the counters 1B and 1C described above when the counters 1B and 1C complete a predetermined count.
Counter 1A, 1 for the memory address mentioned above
The counts of B and 1C are incremented by the above-mentioned clock, and the ROM for interleaving is
The output of counter 2 is determined by a total of 7 bits, including the lower 3 bits of counter 1A and the upper 4 bits of counter 1C. By configuring in this way, interleaving addresses A ₀ to A ₁₀ (counter 1A
A ₀ , A ₁ , A ₂ from counter 1B, A ₃ from counter 1B,
A ₄ , A ₅ , A ₆ , A ₇ , A ₈ , A ₉ , A ₁₀ from ROM2 for interleaving are counters 1A, 1
It is designed to indicate a value 16 x 8 x (the value of counter 1A) earlier than the values (decimal) indicated by B and 1C. Note that when interleaving, each sampled signal word L ₁ , R ₁ , L ₂ , R ₂ ,
L ₃ , R ₃ and error correction words P and Q are subjected to 16H interleaving.

As described above, in conventional devices, a ROM is used in the interleave circuit. this
Those that use ROM have the drawbacks that they consume more power and are more economically expensive than those that use general TTL.

The present invention has been made with the aim of solving these drawbacks of the prior art.

An embodiment of the interleave circuit according to the present invention will be described below with reference to FIG.

In FIG. 2, 11A, 11B, and 11C are counters for memory addresses, 12 is an adder that specifies the address of the basic memory, 13 is an adder that specifies the address of additional memory, and 14 is AND with OR gates 14A and 14C. The gate 14B determines the use of additional memory, and the adder 12
15 is a NAND gate; 15 is a NAND gate;
16, 17, and 18 are inverters.

Adder 12 and adder 13 are connected in series, and a part of the output of adder 12 is input to determination circuit 14,
The output of the determination circuit 14 is input to the adder 13.

From terminal _T1 is the clock terminal of counter 11A.
CK is supplied with a clock similar to that described above.
Similarly, a pulse similar to that described above is supplied as a clear pulse from the terminal _T2 to the clear terminal CL of the counter 11A. Note that the counter 11 mentioned above
The clock terminal CK of B and 11C is supplied with a pulse similar to that supplied to the terminal _T2 described above as a clock from the terminal _T3 . The clear terminals CL of the counters 11B and 11C are supplied with the output of a NAND gate 15 which receives the outputs Q _A and Q _D of the counter 11C and the output from the carry terminal C of the counter 11B.

The output of the adder 12 is divided into the upper 4 bits (outputs Q _A , Q _B , Q _C , Q _D of the counter 11C) to the lower 3 bits (output outputs Q _A , Q _B , Q _C of the counter 11A) to the inverters 16 , 17 . , 18).

In the circuit having the above configuration, A ₀ , A ₁ , A ₂ from the counter 11A, A ₃ , A ₄ , A ₅ , A ₆ from the counter 11B, Σ ₁ , Σ ₂ from the adder 12,
Even if Σ ₄ is an address for interleaving, these are memory address counters 11A and 1.
From the values indicated by 1B and 11C, 16×8×(counter 1
1A) can indicate the previous value.
However, in the embodiment shown in FIG. 2, the word array memories (usually random access memories) connected to the outputs A ₀ , A ₁ , ...A ₁₀ are combined with various capacities. It is assumed that you will use it. In other words, rather than using multiple memories of the same capacity, in order to reduce the overall memory capacity as much as possible, it is assumed that memory of a certain capacity will be used as the basic memory and memory of a different capacity will be added to this.

Therefore, if the address refers to additional memory that has been added rather than the base memory, it must be entered into that additional memory. That is, when it can be input into the basic memory, it is input there, but when it cannot be input, the input must be switched to the additional memory. For this reason, in addition to the adder 12, an adder 13 and a determination circuit 14 are provided. That is, determination circuit 1
4, the use of additional memory is determined. If the additional memory is not used, the address indicates the basic memory, so the determining circuit 14 determines that the basic memory is entered, and outputs the output of the adder 12 as is from the adder 13. Then input it into basic memory. In addition, in the case of using additional memory, since the address does not indicate the basic memory, the determination circuit 14 determines that it does not fit into the basic memory, and the adder 13 adds 1 to the 2 bits output from the adder 12 and outputs the result. . Then input it into additional memory. In this way, correct interleaving can be performed even when using a combination of devices with various capacities.

As described above, the present invention is based on the conventional ROM
Instead, an interleave circuit is constructed using two adders and a determination circuit. Therefore, the present invention not only consumes less power and is economically inexpensive, but also has the effect of reducing the capacity of the word array memory to which the output is connected. .

[Brief explanation of drawings]

FIG. 1 shows an interleaving circuit in a conventional device, and FIG. 2 shows an embodiment of an interleaving circuit according to the present invention. 11A, 11B, 11C...Memory address counter, 12, 13...Adder, 14...
Judgment circuit, 15...NAND gate, 16, 17,
18...Inverter.

Claims (1)

[Claims] 1. An adder that specifies the address of the basic memory in the addressing section that is interposed in the recording system of the PCM device, has a memory consisting of a basic memory and an additional memory, and constitutes an interleave circuit that changes the arrangement of words. and an adder that specifies the address of the additional memory are connected in series,
An interleave circuit in a PCM device, characterized in that a part of the output of the adder at the front stage is input to a determination circuit that determines the use of the additional memory, and the output of the determination circuit is input to the adder at the rear stage.