JPH0421955B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device that can improve access time and reduce power consumption.

[Prior art]

FIG. 1 is a block diagram showing a conventional semiconductor memory device. In the figure, 1 is a memory cell;
2a and 2b are a pair of complementary bit lines, 3 is a word line that activates memory cells on the same row when selected, 4 is a row decode that decodes row address information, and 5 is a row address signal line. ,6a
and 6b is a bit line load connected to the bit lines 2a and 2b, 7 is a power supply terminal, 8 is a sense amplifier whose input is the bit lines 2a and 2b, 9 is a read data line, and 10 is a column for decoding the column address signal. Decoder, 11 is a column address signal line, 12
is a memory cell array consisting of the memory cells 1 arranged in rows and columns.

Note that in the memory cell 1 shown in FIG.
13a and 13b are load elements composed of MOS transistors, resistors, etc.; 14a and 14b;
are inverter transistors, 15a and 15b
is an access transistor, and 16a and 16b are storage nodes of memory cell 1.

Next, the operation of the semiconductor memory device having the above configuration will be described, as an example, in the case where store nodes 16a and 16b are written to "H" level and "L" level, respectively.
First, in the case of reading, the row address information of the cell to be read is input to the row address signal line 5. The row address information is then decoded by the row decode 4, and one word line 3 is activated. Next, the access transistor 15b storing the "L" level becomes conductive, and the bit line load 6b is connected from the power supply terminal 7 to the bit line 2b to the access transistor 15.
b, current flows through the path of inverter transistor 14b, and bit line 2b drops from the precharge level. On the other hand, the column address signal input to the column address signal line 11 of the cell to be read is decoded by the column decode 10, and one sense amplifier 8 corresponding to the selected column is activated. Therefore, bit lines 2a and 2b of the selected column
The potential difference is sensed and amplified, and the read data line 9
A read operation is performed.

In conventional semiconductor memory devices, all memory cells on the same selected row are activated, so current flows from the power supply to the memory cells in all columns, reducing power consumption when configuring a large capacity memory with many columns. There was a growing flaw.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and includes a plurality of partial memory cell groups in which a memory cell array in which memory cells are arranged in rows and columns is divided and arranged in the column direction, and a plurality of partial memory cell groups. A plurality of divided word lines are provided separately for each of the partial memory cell groups and are arranged for each row of memory cells, and a plurality of divided word lines are provided in common to the plurality of partial memory cell groups and are arranged for each row of memory cells. Upper row selection lines arranged, upper row decoding means for decoding the upper row address signal and selectively driving any one of the upper row selection lines, and decoding the lower row address signal and the upper column address signal. Each divided word line is selectively activated based on the output of the upper row selection line and the output of the sub-decoding means, thereby achieving high speed and low power consumption. The purpose is to provide a large capacity semiconductor memory using electric power without increasing the chip area.

[Embodiments of the invention]

FIG. 3 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention. As an example, the number N of partial memory cell groups obtained by dividing the memory cell array in the column direction is 4, and the upper row selection for each partial memory cell group is 4. The case where the number M of rows in which lines are arranged is set to 2 is shown. In the figure, 3a is an upper row selection line, 4a is an upper row decode line, 5a is an upper row address signal line,
5b is a lower row address signal line, 10a is a lower column decode, each partial memory cell group of the memory cell array is divided into four parts 12a, 12b, 12c, and 12d, 11a is a lower column address signal line, and 11b is an upper column address. Signal line 17 is a sub-decode for decoding both the lower row address and the upper column address, 1
8 is a sub-decoder output, 19 is an AND gate whose inputs are the upper row selection line 3a arranged parallel to the word line 3 and the sub-decoder output 18 arranged perpendicularly to the word line 3; It is connected. Note that the word line 3 and the upper row selection line may be in the same layer or in different layers.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, upper row address signal line 5
The upper row decoder decodes the upper row address information inputted to a and activates one of the upper row selection lines arranged every two rows. On the other hand, the sub-decode 17 decodes both the upper column address information and the lower row address information, and selects one of the two rows of the partial memory cell groups 12a to 12d. Since the AND gate 19 generates a logical product of the upper row selection signal and the sub-decode output, only one word line of one block is activated. The following read operation is the same as in the conventional case.

The current flows from the power supply 7 to the memory cell 1 through the bit line load 6a or 6b and the bit line 2a or 2b only in the column in one selected partial memory cell group, compared to all columns in the conventional case. It decreases to 1/2. Furthermore, since the length of the word line 3 is shortened to one-fourth of that in the conventional case, the word line delay is shortened to one-sixteenth of the square of the number of divisions, and high-speed operation is possible. Further, since each AND gate 19 has a small area and is divided into only four pieces in the word line direction, the increment in chip size in the word line parallel direction is small. Furthermore, since there is one upper row selection line for every two rows, the increment in chip size in the word line vertical direction is smaller than if the upper row selection lines are arranged in each row, and the interval between adjacent upper row selection lines 3a can be increased. The line-to-line parasitic capacitance is small, and the delay in the selection time of the upper row selection line is suppressed compared to those arranged in each row, thereby shortening the access time. Furthermore, compared to those arranged in each row, bit lines 2a, which are arranged orthogonally to the upper row selection line 3a,
The number of intersections with 2b is small, and the upper row selection line 3
The number of failures due to poor insulation at the intersections between the upper row selection line 3a and the bit lines 2a and 2b is reduced, and the yield and reliability are good.
Since the parasitic capacitance between the bit lines 2a and 2b is small, when reading information from the memory cell 1 and writing information to the memory cell 1, the bit lines 2a and 2b are
The time and amount of charge required for charging and discharging the battery 2b are small, and high speed and low power consumption can be achieved.

In the above embodiment, the case where N=4 and M=2 was explained, but it goes without saying that other values may be used. In addition, as shown in Figure 2 as a memory cell,
Although the case of an NMOS static memory cell is shown, any other memory cell, e.g.
It may be a CMOS static type memory cell or a dynamic type memory cell. Furthermore, although the AND gate 19 is shown arranged at the end of the partial memory cell group, it may be arranged at another position, for example, at the center of the partial memory cell group. Further, although the word line is driven by the AND signal of the upper row selection signal 3a and the sub-decode output signal 18, the logic of 3a and 18 may be inverted, and the word line may be driven by their NOR signal.

〔Effect of the invention〕

As explained above, according to the semiconductor memory device according to the present invention, memory cell selection is performed hierarchically in two stages: the upper row selection line and the word line, so it can achieve low power consumption and high speed. This has the advantage that a large capacity semiconductor memory device can be constructed.

Moreover, since the upper row selection line is arranged for each row of memory cells, the increment in chip size in the vertical direction of the word line can be made smaller than when the upper row selection line is arranged for each row. The line-to-line parasitic capacitance in the upper row selection line 3a can be reduced, the delay in the selection time of the upper row selection line can be suppressed, and the access time can be shortened. 2
The number of intersections between the upper row selection line 3a and the bit lines 2a and 2b is small, and failures due to poor insulation at the intersections between the upper row selection line 3a and the bit lines 2a and 2b are reduced, improving yield and reliability. Since the parasitic capacitance between the line 3a and the bit lines 2a, 2b is small, the time and charge required for charging and discharging the bit lines 2a, 2b when reading information from the memory cell 1 and writing information to the memory cell 1 is small. This has the effect of requiring only a small amount and achieving higher speed and lower power consumption.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional semiconductor memory device, Fig. 2 is a circuit diagram showing a memory cell, and Fig. 3 is a block diagram showing a conventional semiconductor memory device.
FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention. 1...Memory cell, 2a, 2b...Bit line, 3...Word line, 4...Row decode, 5...
Row address signal lines, 6a, 6b...Bit line load, 7...Power terminal, 8...Sense amplifier, 9...
...Read signal line, 10...Column decoder, 11...
...Column address signal line, 12...Memory cell array, 13a, 13b...Load element, 14a, 14
b...Inverter transistor, 15a, 15b
...Access transistor, 16a, 16b...
Storage node, 3a...Upper row selection line, 4a
...Upper row decoder, 5a...Upper row address signal line, 5b...Upper row address signal line, 10a...
...Upper column address signal line, 11a...Lower column address signal line, 11b...Upper column address signal line,
12a, 12b, 12c, 12d... memory cell group, 17... sub decoder, 18... sub decoder output line, 19... AND gate.

Claims (1)

[Scope of Claims] 1. A plurality of partial memory cell groups in which a memory cell array in which memory cells are arranged in rows and columns is divided and arranged in the column direction; and each of the plurality of partial memory cell groups is provided separately, and a plurality of divided word lines arranged for each row of the memory cells; and a plurality of divided word lines that pass through the plurality of partial memory cell groups and are provided in common to each partial memory cell group, and are arranged for each of the plurality of rows of the memory cells. an upper row selection line arranged in the upper row selection line; upper row decoding means for decoding the upper row address signal and selectively driving any one of the upper row selection lines; a lower row address signal and an upper column address signal. and sub-decoding means for decoding, and one of the divided word lines is selectively activated based on the output of the upper row selection line and the output of the sub-decoding means. A semiconductor memory device.