JPH0421991A - Storage device - Google Patents

Abstract

PURPOSE:To discriminate whether data error is caused by the fault of an RF (refresh) control system, storage part control system or storage part system by monitoring a time interval to be moved from an RF operation to a normal operation according to the RAS signal and under-RE signal of the RF control system. CONSTITUTION:Since an edge detection circuit 1 turns an RF end signal 103 to 1 when an under-RF signal 102 is logic 1 and an RAS signal 100 is changed from 1 to 0, the 1 is set to an F/F 2 and a counter 3 starts counting-up. From the change of the signal 100 to 0 to the next change from 0 to 1, namely, from the end of the RF operation to the start of the normal operation, when the interval is enough wide, namely, in the case of the normal operation, the F/F 2 is reset and even when a complement output signal 105 is turned to 1, the counter 3 is stopped at a prescribed value. Therefore, an RAS interval check signal 106 is not turned to 1, 0 is outputted from an AND gate 4 as a gate signal 107 and the generation of error is not detected.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a storage device, and in particular to a storage device such as a CA S (Coluo
+nAddress 5trobe) Before RA
The present invention relates to a method for detecting abnormal termination of a refresh circuit in a storage device that performs refresh using the S (Row Addrcss 5 trobe) refresh method.

BACKGROUND ART Conventionally, in this type of storage device, data errors have been detected during a data read operation, but whether a refresh operation has ended normally or abnormally has not been detected.

In such conventional storage devices, the occurrence of an error is detected only by detecting a data error during a data read operation, so it is difficult to determine whether the data error is due to a failure in the refresh control system or whether the storage control system and storage The drawback is that it is difficult to determine whether the problem is due to a system failure.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the conventional system.It is possible to detect a faulty part of the refresh control system, and to determine whether a data error is due to a failure in the refresh control system or whether the data error is due to a failure in the refresh control system or whether the data error is due to a failure in the refresh control system or whether the data error is due to a failure in the refresh control system or whether the data error is due to a The object of the present invention is to provide a storage device that makes it possible to determine whether a failure is due to a failure in a control system or a storage system.

Composition of the Invention A storage device according to the present invention performs a refresh operation using a column address strobe signal and a row address strobe signal that are enabled and disabled at preset timing, and the memory device performs a refresh operation using a column address strobe signal and a row address strobe signal that are enabled and disabled at preset timings, and whether the normal operation is started after a predetermined period of time has elapsed from the end of the refresh operation based on the timing of the refresh operation and the validity/invalid timing of the refresh signal indicating that the refresh operation is being performed. and means for notifying an abnormality in the refresh operation when the detection means detects that the normal operation has started before the predetermined time elapses.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the edge detection circuit 1 is RA S (Ro
w Address 5trobe) signal ioo and C
AS(Column Address 5trobe)
) signal 101 and a refresh in progress signal 102 indicating that a refresh operation is being performed, and outputs a refresh end signal 103 indicating the end of the refresh operation and a normal operation start signal 104 indicating the start of the normal operation. do.

A flip-flop (hereinafter referred to as F/F) 2 is set by a refresh end signal 103 from the edge detection circuit 1 and reset by a normal operation start signal 104.

Further, the F/F 2 outputs the inverted value of its contents to the AND gate 4 as a concomitant output signal 105.

The counter 3 starts counting in response to the refresh end signal 103 from the edge detection circuit 1, and when the count value reaches a predetermined value, outputs the RAS interval check signal 10B to the AND gate 4, and also outputs the RAS interval check signal 10B to the AND gate 4. Stops counting and resets the count value.

Note that the output timing of the RAS interval check signal 108 from the counter 3, that is, the predetermined value in the counter 3, can be arbitrarily set depending on the characteristics of a DRAM (not shown) used in the storage device.

The AND gate 4 performs an AND operation between the concomitant output signal 1'05 from the F/F 2 and the RAS interval check signal 108 from the counter 3, and sends the result to the error detection signal 1'05.
Output as 07.

The edge detection circuit 1 normally outputs logic "0" as the refresh end signal 103, the RAS signal +00 changes from logic "1" to logic "0", and the refreshing signal 102 indicates that the refresh operation is in progress. It outputs logic "1" when it takes logic "1".

Further, the edge detection circuit 1 outputs the normal logic "O" as the normal operation start signal IO4, the RAS signal 101 changes from logic "0" to logic "1", and the refresh in progress signal 102 indicates that the refresh operation is in progress. When the logic value is "0" indicating that the signal is not present, a logic "1" is output.

FIGS. 2 and 3 are timing charts showing the operation of one embodiment of the present invention. Figure 2 shows a timing chart when the transition from refresh operation to normal operation is performed normally, and Figure 3 shows a timing chart when normal operation starts earlier than the specified time after the refresh operation ends. There is.

The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

First, the refresh signal 102 is logic “1°” and R
When the AS signal JOO changes from logic "1" to logic "0", the edge detection circuit 1 sets the refresh end signal I03 to logic "1", so logic "1" is set in F/F2 and the counter 3 starts counting up.

There is a sufficient interval from when the RAS signal 100 changes to logic "0" until it changes from logic "O" to logic "1#", that is, from the end of the refresh operation to the start of normal operation. In the wide case, that is, when the transition from the refresh operation to the normal operation is performed normally, the normal operation start signal 104 from the edge detection circuit 1 becomes logic "1" and before the F/F 2 is reset. , when the count value of the counter 3 reaches a predetermined value, the RAS interval check signal 10 is output.
Since B becomes logic "1", the count value of the counter 3 is reset.

Therefore, even if the F/F 2 is reset and the concomitant output signal 105 becomes logic "1", the RAS interval check signal 10B will not become logic "1" because the counter 3 has stopped counting. Naku, And Gate 4
Logic “O” is output as the output signal 107 from Antogame 1.
is output, and no error is detected (see Figure 2).

Note that when the RAS interval check signal 106 from the counter 3 becomes logic "1", the concomitant output signal 105 from the F/F 2 is logic "0", so the AND gate output signal 107 from the AND gate 4 becomes logic "1". O"
is output.

Here, if the normal operation after the end of the refresh operation starts earlier than the specified time, the count value of the counter 3 becomes the specified value and the RAS interval check signal 106 becomes logic "1".
Before this occurs, the normal operation start signal 104 from the edge detection circuit 1 becomes logic "1" and the F/F 2 is reset.
Combiment output signal 105 to AND gate 4 becomes logic "1".

In this state, when the count value of the counter 3 reaches a predetermined value and the RAS interval check signal 1011 becomes logic "1", the AND gate 4 outputs logic "1" as the error detection signal 107, indicating that the refresh operation has ended abnormally. An error is notified (see Figure 3).

The refresh operation at this time may result in a shortage of DRAM precharge time, that is, the time required for recharging the DRAM capacitor, and the data stored in the DRAM may be destroyed.

In this way, by monitoring the time interval when transitioning from refresh operation to normal operation using edge detection circuit 1, F/F 2, counter 3, and AND gate 4, abnormalities in the end state of refresh operation can be detected. can be detected.

Therefore, it is possible to determine whether the cause of a data error when continuously outputting data from the storage unit (not shown) is due to a failure in the refresh control system or a failure in the storage unit control system and the storage unit. .

Furthermore, since the predetermined value in the counter 3, that is, the output timing of the RAS interval check signal 106, can be set according to the characteristics of the DRAM,
The present invention can also be applied to

Effects of the Invention - As described, according to the present invention, by monitoring the time interval when transitioning from refresh operation to normal operation using the RAS signal and the refresh control signal of the refresh control system, This has the effect of being able to detect a failure in the refresh control system and making it possible to determine whether a data error is due to a failure in the refresh control system or a failure in the storage control system and storage system. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 2 and 3 are timing charts showing the operation of the embodiment of the invention. Explanation of symbols of main parts 1... Edge detection circuit 2... Flip-flop 3... Counter 4... AND gate

Claims (1)

[Claims] (1) A memory device that performs a refresh operation using a column address strobe signal and a row address strobe signal that are enabled and disabled at preset timings, the timing of enabling and disabling the row address strobe signal and the refresh operation a detection means for detecting whether or not normal operation is started after a predetermined period of time has elapsed from the end of the refresh operation based on the validity and invalidity timings of a refresh in progress signal indicating that the refresh operation is being performed; A storage device comprising: means for notifying an abnormality in the refresh operation when the detection means detects that the normal operation has started before the predetermined time elapses.