JPH0498682A - Refresh error detecting system - Google Patents

Abstract

PURPOSE:To detect illegal refresh without fail by detecting refresh error during the time from refresh detection to the next refresh detection. CONSTITUTION:A refresh detection circuit 2 discriminates refresh at timing for the RAS and CAS signal lines of a control line 10 and reports it to a transmission line 11. A time monitor circuit 3 is a timer operated at all times, and when it is reported from the transmission line 111 that refresh is detected, the circuit 3 is reset. Then, after the passage of time longer than the rated value of the refresh cycle time of a dynamic RAM used for a memory element 1, refresh error is reported to a transmission line 12. Thus, refresh can be detected without fail.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a refresh error detection method.

[Conventional technology]

Conventionally, this type of refresh error detection method detects a refresh request signal that triggers refresh execution, and the time between detecting the next refresh request signal is
When the refresh cycle time of the dynamic RAM used exceeds the standard, it is determined that a refresh error has occurred.

[Problem to be solved by the invention]

In the conventional refresh error detection method described above, errors are determined based on the refresh request signal that triggers refresh execution. This has the drawback that the timing of the control signal is incorrect, making it impossible to detect errors in cases other than refresh for dynamic RAM.

[Means to solve the problem]

The refresh error detection method of the present invention includes a refresh detection circuit that determines refresh based on the timing of a control signal connected to a control input of a dynamic RAM;
It has a time monitoring circuit that determines that a refresh error has occurred when the time from when the refresh detection circuit detects a refresh to when the next refresh is detected exceeds the refresh cycle time standard of the dynamic RAM being used. are doing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The memory element 1 is a dynamic RAM in which data is written, read, or refreshed using a control line 10 including RAS and CAS signal lines.

The refresh detection circuit 2 uses the control lines 10 RAS and CA.
Based on the timing of the S signal line (other signals are observed if necessary), refresh is determined and reported to the transmission line 11.

The time monitoring circuit 3 is a timer that is constantly operating,
It is reset when a report is received from the transmission line 11 that refresh has been detected, and if a time longer than the standard refresh cycle time of the dynamic RAM used in the storage element 1 has passed, the transmission line 12 is reset. Report an error.

Next, a description will be given of how refresh is determined based on the timing of the RAS and CAS signal lines.

Figures 3, 4, and 5 are typical dynamic RAs.
FIG. 4 is a timing chart of RAS and CAS of each operation in M. FIG. 3 is a timing diagram for reading and writing data, FIG. 4 is a timing diagram for RAS only refresh, and FIG. 5 is a timing diagram for CAS before RAS refresh.

Comparing FIG. 3 with FIGS. 4 and 5 based on the RAS signal, the timing of the CAS signal is different. In other words, the relationship between the RAS signal and the CAS signal for general refresh in dynamic RAM is different from the relationship between the RAS signal and the CAS signal for read and write operations.

Refreshing can be detected by checking the timing of the CAS signal.

Also, it is possible to detect whether normal refresh is being performed. (In order to strictly check whether RAS-only refresh is being performed normally, it is necessary to check the address signal at the same time.) Figure 6 is a timing diagram of CAS-before-RAS refresh, which is an example. It shows the timing with the clock used in the device.

FIG. 2 shows an embodiment of a refresh detection circuit for a storage device that performs a refresh operation using the CAS before RAS refresh shown in FIG.
Control line 10 (7) RAS in the figure.

Corresponding to the CAS signal line, the transmission line 47 is the transmission line 1 in FIG.
It corresponds to 1.

The buffer 20 receives the RAS signal on the control line 40 and outputs it to the signal line 43, and the buffer 21 receives the CAS signal on the control line 41.
The signal is input and output to the signal line 44, and the inverter 2
The inverter 2 inputs the signal line 43, inverts the value, and outputs it to the signal line 45, and the inverter 23 inputs the signal line 44, inverts the value, and outputs it to the signal line 46.

Registers 29, 30, 31, and 32 are flip-flops that are activated by the rising edge of the clock line 42 signal. Since the AND gate 24 receives the signal lines 43 and 44 and performs a logical product, the To timing shown in FIG. 6 is checked.

Since the register 29 takes in the output of the AND gate 24 as a data input at the rising edge of the clock line 42 and outputs it to the AND gate 25, the register 29 receives the result checked by the AND gate 14 at the TO timing in FIG.
This will delay the timing.

AND gate 25 connects signal lines 43, 48 . register 2
Since the output of 9 is used as the input and the logical product is calculated, the To and TI timings in FIG. 8 are checked. Registers 30, 31, and 32 are AND gates (AND gates) connected to data inputs like register 29.) The results checked in steps 25, 28, and 27 are delayed to the next timing.

AND gates 26, 27, 28, like AND gate 25, are connected to TO to T2. This means that the timings of To-T3° and To-T4 are respectively investigated. RA in Figure 6
S, CAS To-T4 timing is CAS before R
Since this is an AS refresh, the transmission line 47, which is the output of the AND gate 28, outputs logic "1" at timing T4 when the CAS before RAS refresh is normally performed.

〔Effect of the invention〕

As explained above, the present invention is applicable to Dyna-type RAM and Mic-type RAM.
By detecting refresh based on the timing of the control signal connected to the control input of Therefore, it becomes possible to reliably detect refresh irregularities that cause large-scale loss of stored data, which has the effect of improving reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the refresh detection circuit shown in FIG. 1, and FIG. 3 is a timing diagram of RAS and CAS during reading and writing. Figure 4 shows RAS-only refresh RA
S, CAS timing diagram, Figure 5 is CAS before R
AS Refresh Timing Diagram FIG. 6 is a timing diagram of CAS before RAS refresh. 1... Memory element, 2... Refresh detection circuit, 3
...Time monitoring circuit, 10...Control line, 11.12.
...Transmission line, 20.21...Buffer, 22.23.
...Inverter 24-28...AND gate, 2
9-32...Register, 40.41...Control line, 4
2-...Clock line, 43-46...Signal line, 47-
...Transmission line.

Claims (1)

[Claims] A refresh detection circuit that determines refresh based on the timing of a control signal connected to a control input of a dynamic RAM, and a dynamic RAM that uses the time from when the refresh detection circuit detects a refresh to when it detects the next refresh. 1. A refresh error detection method comprising: a time monitoring circuit that determines a refresh error when the refresh cycle time of a type RAM exceeds a standard.