JPH04219971A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To easily layout a pattern by a method wherein the width of a circuit region limited by a memory cell size is constituted so as to be capable of being expanded to a length covering a plurality of columns in the case of buffers arranged in a column direction and to a length covering a plurality of rows in the case of buffers arranged in a row direction. CONSTITUTION:Two Y-decoder-based circuits and two sense amplifiers are arranged respectively at the inside of regions 201, 202. The width in the word- line direction of the Y-decoder-based circuits + column sense amplifiers 101, 102, 103, 104 in the individual rows is ensured so as to cover two columns. The length in the bit-line direction of the regions 201, 202 is not limited by a memory cell size. Consequently, individual buffers for 101, 102 and 103, 104 can be laid out comparatively freely in the bit-line direction and the column direction at the inside of the regions 201 and 202, and a layout pattern can be formed easily.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to the layout of circuits located in the periphery of a static RAM memory cell array.

0002

[Prior Art] Figure 3 shows, for example, a digest of the I.I.I. International Solid State Circuits Conference 1990.
of Technical Papers, pages 132-133 Figure 3 (IEEE International S
solid-State Circuits Confe
rence 1990, DIGEST OF TEC
HNICAL PAPERS, P. 132-133,
FIG. 3 is a block diagram showing the configuration of a read circuit around the bit line of the static RAM shown in Figure 3). In the figure, 1 is a memory cell, 2 is a bit line pair, 3 is a bit line load that charges or equalizes the bit line pair 2, 4 is a word line, and 5 is an X decoder that selects and drives the word line 4. circuit, 8 is a data line pair, 6
Reference numerals denote a pair of transfer gates for controlling data transmission between the bit line pair 2 and the data line pair 8, 7 a Y decoder circuit, 9 a sense amplifier, and 10 a data line.

Next, the operation at the time of reading will be explained. Selection of the memory cell 1 is realized when the X decoder circuit 5 and the Y decoder circuit 7 are simultaneously selected. At this time,
Word line 4 is at a high level, and transfer gate pair 6 electrically connects bit line pair 2 and data line pair 8. As a result, the data stored in the memory cell 1 is transmitted to the sense amplifier 9 via the bit line pair 2 and the data line pair 8, and the amplified signal is transmitted to the data line 10. The data line 10 is connected to an output buffer (not shown) and data is output to the outside of the chip.

On the other hand, if the memory cell 1 is not selected, then the X decoder circuit 5 or the Y decoder circuit 7
, or when both circuits 5 and 7 are in a non-selected state, the stored data of the memory cell 1 is not transmitted to the data line pair 8, and at this time, the stored data of another memory cell (not shown) in the selected state is transmitted. only is transmitted to data line pair 8. FIG. 4 is a diagram showing an example of the physical arrangement of the circuit blocks shown in FIG. 3. In FIG. Here, a static RAM having a memory cell array of n columns and m rows is taken as an example. 11, 12, 21
, 22 indicate the memory cells at the four corners of the memory cell array each having a rectangular shape, 11 is the memory cell in the 1st column, 1st row, 12 is the memory cell in the 1st column, m-th row, and 21 is the memory cell in the 1st row, in the n-column. The memory cell 22 is the memory cell in the nth column and the mth row. 15, 25, 17, 2
7 shows the arrangement of the X and Y decoder circuits for selecting each cell, 15 is the X decoder circuit in the first row, 25 is the X decoder circuit in the mth row, and 17 is the Y decoder circuit in the first column. The circuit 27 is a Y decoder circuit in the n-th column. In addition, in this example, the bit line load 13 of each column is
, 23 and transfer gate pairs 16, 26 are arranged to sandwich each column, 13 is the bit line load of the first column, 23 is the bit line load of the nth column, and 16 is the bit line load of the 1st column.
The transfer gate pair in the column 26 is a transfer gate pair in the n-th column.

[0005]

[Problem to be solved by the invention] Conventional static R
Each circuit around the AM memory cell array is arranged as described above, so the width of the X decoder circuit 5 is limited by the length of one memory cell in the bit line direction, and the width of the
The width of circuits arranged in each column at both ends of the column, such as the decoder circuit 7, bit line load 3, and transfer gate pair 6, is limited by the length of one memory cell in the word line direction.

Generally, increasing the capacity of a memory device requires reducing the memory cell size. Therefore, the degree of freedom in the circuit pattern of each of the above-mentioned circuits arranged around the memory cell array is greatly restricted, making pattern creation more difficult.

[0007] Furthermore, the column sense method is an effective means for increasing the speed of static RAM. FIG. 5 shows a configuration diagram of a read circuit around a bit line when a column sensing method is adopted, and FIG. 6 shows an example of the physical layout of FIG. 5. In these figures, the same symbols as in FIGS. 3 and 4 indicate the same or equivalent parts, 19 indicates a column sense amplifier, 14 indicates a column sense amplifier for the first column, and 24 indicates a column sense amplifier for the nth column. . As you can see from these figures, column sense amplifier 1
One side of 9 is also limited by the memory cell size. This column sense amplifier 19 senses a slight change in the bit line pair 2 and quickly transmits this change to the data line pair 8 via the transfer gate 6, so a circuit with good sensitivity and high load driving ability is required. ing. However, it is extremely difficult to employ a column sense amplifier with sufficient performance in a highly integrated static RAM when creating a circuit pattern, considering the number of column sense amplifier elements and area such as transistor size. It had become.

Furthermore, Bi-CMOS static RA
In M, since the bipolar transistor requires a large area, there are problems such as having to restrict the use of bipolar transistors even though there are circuits that require driving power.

The present invention was made to solve the above-mentioned problems, and it increases the degree of freedom in the layout pattern of the peripheral circuit of the memory cell array, facilitates pattern creation, and further increases the degree of freedom in the layout pattern. By increasing the size of semiconductor memory, it is possible to remove restrictions on the pattern of circuits such as column sense amplifiers and bipolar transistors, which were previously largely limited due to area issues, and to freely arrange these circuits, promoting higher performance. The purpose is to obtain equipment.

0010

[Means for Solving the Problems] In a semiconductor memory device according to the present invention, in a circuit around a memory cell array arranged in the row direction of the memory cell array, such as an X decoder circuit, the length of the circuit area in the bit line direction is or, in circuits surrounding the memory cell array arranged in the column direction of the memory cell array, such as Y decoder circuits, column sense amplifiers, and bit line loads, the word width of the circuit area It is set so that the length in the line direction has the width of multiple columns.

Further, in the semiconductor memory device according to the present invention, in the circuits arranged in the row direction of the memory cell array in the circuits surrounding the memory cell array, and the circuits arranged in the column direction of the memory cell array, the bit line direction of the circuit area is The length is set to have a width of multiple rows, and the length in the word line direction is set to have a width of multiple columns.

0012

[Operation] In the circuits arranged in the periphery of the memory cell array according to the present invention, one side of the circuit area is the length of one cell in the bit line direction for circuits located in the column direction, and for circuits located in the row direction One side of the circuit area was limited by the length of one cell in the word line direction, but by relaxing this to the width of a plurality of columns, the degree of freedom in layout patterns increases and pattern creation becomes easier. Furthermore, complex circuits that were previously difficult to fit into a long and narrow area, such as transistors with large gate widths and bipolar transistors, can now be arranged relatively freely, making it possible to improve the performance of devices. It becomes possible.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the arrangement of a static RAM memory cell array and its peripheral circuits in a semiconductor memory device according to an embodiment of the present invention. Here, we will consider a case where two columns' worth of Y decoder system circuits and column sense amplifiers are housed in an area having a width of two columns.

In the figure, the same reference numerals as in FIG. 4 indicate the same or corresponding parts, and 201 is the area of the Y decoder system circuit + column sense amplifier in the 1st and 2nd columns, of which 101
is the area in the first column, and 102 is the area in the second column. 202 is the n-1 and n-th Y decoder circuit +
In the area of the column sense amplifier, 103 is the area of the (n-1)th column, and 104 is the area of the nth column. Also 31,
32, 41, and 42 are memory cells, 31 is the memory cell in the 2nd column, 1st row, 32 is the memory cell in the 2nd column, m-th row, 41 is the memory cell in the n-1 column, 1st row, 4
2 indicates a memory cell in the m-th row of the n-1 column. 33 and 43 are bit line loads, 33 is the bit line load of the second column, and 43 is the bit line load of the n-1 column n.

Two Y decoder system circuits and two column sense amplifiers are arranged in the areas indicated by 201 and 202, respectively, and each column's Y decoder system circuit +
The width of the column sense amplifiers 101, 102, 103, and 104 in the word line direction (horizontal direction in the figure) is secured for two columns. The lengths of the regions 201 and 202 in the bit line direction (vertical direction in the figure) are not limited by the memory cell size, and therefore the lengths of the regions 101, 102 and 103, 10
Each of the buffers 4 can be laid out relatively freely in the bit line direction and column direction (vertical and horizontal directions in the figure) within the regions 201 and 202. As a result, it is not only easier to create layout patterns, but also circuits that are difficult to fit into a narrow area, such as transistors with large gate widths and bipolar transistors that require a large area, can be laid out relatively freely. Become.

[0016] In the above-mentioned first embodiment, an example was shown in which the buffers 101 and 102 are arranged vertically in the figure in column units within an area of two columns, for example, 201, but the present invention is not limited to this. The buffers for each column may be mixed in any arrangement as long as they are within the area of two columns, and even in this case, the same effect as in the above embodiment can be achieved.

Furthermore, in the first embodiment, buffers for two columns are mixed within the area for two columns, but the present invention is not limited to the area for two columns, but can be applied to the area for multiple columns. A similar effect can be achieved even if buffers for multiple columns are mixed within.

Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG. In this example as well, consider the case where Y decoder circuits and column sense amplifiers for two columns are housed in an area having a width of two columns. In Figure 2,
The same symbols as in FIG. 1 indicate the same or equivalent parts, and each column's Y decoder system circuit + column sense amplifier 101, 102
, 103, 104 and each column's bit line load 13,
23, 33, and 43 are arranged alternately above and below each column,
Two columns constitute one set of repeating units. Even in this case, the area where the Y decoder system circuit + column sense amplifiers 101, 102, 103, and 104 of each column can be laid out can be secured up to the width of two columns as in the first embodiment. In this case, it goes without saying that address selection signal lines necessary for selecting each column must be arranged at both ends of the column.

In the above-mentioned second embodiment, one repeating unit is constituted by an area for two columns, but by using the structure in conjunction with the above-mentioned first embodiment, it is not limited to two columns, and even-numbered columns can be formed. It is clear that one repeating unit can be constructed in the region of minutes.

Note that the first and second embodiments above are examples applied to buffers located in the column direction.
The present invention may be applied to, for example, an X decoder circuit located in the row direction, and similar effects can be expected in this case as well.

[0021]

As described above, according to the present invention, in circuits arranged around the memory cell array, the width of the circuit area, which was limited by the memory cell size, can be reduced to multiple columns if the buffer is arranged in the column direction. Buffers arranged in the row direction can be expanded to the length of multiple rows, making pattern layout easier and complex circuits that were conventionally difficult to fit into a long and narrow area. For example, transistors with large gate widths, bipolar transistors, etc. can be arranged relatively freely, so that a high-performance semiconductor memory device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the arrangement of a static RAM memory cell array and its peripheral circuits in a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing the arrangement of a static RAM memory cell array and its peripheral circuits in a semiconductor memory device according to a second embodiment of the invention.

FIG. 3 is a block diagram of a read-related circuit around a bit line of a conventional static RAM.

FIG. 4 is a block diagram showing the arrangement of each buffer shown in FIG. 3;

FIG. 5 is a block diagram of a read circuit of a conventional static RAM using a column sense method.

FIG. 6 is a block diagram showing the arrangement of each buffer shown in FIG. 5;

[Explanation of symbols]

1 Memory cell 11 Memory cell 12 Memory cell 21 Memory cell 22 Memory cell 31 Memory cell 32 Memory cell 41 Memory cell 42 Memory cell 2 Bit line pair 3 Bit line load 13 Bit line load 23 Bit line load 33 Bit line load 43 Bit line load 4 word line 5 X decoder circuit 15 X decoder circuit 25 19 Column sense amplifier 14 Column sense amplifier 24 Column sense amplifier 101 Y decoder system circuit + column sense amplifier 10
2 Y decoder system circuit + column sense amplifier 103
Y decoder system circuit + column sense amplifier 104 Y
Decoder circuit + column sense amplifier 201 Area 202 where layout of Y decoder circuit + column sense amplifier is possible Area 202 where layout of Y decoder circuit + column sense amplifier is possible

Claims (2)

[Claims] 1. A circuit located at the periphery of a memory cell array, which is arranged in the row direction or column direction of the memory cell array, has a plurality of lengths in the bit line direction or word line direction of the circuit area. A semiconductor memory device characterized by being set to have a width of a row or multiple columns. 2. The circuits located in the periphery of the memory cell array, which are arranged in the row direction and the column direction of the memory cell array, have the length of the circuit area in the bit line direction. A semiconductor memory device characterized in that the semiconductor memory device is set to have a width of a plurality of rows, and a length in a word line direction is set to have a width of a plurality of columns.