JPH04219976A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a logic LSI whose delay time due to a load has been reduced without increasing a power consumption. CONSTITUTION:An LSI constituted by forming cells required to constitute a logic circuit is provided with elements whose loadto-delay time characteristic is different and which constitute a plurality of output circuits 4 (5), 14 (15) whose delay-time characteristics are crossed on a load-to-delay time characteristic diagram. It is constituted by selecting any of said plurality of output circuits 4 (5), 14 (15).

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit device (
The present invention relates to an LSI (hereinafter referred to as an LSI) that is constructed by providing cells in which elements necessary to construct a logic circuit, such as a gate array, are arranged.

0002

2. Description of the Related Art Conventionally, for example, FIG. Something like the one shown in the figure has been proposed. This ECL circuit is an example of a buffer, and in the figure, 1
is an input terminal to which the input signal SI is input, 2 is the reference voltage V
Reference voltage terminal to which REF is supplied, 3 is current switching circuit (CML circuit), 4 and 5 are output circuits, 6 and 7 are pull-down resistors, 8 and 9 are output terminals, 10 and 11 are output wiring An inverted output signal SOX and a non-inverted output signal SO are output to output terminals 8 and 9, respectively.

FIG. 6 is a diagram showing the load dependence of the delay time in the output circuits 4 and 5 of the conventional ECL circuit, that is, the load versus delay time characteristics. As is clear from this diagram, When the load increases, that is, the wiring 10, 1
1 has a problem in that the delay time increases when the wiring becomes long.

[0004] Also, an ECL circuit, the circuit diagram of which is shown in FIG. 7, has heretofore been proposed. In this ECL circuit, in addition to resistors 6 and 7, extra resistors 12 and 13 are provided as pull-down resistors, and these resistors 6, 7, and 1
2 and 13 are used as follows. For example, if the wiring 10 is a short wiring and does not require a large load driving capability, only the resistor 6 is used in the output circuit 4. On the other hand, the wiring 10 is a long wiring,
If large load driving capacity is required, resistors 6, 1
2 are connected in parallel to reduce the combined resistance. The same applies to the output circuit 5. Note that FIG. 7 shows a case where only the resistor 6 is used as a pull-down resistor in the output circuit 4, and two resistors 7 and 13 are connected in parallel in the output circuit 5.

As described above, according to the conventional ECL circuit shown in FIG. 7, when the load is large, the value of the pull-down resistor can be reduced to increase the load driving capability. Also, the delay time can be reduced. FIG. 8 is a diagram showing this, where the curve
curve Y is when the pull-down resistance is large (for example, when only resistor 6 is used as a pull-down resistor in output circuit 4), and curve Y is when pull-down resistance is small (for example, when two resistors 6 are used as pull-down resistors in output circuit 4)
12 are connected in parallel).

[0006]

[Problem to be solved by the invention] In this way, by reducing the pull-down resistance, even when the load is large,
Although the delay time can be reduced, there is a problem in that power consumption increases. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an LSI that can provide a logic LSI with reduced delay time due to load without increasing power consumption.

[0007]

[Means for Solving the Problems] The LSI according to the present invention has the following features:
In an LSI configured with cells in which elements necessary to configure a logic circuit are arranged, there are a plurality of LSIs with different load vs. delay time characteristics and whose delay time characteristic curves intersect on the load vs. delay time characteristic diagram. The device is configured by providing a cell that includes elements necessary to configure an output circuit, and allows selecting and configuring any one of the plurality of output circuits.

[0008]

[Operation] The present invention includes elements necessary to configure a plurality of output circuits that have different load vs. delay time characteristics and whose delay time characteristic curves intersect in the load vs. delay time characteristic diagram. It is possible to configure an output circuit with low power consumption and high load driving capability for a large load.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. Note that in FIG. 1, parts corresponding to those in FIG. 5 are given the same reference numerals. FIG. 1 shows a circuit example of a cell provided in this embodiment, in which output circuits 4, 5, 14,
15 are provided. Note that the output circuits 4 and 14 are output circuits for the inverted output signal SOX, and the output circuits 5 and 15 are output circuits for the inverted output signal SOX.
is an output circuit for the non-inverted output signal SO. Furthermore, the output circuits 14 and 15 have the same circuit configuration. Therefore, in this embodiment, depending on the size of the load, for example, as shown in FIG.
The ECL circuit is configured as shown in FIG.

In the output circuit 14, when the input signal SI is at a low level "L", the node 16 becomes a high level "H", and as a result, the inverted output signal SOX becomes a high level "H". . In this case, the node 17 becomes low level "L". After that, when the input signal SI is inverted to a high level "H", the node 16 becomes a low level "H".
As a result, the inverted output signal SOX is inverted to the low level "L". In this case, the node 17 is inverted from the low level "L" to the high level "H", and this level change It is differentiated by a differentiating circuit consisting of a capacitor 18 and a resistor 19, and this differentiated output (positive peak-shaped pulse) is supplied to the gate of the pull-down transistor 20. As a result, the O of the pull-down transistor 20
The N resistance suddenly decreases, and the charge accumulated in the parasitic capacitance of the load, that is, the wiring 10, is forcibly extracted. The load vs. delay time characteristic of the output circuit 14 is as shown by curve Z in FIG. The same applies to the output circuit 15. Note that the curve X shows the load versus delay time characteristics of the output circuits 4 and 5.

As described above, the output circuits 14 and 15 have a longer delay time than the output circuits 4 and 5 when the load is small, but when the load becomes large, the delay time becomes smaller than that of the output circuits 4 and 5. Moreover, these output circuits 14 and 15 are
Compared to the case where the pull-down resistors 6 and 7 in the output circuits 4 and 5 are made smaller to increase the load driving capability, power consumption can be reduced.

Therefore, in this embodiment, for example, when the wiring 10 is a short wiring, the output circuit 4 is used for the wiring 10, and when the wiring 10 is a long wiring, the output circuit 4 is used for the wiring 10. 10, the output circuit 14 is used. Similarly, when the wiring 11 is a short wiring, the output circuit 5 is used for the wiring 11, and when the wiring 11 is a long wiring, the output circuit 15 is used for the wiring 11. to use. In this case, a load versus delay time characteristic as shown by the solid line W in FIG. 4 can be obtained. Note that FIG. 2 shows an example in which the output circuit 14 is used for the wiring 10, and the output circuit 5 is used for the wiring 11.

As described above, according to this embodiment, it is possible to construct an ECL circuit having an output circuit with low power consumption and high load driving capability for a large load.

[0014]

As described above, according to the present invention, it is necessary to configure a plurality of output circuits that have different load vs. delay time characteristics and whose delay time characteristic curves intersect in the load vs. delay time characteristic diagram. Since it is equipped with a cell that can select and configure one of these multiple output circuits,
It is possible to configure an output circuit with low power consumption and large load driving capacity for a large load, and as a result, a logic LSI with reduced delay time due to the load without increasing power consumption can be obtained. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a cell provided in an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an ECL circuit configured by elements provided in the cell shown in FIG. 1;

FIG. 3 is a diagram showing load versus delay time characteristics of the output circuit shown in FIG. 1;

FIG. 4 is a diagram showing load vs. delay time characteristics obtained by selectively using the output circuits shown in FIG. 1;

FIG. 5 is a diagram showing an example of an ECL circuit configuring a logic LSI obtained using a conventional LSI configured by providing cells in which elements necessary for configuring the logic circuit are arranged.

FIG. 6 is a diagram showing load versus delay time characteristics of the output circuit forming the ECL circuit of FIG. 5;

FIG. 7 is a diagram showing another example of an ECL circuit configuring a logic LSI obtained using a conventional LSI configured by providing cells in which elements necessary for configuring a logic circuit are arranged.

8 is a diagram showing load versus delay time characteristics of an output circuit forming the ECL circuit of FIG. 7; FIG.

[Explanation of symbols]

3 Current switching circuit 4, 5, 14, 15 Output circuit

Claims (1)

[Claims] Claim 1: In a semiconductor integrated circuit device configured with cells in which elements necessary to configure a logic circuit are arranged, the load vs. delay time characteristics are different, and the delay A semiconductor comprising a cell that is equipped with elements necessary to configure a plurality of output circuits whose time characteristic curves intersect, and is configured to select and configure any one of the plurality of output circuits. Integrated circuit device.