JPH04222995A - Shift register circuit - Google Patents

Abstract

PURPOSE:To prevent the racing of the m-bit shift register, to restrain the increase in the number of gate and to prevent the skew of the clock line by connecting the n-bits half shift register which operates with an independent clock signal and the m-bit shift resister. CONSTITUTION:The 1-bit half flip-flop 1 as a first shift register outputs the data from an input terminal A shifting n-(n is a positive integer) bit half with the clock from an input terminal B. A flip-flop 2 as a second shift register outputs the data from the first shift register by shifting m-(m is a positive integer) bit with the clock of the output through a buffer 4 from the input terminal B.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit in a semiconductor integrated circuit.

0002

2. Description of the Related Art In a conventional shift register circuit, as shown in FIG. 4, an n-bit shift register circuit 1a and an m-bit shift register circuit 2, each operated by an independent clock, are connected, and s-bit (s=n+m) shift is performed. When the register circuit 3a is configured, if the delay time of the buffer 4a is larger than the delay time of the n-bit shift register circuit 1a due to the influence of wiring length and fan-out, racing may occur in the m-bit shift register circuit 2 and malfunction may occur. There was sex. Therefore, as shown in FIG. 5, a flip-flop (D-F/F) 5 and an inverter circuit 6 are added to the circuit of FIG. 4 to create a circuit configuration that prevents reliable racing in the m-bit shift register circuit 2.

0003

[Problems to be Solved by the Invention] In the conventional shift register circuit described above, in order to prevent racing in the m-bit shift register circuit 2, as shown in FIG.
If the circuit structure is made with the addition of the inverter circuit 6,
Compared to the circuit configuration in Figure 4, the number of gates is approximately (1/s) x 10
0%, and the clock line load also increases, which has the disadvantage that skew is likely to occur in the clock line.

0004

[Means for Solving the Problems] The shift register circuit of the present invention includes a first shift register that outputs data half-shifted by n bits (n is a positive integer) by a clock, and The data from the first shift register is transferred m (m is a positive integer) by a clock.
and a second shift register for bit shifting and outputting.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 shows one embodiment of the present invention, which is an s-bit shift register that is a combination of an n-bit half shift register and an m-bit shift register. In order to facilitate the explanation of this embodiment, it will be explained using FIGS. 2 and 3.

FIG. 2 is a circuit diagram of a 2-bit shift register showing an embodiment of the shift register circuit according to the present invention.

Input terminal A is a data input terminal, and input terminal B is a clock input terminal. Connect input terminal A and the data input of 1-bit half flip-flop (hereinafter referred to as D-F/F) 1, and connect the Q output flip-flop of D-F/F1 (
Connect the data input of D-F/F)2 and connect the input terminals B and D.
- Connect the clock input of F/F1 and the input of buffer 4, connect the output of buffer 4 and the clock input of DF/F2, and connect the Q output of DF/F2 to output terminal C. .

FIG. 3 is an explanatory diagram of waveforms in the circuit of FIG. 2, and input signals (A) and (B) are connected to input terminals A and B of FIG.
, the signal (2) corresponds to the Qh output, and the output signal (C) corresponds to the output of FIG.

When the 0 of the input signal (B) becomes 1, D-F/
F1 latches data “D0” of input signal (A),
When the 1 of the input signal (B) becomes 0 after half a bit, the signal (
As shown in 2), data "D0" is output from DF/F1. Next, when the 0 of the input signal (B) becomes 1 after half a bit, the data "D0" is latched by the D-F/F2, and the data "D0" is output from the output terminal C as shown in the output signal (C). . Therefore, since the change point of the data input of DF/F2 has a phase difference of half a bit with respect to the rising edge of the clock, even if the delay time of buffer 4 is larger than the delay time of DF/F1, D-F/F2 /I will never race in F2.

In this way, when configuring the s-bit shift register 3 as shown in FIG. 1, by connecting the m-bit register 2 to the n-bit half shift register 1 (s=n+m), the subsequent m-bit shift register In addition to preventing racing, the increase in the number of gates is approximately (1/2 s) ×
The number of gates can be reduced by approximately (1/2 s) x 100% compared to the conventional circuit configuration for preventing racing as shown in FIG. Furthermore, compared to the conventional anti-racing circuit configuration as shown in FIG. 5, there is no need to increase the load on the clock line, so skew in the clock line is less likely to occur.

[0011]

Effects of the Invention As explained above, the present invention provides a semiconductor integrated circuit that operates with independent clock signals.
By connecting the half-bit shift register and the m-bit shift register, it is possible to prevent racing of the m-bit shift register and to reduce the increase in the number of gates. Further, since the load on the clock line does not have to increase, there is an effect that skew of the clock line is less likely to occur.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram for explaining this embodiment.

FIG. 3 is a waveform diagram for explaining the operation of this embodiment.

FIG. 4 is a block diagram of an example of a conventional shift register circuit.

FIG. 5 is a block diagram for explaining a conventional example.

[Explanation of symbols]

1 n-bit half shift register (D-F/F1)
2 m-bit shift register (D-F/F2) 3
s-bit shift register 4 buffer

Claims (1)

[Claims] 1. A first shift register that outputs data shifted by half by n bits (n is a positive integer) by a clock; and a first shift register that outputs data shifted by half by n (n is a positive integer) bits by a clock; and a second shift register that shifts and outputs m (m is a positive integer) bits.