JPH04224256A - Data signal processing system - Google Patents

Abstract

PURPOSE:To obtain a signal processing system by which a data signal given from a signal sensor becomes the reference base of each controller as the common regular data. CONSTITUTION:A data signal of one sensor 3 is inputted to a front controller 1. A data signal 6 outputted from the sensor 3 is inputted to the rear controller 2 after finishing a specified initialization, and it becomes reference data of the controller 2. A time in which the initialization of the front controller 1 finishes is preliminarily determined, and the input of the data signal 9 is carried out by the rear controller 2 provided that the abovementioned time of initialization passed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal processing system, and more particularly to a data signal processing system for an on-vehicle electronic control device equipped with a plurality of controllers that output a predetermined control signal based on a single data signal. .

0002

2. Description of the Related Art In general, in in-vehicle electronic control devices, systems are known in which each controller controls a corresponding drive device, etc., based on output data of a sensor at a specific part when performing a predetermined operation of each part of the device. ing.

For example, as shown in FIG. 9, there is an engine (fuel injection) controller 1 in the front stage and a
In combination with the T mission controller 2, the signal from the single sensor 3 that detects the throttle opening is taken into the CPU 5 of the engine controller 1, and this CPU
5 is input to the CPU 6 of the AT mission controller 2, and the AT mission controller 2 controls the AT shift valve 7 based on this. The reason why the signal from the sensor 3 is input to the AT mission controller 2 via the engine controller 1 is that the control of the AT mission controller 2 is associated with the engine state, and the signals from the sensor 3 are input to the AT mission controller 2 via the engine controller 1. 1,2
This is due to the fact that it is uneconomical to provide individual sensors for each.

0004

However, the above-mentioned conventional structure causes the following disadvantages.

That is, in the case of the system having the above configuration, generally when the ignition switch 8 is turned on and each controller starts operating, each controller 1, 2
When the power supply circuits 10 and 11 are turned on, initialization signals S1 and S2 are given to each CPU 5 and 6, thereby initializing (resetting) the CPUs 5 and 6, and then starting the corresponding subsequent control. Yes, and the time required for the initialization is not the same depending on the controller, so if the time required for initialization is longer for engine controller 1 than for AT mission controller 2, engine controller 1 will start control and initialize. The AT mission controller starts control before outputting the data signal θ of the subsequent throttle opening. Therefore, the data signal of the throttle opening degree given to the AT mission controller is not a correct value, and the AT mission controller 2 that receives this data signal causes a problem that accurate control cannot be performed thereafter. This is because the data signal of the throttle opening that is first taken in by the AT mission controller 2 is used as an initial value and as base data for subsequent control.

[0006]

OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a data signal of the sensor output from the previous controller when the detection signal of a single sensor is used as the base data of the subsequent controller via the previous controller. An object of the present invention is to provide a data signal processing system in which only correct values after initialization can be taken in by a subsequent controller, and subsequent control of the subsequent controller can be performed based on this value.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the data signal processing system according to the present invention inputs one data signal to a previous stage controller, and then inputs the data signal given from the previous stage controller. In a system that includes a subsequent controller that outputs a predetermined control signal based on a signal, and is configured such that each controller is initialized when the power is turned on, the subsequent controller completes initialization from the preceding controller. After a signal is input or the required initialization time set in advance has elapsed,
It is configured to be able to take in the data signal given from the previous stage controller.

[0008]

[Operation] After the data signal is taken into the preceding controller, the subsequent controller does not take in the data signal until the initialization of the preceding controller is completed or the initialization time has elapsed. Import is permitted subject to completion of conversion, etc. Therefore, the subsequent controller can use the correct value as base data for subsequent control, and accurately control a predetermined drive device or the like in a predetermined correspondence with the preceding controller.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

A first embodiment is shown in FIGS. 1 and 2. Although FIG. 1 mainly shows the front-stage controller 1 and the rear-stage controller 2, the system as a whole is substantially the same as that of FIG. 9 described above. Therefore, in the following description of the embodiment, the same reference numerals will be used for the same components as in FIG.

The pre-stage controller 1 constitutes, for example, an engine controller, and is configured such that a reset signal S1 is given to the CPU 5 from the power supply circuit 10 when the ignition switch 8 is turned on. The CPU 5 inputs the data signal from the throttle opening sensor 3 and converts it into an encoded data signal θ.
The controller 2 is configured to output the signal to a subsequent controller 2 such as an AT mission controller. On this occasion,
The CPU 5 is configured to output a status signal ST as an initialization completion signal to the subsequent controller 2 when the CPU 5 is initialized in response to the reset signal S1.

On the other hand, like the controller 1 in the previous stage, the controller 2 in the latter stage is configured such that the CPU 6 is initialized in response to the reset signal S2 from the power supply 11.
6 is configured to take in the data signal θ on condition that the status signal ST given from the CPU 5 of the controller 1 at the previous stage is input. That is, as shown in FIG. 2, the CPU 6 outputs the status signal ST after completion of initialization.
The presence or absence of the input of the status signal ST is first checked, and when the status signal ST is input, the data signal θ is taken in, and subsequent predetermined control signals are output based on this.

Therefore, according to this embodiment, the data signal of the sensor 3 given by the CPU 5 of the controller 1 at the previous stage cannot be taken into the CPU 6 of the controller 2 at the rear stage until the CPU 5 is initialized. Therefore, by always taking in only the regular data after initialization, the subsequent controller 2 is able to output subsequent control signals. The effect is that reliability can be expected even if there is a problem.

Next, a second embodiment will be explained based on FIGS. 3 and 4.

The feature of this second embodiment is that instead of the status signal ST, a predetermined delay circuit 13 is provided in the controller 2 at the subsequent stage, and the initialization signal S2 given to the CPU 6 from this delay circuit 13 is It's about delaying it.

That is, as is clear from FIG. 4, the rise time of the initialization signal S2 is delayed in accordance with the preset required initialization time of the CPU 5 in the preceding controller 1, and thereby the CPU 6 is initialized. When the controller 1 is converted into a controller, the data signal θ from the controller 1 at the previous stage can be taken in. In addition, delay circuit 1
3 can also be provided in the controller 1 at the previous stage.

Therefore, according to the second embodiment,
As a result of being able to avoid that the CPU 6 in the subsequent controller 2 is initialized before the CPU 5 of the preceding controller 1, the subsequent controller 2 can always perform predetermined control based on the regular data signal θ after initialization. I can do it. Other structures and functions are the same as those of the first embodiment.

Next, a third embodiment will be explained based on FIGS. 5 to 7. Here, FIG. 5 shows an operation flowchart of the CPU 5 in the first-stage controller 1, and FIG. 6 shows an operation flowchart of the CPU6 in the second-stage controller 2. Further, FIG. 7 is a timing chart for each signal.

As shown in FIG. 5, after being initialized (reset) in response to the initialization signal S1, the CPU 5 transmits a reset completion signal θ1 as an initialization completion signal to the subsequent controller 2, and then The data signal θ of the sensor 3 is transmitted in the same manner. Here, the above operation is performed regardless of whether initialization of the subsequent CPU 6 is completed or not.

On the other hand, as shown in FIG. 6, after being reset, the CPU 6 looks at the signal θ1 sent from the CPU 5 on the previous stage and determines whether it is a reset completion signal or not.
When it is determined that this is the reset completion signal, the CP
The data signal θ from U5 will be taken in.

[0021] This embodiment can also provide substantially the same effects as the above embodiment.

Next, a fourth embodiment will be explained based on FIG. 8. FIG. 8 shows an operation flowchart of the CPU 6 in the subsequent controller 2. After the CPU 6 is reset, time is counted and compared with a delay time D preset as the required initialization time of the CPU 5 in the preceding controller 1. It is provided. Then, when the time is longer than D, the data signal θ from the controller 1 at the previous stage is taken in.

[0023] Therefore, even with such a configuration, the same effects as in the above embodiment can be obtained.

[0024] In carrying out the present invention, the number of controllers may be two or more, and in short, the present invention can be widely applied to cases where the control conditions, etc. have a certain relationship between the controllers. The controller is not limited to an engine controller, an AT mission controller, or the like.

[0025]

[Effects of the Invention] As explained above, according to the present invention,
In a control system in which the detection signal of a single sensor is passed through a previous-stage controller and used as base data for a subsequent-stage controller, it is possible to ensure that only regular data is taken in as the sensor data provided by the previous-stage controller. This has the advantage that it is possible to avoid the inconvenience of a subsequent controller performing subsequent control based on irregular data.

Therefore, for example, if the controller 1 at the front stage is an engine controller and the controller 2 at the rear stage is an AT mission controller, the control of the AT mission controller can always be performed in a predetermined correspondence with the engine state. Therefore, it is expected that this will greatly contribute to the stable control of both.

Moreover, by making the above-mentioned control possible, the need to provide two sensors 3 independently is eliminated, which not only contributes to economic efficiency, but also reduces the number of sensors and reduces the relative cost. This has the effect of suppressing the incidence of failures, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a main part of a first embodiment of a data signal processing system according to the present invention.

FIG. 2 is a flowchart of the CPU 6 on the downstream side in the first embodiment.

FIG. 3 is a diagram similar to FIG. 1 showing a second embodiment.

FIG. 4 is a timing chart of output signals in a second embodiment.

FIG. 5 is a flowchart for explaining the operation of the CPU on the front stage in the third embodiment.

FIG. 6 is a flowchart diagram for explaining the operation of a CPU on the latter stage in the third embodiment.

FIG. 7 is a timing chart diagram of output signals in a third embodiment.

FIG. 8 is a flowchart diagram for explaining the operation of a CPU on the latter stage in the fourth embodiment.

FIG. 9 is a block diagram showing a conventional example.

[Explanation of symbols]

1 Pre-stage controller 2 Post-stage controller 3 Sensor 5 CPU 6 CPU S1 Initialization signal S2 Initialization signal θ Data signal θ1 Reset signal ST as initialization completion signal
Status signal 13 as initialization completion signal Delay circuit

Claims (1)

[Claims] 1. A second-stage controller that outputs a predetermined control signal based on the data signal given from the first-stage controller after inputting one data signal to the first-stage controller; In the system configured to initialize, the subsequent controller receives the data given from the preceding controller upon input of an initialization completion signal from the preceding controller or after a preset required initialization time has elapsed. A data signal processing system characterized by being configured to be able to take in signals.