JPH04225542A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04225542A
JPH04225542A JP2408071A JP40807190A JPH04225542A JP H04225542 A JPH04225542 A JP H04225542A JP 2408071 A JP2408071 A JP 2408071A JP 40807190 A JP40807190 A JP 40807190A JP H04225542 A JPH04225542 A JP H04225542A
Authority
JP
Japan
Prior art keywords
bumps
metal
bump
metal bumps
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2408071A
Other languages
Japanese (ja)
Inventor
Kazumitsu Itabashi
一光 板橋
Hiroyuki Shigyo
裕之 執行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Original Assignee
Tanaka Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Denshi Kogyo KK filed Critical Tanaka Denshi Kogyo KK
Priority to JP2408071A priority Critical patent/JPH04225542A/en
Publication of JPH04225542A publication Critical patent/JPH04225542A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07231Techniques
    • H10W72/07236Soldering or alloying
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To make easy a fixing workability in a semiconductor device by a method wherein a metallic bump is respectively provided on the semiconductor chip side and the substrate lead side, both metallic bumps are connected by a heat-compressing or by a melt-compressing in a condition that only one bump is melted, and also both the metallic bumps differ in sort and shape. CONSTITUTION:Metallic bumps 5, 6 are respectively formed on a wire 2 of a chip 1 and a lead 4 of a substrate 3, both bumps are connected by a thermo- compression bonding method or a fusion bonding method in a condition that only one metallic bump is melted. The metallic bumps 5, 6 are made of different materials selected from Au, Pd, Pt, Ni, Cu, or their alloys, Pb-Sn, Pb-In, Sn-In or the like, and differ in size and shape.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体装置、詳しくは半
導体チップをワイヤレスボンディング法、特にフリップ
チップボンディング法又はテープキャリアボンディング
法により装着される半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor chip is attached by a wireless bonding method, particularly a flip chip bonding method or a tape carrier bonding method.

【0002】0002

【従来技術とその課題】従来、半田バンプを介して装着
した半導体装置は図8に示す如く、半導体チップ1′の
配線2′又は基板3′のリード4′の何れか一方に半田
バンプ6′を設け、該バンプ6′に他方を熱圧着法又は
リフロー法によって接合し実装するものである。
[Prior Art and Problems] Conventionally, as shown in FIG. 8, a semiconductor device mounted via solder bumps has solder bumps 6' attached to either wiring 2' of a semiconductor chip 1' or leads 4' of a substrate 3'. is provided, and the other is bonded to the bump 6' by a thermocompression method or a reflow method for mounting.

【0003】しかるに、最近は半導体装置に不良が発生
した場合、半導体チップ1′をいったん基板3′から剥
離し、不良部を修正した後に再度チップ1′を装着する
修復作業を要求されるが、前記従来構造においてはチッ
プ1′を剥離する際、バンプ6′の熱疲労破壊による割
れ10′は基板3′側又はチップ1′側に生じるなど一
定せず、再装着時におけるバンプ形成等に手数を要し、
あるいは再装着不能になる等の不具合がある。
However, recently, when a defect occurs in a semiconductor device, repair work is required in which the semiconductor chip 1' is once removed from the substrate 3', the defective part is repaired, and the chip 1' is reattached. In the conventional structure, when the chip 1' is peeled off, the cracks 10' due to thermal fatigue fracture of the bumps 6' occur inconsistently on the substrate 3' side or the chip 1' side, making it troublesome to form bumps when reattaching them. It takes
Or, there is a problem such as not being able to reattach it.

【0004】本発明は斯る従来不具合を解消して半導体
装置の修復作業性を容易ならしめる半導体装置を提供せ
んとすることを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which eliminates such conventional problems and facilitates repair work of the semiconductor device.

【0005】[0005]

【課題を解決するための手段】斯る本発明の半導体装置
は、半導体チップ側と基板リード側とにそれぞれ金属バ
ンプを設け、両金属バンプを熱圧着により接合又は一方
の金属バンプのみ溶かした状態で融着接合せしめるとと
もに、前記両金属バンプが異種又は異形であることを特
徴とする。
[Means for Solving the Problems] In the semiconductor device of the present invention, metal bumps are provided on the semiconductor chip side and the substrate lead side, and both metal bumps are bonded by thermocompression bonding, or only one metal bump is melted. The metal bumps are of different types or have different shapes.

【0006】上記両金属バンプの接合手段としてリフロ
ー法によれば、両バンプが溶融一体化して本発明の作用
効果が得られないので、前述の通り熱圧着法又は一方の
金属バンプのみ溶かした状態での遊着接合法によるもの
である。
If the reflow method is used as a means for joining the two metal bumps, both bumps will melt and become integrated, and the effects of the present invention cannot be obtained. This is based on the free bonding method.

【0007】金属バンプを異種とする態様には次の2つ
がある。すなわち、その一態様は金属バンプの一方を高
融点金属、例えばAu ,Pd ,Pt ,Ni ,C
u あるいはそれらの合金等とし、他方を低融点金属、
例えばPb ,Sn ,In あるいはPb−Sn ,
Pb−In ,Sn−In などの合金等とする。
[0007] There are two ways to use different types of metal bumps. That is, in one embodiment, one of the metal bumps is made of a high melting point metal, such as Au, Pd, Pt, Ni, C.
u or an alloy thereof, and the other is a low melting point metal,
For example, Pb, Sn, In or Pb-Sn,
An alloy such as Pb-In or Sn-In is used.

【0008】又、他の態様は前記低融点金属同志あるい
は高融点金属同志をそれぞれの金属バンプとし、かつそ
れら低融点金属又は高融点金属中の異なる金属の組合せ
とし、その中にはPb−Sn ,Pb−In 合金のS
n ,In の濃度を変えた組合せも含むものである。
[0008] In another embodiment, the low melting point metals or the high melting point metals are used as metal bumps, and different metals among the low melting point metals or high melting point metals are combined, including Pb-Sn. , S of Pb-In alloy
This also includes combinations in which the concentrations of n and In are changed.

【0009】この後者態様においては、低融点金属同志
又は高融点金属同志から硬さ及び融点の異なる組合せと
することが望ましい。
In this latter aspect, it is desirable to use a combination of low melting point metals or high melting point metals having different hardness and melting point.

【0010】上記金属バンプを異形とする態様としては
両金属バンプを大小異なる形状、すなわち一方を他方よ
り小さなバンプ形状とする。この金属バンプの異形態様
においては、前記バンプの異種態様との組合せによる複
数の態様のあることはもちろんであるが、両金属バンプ
の種類を同一金属とし、それらを相互に大小異なる形状
とする態様とすることもよい。
[0010] As an embodiment of making the metal bumps irregularly shaped, both metal bumps are made to have different sizes, that is, one bump shape is smaller than the other. Of course, in this variant form of the metal bump, there are a plurality of forms in combination with the different types of bumps, but there is also a form in which both metal bumps are made of the same metal and have shapes that are different in size from each other. It is also good to do this.

【0011】[0011]

【作用】本発明によれば、半導体チップ側と基板リード
側とに設けた異種又は異形の2つの金属バンプを熱圧着
により接合又は一方の金属バンプのみ溶かした状態で融
着接合せしめたので、チップを剥離する際の破壊は常に
両金属バンプの接合界面近傍で起る。
[Operation] According to the present invention, two metal bumps of different types or irregular shapes provided on the semiconductor chip side and the substrate lead side are joined by thermocompression bonding or by fusion bonding with only one metal bump melted. Breakage during chip peeling always occurs near the bonding interface between both metal bumps.

【0012】従って、チップを再装着する際には、新た
に形成した一方の金属バンプが前記他方の金属バンプの
破壊面を埋める状態で接合させ得る。
[0012] Therefore, when the chip is reattached, the newly formed metal bump can be bonded to fill the broken surface of the other metal bump.

【0013】[0013]

【実施例】本発明の実施例を図面により説明すれば、図
1及び図2は本発明の原理、作用を説明するものであり
、図において、1は半導体チップ、2は該チップ1に形
成されたAl などの配線、3は基板、4は該基板3に
形成されたCu ,Al ,Ni などのリードである
。上記配線2及びリード4はチップ1及び基板3上に対
応して多数配設されるが、説明の便宜のため、対応する
一対のみを示す。
[Embodiment] An embodiment of the present invention will be described with reference to the drawings. FIGS. 1 and 2 explain the principle and operation of the present invention. 3 is a substrate, and 4 is a lead made of Cu, Al, Ni, etc. formed on the substrate 3. A large number of the wirings 2 and leads 4 are provided on the chip 1 and the substrate 3, but for convenience of explanation, only one corresponding pair is shown.

【0014】チップ1の配線2上及び基板3のリード4
上には、それぞれに金属バンプ5,6をワイヤボンディ
ング法など任意の方法によって形成し(図1(A))、
両金属バンプ5,6を熱圧着法又は一方の金属バンプの
み溶かした状態での融着接合法により接合せしめる(図
1(B))。
On the wiring 2 of the chip 1 and on the leads 4 of the substrate 3
On the top, metal bumps 5 and 6 are formed by an arbitrary method such as a wire bonding method (FIG. 1(A)),
Both metal bumps 5 and 6 are joined by thermocompression bonding or fusion bonding with only one metal bump melted (FIG. 1(B)).

【0015】金属バンプ5,6は、Au ,Pd ,P
t ,Ni ,Cu あるいはそれらの合金、Pb ,
Sn ,In あるいはそれらの合金であるPb−Sn
 ,Pb−In ,Sn−In 等から選んだ異種又は
同種である。
The metal bumps 5 and 6 are made of Au, Pd, P
t, Ni, Cu or their alloys, Pb,
Sn, In or their alloy Pb-Sn
, Pb-In, Sn-In, and the like.

【0016】上記半導体装置を修復する場合、チップ1
を基板3から剥離する際に、接合する金属バンプ5,6
間では両者の接合界面又はその近傍で割れ10が生じる
ことになり(図2(A))、その後にチップ1に新たな
金属バンプ5′を形成して(図2(B))、基板3上に
熱圧着又は一方の金属バンプのみ溶かした状態で融着接
合すると前記バンプ5′が金属バンプ6の割れ10を埋
める状態で両バンプ5′,6が接合する。
When repairing the above semiconductor device, the chip 1
The metal bumps 5 and 6 to be bonded when peeling off from the substrate 3
A crack 10 occurs at or near the bonding interface between the two (FIG. 2(A)), and then new metal bumps 5' are formed on the chip 1 (FIG. 2(B)), and the substrate 3 By thermocompression bonding or fusion bonding with only one of the metal bumps melted, both bumps 5' and 6 are bonded with the bump 5' filling the crack 10 in the metal bump 6.

【0017】上記接合は、レーザービーム加熱等の局所
加熱法により大気中好ましくはN2 ガス等の不活性ガ
ス中で可能である。
The above bonding can be performed in the atmosphere, preferably in an inert gas such as N2 gas, by a local heating method such as laser beam heating.

【0018】図3〜図6は金属バンプ5,6の組合せを
例示するものであり、図3は高融点金属、すなわちAu
 ,Pd ,Pt ,Ni あるいはそれらの合金と、
低融点金属、すなわちPb ,Sn ,In あるいは
それらの合金Pb−Sn ,Pb−In ,Sn−In
 等との組合せを示す。そして図3(A)は一例として
金属バンプ5にAu を、バンプ6にSn を用いた同
一形状の態様を示し、図3(B)は金属バンプ5を金属
バンプ6より小さくした大小異形の態様である。
3 to 6 illustrate combinations of metal bumps 5 and 6, and FIG. 3 shows a combination of metal bumps 5 and 6, and FIG.
, Pd, Pt, Ni or an alloy thereof,
Low melting point metals, namely Pb, Sn, In or their alloys Pb-Sn, Pb-In, Sn-In
This shows the combination with etc. FIG. 3(A) shows, as an example, an embodiment of the same shape in which the metal bumps 5 are made of Au and the bumps 6 are made of Sn, and FIG. 3(B) shows an embodiment of a different size in which the metal bumps 5 are smaller than the metal bumps 6. It is.

【0019】図4は金属バンプ5,6を前記低融点金属
同志の異種とした組合せであって、その図4(A)は一
例として金属バンプ5にSn を、バンプ6にPb−S
n を用いた同一形状の態様を示し、図4(B)はその
大小異形の態様を示す。
FIG. 4 shows a combination of metal bumps 5 and 6 made of different types of low melting point metals, and FIG. 4A shows an example in which the metal bumps 5 and 6 are made of Sn and the bump 6 is made of Pb-S.
FIG. 4(B) shows an aspect of the same shape using n, and FIG. 4(B) shows an aspect of the irregular shape.

【0020】図5は金属バンプ5,6を前記高融点金属
同志の異種とした組合せであって、その図5(A)は一
例として金属バンプ5にAu を、バンプ6にPd を
用いた同一形状の態様を示し、図5(B)はその大小異
形の態様を示す。
FIG. 5 shows a combination of metal bumps 5 and 6 made of different types of high melting point metals, and FIG. The shape is shown, and FIG. 5(B) shows the size and size of the irregular shape.

【0021】図6は金属バンプ5,6を前記低融点金属
同志の同種又は高融点金属同志の同種とし、かつ大小異
形とした態様を示す。
FIG. 6 shows an embodiment in which the metal bumps 5 and 6 are made of the same kind of low melting point metals or the same kind of high melting point metals, and have different sizes.

【0022】図6(A)は一例として金属バンプ5,6
にそれぞれPb−Sn を用いた場合であり、図6(B
)は金属バンプ5,6にそれぞれAu を用いた場合で
ある。
FIG. 6(A) shows metal bumps 5 and 6 as an example.
Figure 6 (B
) is the case where Au is used for each of the metal bumps 5 and 6.

【0023】尚、上記実施例図3〜図6においては低融
点金属、高融点金属の中から1つを例示したが、他の金
属バンプの組合せを選定することも自由であり、また金
属バンプ5と6との金属を逆にすることも任意である。
In the embodiments shown in FIGS. 3 to 6, one of a low melting point metal and a high melting point metal is shown as an example, but other combinations of metal bumps may be freely selected. It is also optional to reverse the metals of 5 and 6.

【0024】又、実施例図4及び図5の如く、低融点金
属同志又は高融点金属同志の中から異種を選ぶ場合には
、その一方を他方より融点が高い金属又は硬い金属を選
定することが好ましく、さらに図6の実施例においては
チップ1を剥離する際に金属バンプ5,6がその略接合
界面で破壊し離反する。
Furthermore, as shown in FIGS. 4 and 5, when selecting different types of metals from low-melting point metals or high-melting point metals, one should be selected to have a higher melting point or a harder metal than the other. Further, in the embodiment shown in FIG. 6, when the chip 1 is peeled off, the metal bumps 5 and 6 are broken and separated approximately at the bonding interface.

【0025】図7は前示実施例図3(B)の場合におけ
る他の作用例を説明するものである。  同図において
チップ1を基板3から剥離する際に、金属バンプ5の配
線2側又はバンプ5と配線2との接合界面で破壊を生じ
て、金属バンプ5の一部又は全部が金属バンプ6上に残
る場合もある(図7(B))。その場合でも、チップ1
に新たな金属バンプ5′を形成して(図7(C))、基
板3上に熱圧着すると前記バンプ5′がバンプ6上のバ
ンプ5をバンプ6内に押込んでそれらバンプ5,5′,
6が接合一体的となる。
FIG. 7 illustrates another example of the operation in the case of the previous embodiment shown in FIG. 3(B). In the figure, when the chip 1 is peeled off from the substrate 3, destruction occurs at the wiring 2 side of the metal bump 5 or at the bonding interface between the bump 5 and the wiring 2, and part or all of the metal bump 5 is removed from the metal bump 6. (Figure 7(B)). Even in that case, chip 1
When a new metal bump 5' is formed (FIG. 7(C)) and thermocompression bonded onto the substrate 3, the bump 5' pushes the bump 5 on the bump 6 into the bump 6, and the bumps 5, 5' ,
6 becomes integrally joined.

【0026】[0026]

【効果】本発明によれば、半導体装置を修復するために
チップを剥離する際の破壊が常に両金属バンプの接合界
面近傍で起るので、一方の金属バンプはそのバンプ形状
をほぼ保持した状態で残り、再装着の際に新たに形成し
たバンプと熱圧着により接合又は一方の金属バンプのみ
溶かした状態で融着接合して導通をとることができる。 従って、修復可能な半導体装置を提供し所期の目的を達
成し得る。
[Effect] According to the present invention, when a chip is peeled off to repair a semiconductor device, destruction always occurs near the bonding interface between both metal bumps, so one metal bump maintains almost its bump shape. When reinstalling, it can be bonded to the newly formed bump by thermocompression bonding, or it can be fused and bonded with only one metal bump melted to establish electrical continuity. Therefore, it is possible to provide a repairable semiconductor device and achieve the intended purpose.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明半導体装置の接合を示す部分拡大正面図
FIG. 1 is a partially enlarged front view showing bonding of a semiconductor device of the present invention.

【図2】本発明の修復作用を説明する同正面図。FIG. 2 is a front view illustrating the repair action of the present invention.

【図3】金属バンプの態様を示す同正面図。FIG. 3 is a front view showing an aspect of a metal bump.

【図4】金属バンプの他の態様を示す同正面図。FIG. 4 is a front view showing another aspect of the metal bump.

【図5】金属バンプのさらに他の態様を示す同正面図。FIG. 5 is a front view showing still another aspect of the metal bump.

【図6】金属バンプのさらに他の態様を示す同正面図。FIG. 6 is a front view showing still another aspect of the metal bump.

【図7】本発明の修復における他の作用を示す同正面図
FIG. 7 is a front view showing another action in the repair of the present invention.

【図8】従来例を示す同正面図。FIG. 8 is a front view showing a conventional example.

【符号の説明】[Explanation of symbols]

1    半導体チップ              
  2 配  線3    基  板        
            4    リード5,5′,
6    金属バンプ
1 Semiconductor chip
2 Wiring 3 Board
4 Lead 5, 5',
6 Metal bump

Claims

【特許請求の範囲】 【請求項1】    半導体チップ側と基板リード側と
にそれぞれ金属バンプを設け、両金属バンプを熱圧着に
より接合又は一方の金属バンプのみ溶かした状態で融着
接合せしめるとともに、前記両金属バンプが異種又は異
形である半導体装置。
   【請求項2】    前記金属バンプの一方が高融点の
金属バンプであり、他方が低融点の金属バンプである請
求項1記載の半導体装置。
【請求項3】    前記金属バンプが低融点同志であ
り、かつ相互に異なる金属バンプである請求項1記載の
半導体装置。
【請求項4】    前記金属バンプが高融点同志であ
り、かつ相互に異なる金属バンプである請求項1記載の
半導体装置。
【請求項5】    前記金属バンプが大小異なる形状
である請求項2〜4の何れか1項記載の半導体装置。
【請求項6】    前記両金属バンプが同種であり、
かつ相互に大小異なる形状である請求項1記載の半導体
装置。
[Claims] 1. Metal bumps are provided on the semiconductor chip side and the substrate lead side, respectively, and both metal bumps are bonded by thermocompression bonding or fusion bonded with only one metal bump melted, and both metal bumps are of different types. or semiconductor devices that are irregularly shaped. 2. The semiconductor device according to claim 1, wherein one of the metal bumps is a high melting point metal bump and the other is a low melting point metal bump. 3. The semiconductor device according to claim 1, wherein the metal bumps have low melting points and are different from each other. 4. The semiconductor device according to claim 1, wherein the metal bumps have high melting points and are different from each other. 5. The semiconductor device according to claim 2, wherein the metal bumps have shapes of different sizes. 6. Both the metal bumps are of the same type,
2. The semiconductor device according to claim 1, wherein the semiconductor device has shapes that are different in size from each other.
JP2408071A 1990-12-27 1990-12-27 Semiconductor device Pending JPH04225542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2408071A JPH04225542A (en) 1990-12-27 1990-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2408071A JPH04225542A (en) 1990-12-27 1990-12-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04225542A true JPH04225542A (en) 1992-08-14

Family

ID=18517572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2408071A Pending JPH04225542A (en) 1990-12-27 1990-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04225542A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477086A (en) * 1993-04-30 1995-12-19 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
JPH0878474A (en) * 1994-08-31 1996-03-22 Nec Corp Board connection structure and connection method thereof
JPH08148495A (en) * 1994-11-25 1996-06-07 Fujitsu Ltd Semiconductor device, manufacturing method thereof, and bump adhesion evaluation method in semiconductor device
JPH08213425A (en) * 1995-02-03 1996-08-20 Matsushita Electron Corp Semiconductor device and manufacturing method thereof
US5708283A (en) * 1994-10-20 1998-01-13 Hughes Aircraft Flip chip high power monolithic integrated circuit thermal bumps
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US6436730B1 (en) * 1993-10-04 2002-08-20 Motorola, Inc. Microelectronic package comprising tin copper solder bump interconnections and method for forming same
US6583514B2 (en) 2000-10-04 2003-06-24 Nec Corporation Semiconductor device with a binary alloy bonding layer
JP2005311188A (en) * 2004-04-23 2005-11-04 Fuchigami Micro:Kk Multilayer wiring board
JP5817893B1 (en) * 2014-07-14 2015-11-18 大日本印刷株式会社 Component mounting wiring board and manufacturing method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477086A (en) * 1993-04-30 1995-12-19 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
US6436730B1 (en) * 1993-10-04 2002-08-20 Motorola, Inc. Microelectronic package comprising tin copper solder bump interconnections and method for forming same
JPH0878474A (en) * 1994-08-31 1996-03-22 Nec Corp Board connection structure and connection method thereof
US5708283A (en) * 1994-10-20 1998-01-13 Hughes Aircraft Flip chip high power monolithic integrated circuit thermal bumps
JPH08148495A (en) * 1994-11-25 1996-06-07 Fujitsu Ltd Semiconductor device, manufacturing method thereof, and bump adhesion evaluation method in semiconductor device
JPH08213425A (en) * 1995-02-03 1996-08-20 Matsushita Electron Corp Semiconductor device and manufacturing method thereof
US6583514B2 (en) 2000-10-04 2003-06-24 Nec Corporation Semiconductor device with a binary alloy bonding layer
JP2005311188A (en) * 2004-04-23 2005-11-04 Fuchigami Micro:Kk Multilayer wiring board
JP5817893B1 (en) * 2014-07-14 2015-11-18 大日本印刷株式会社 Component mounting wiring board and manufacturing method thereof

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