JPH04225558A - Semiconductor memory and production thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which allows no disconnection at the contact part of a first wiring layer and easy patterning at a photolithography process for a DRAM which stores information by charges accumulated on a data storage area (capacitor). CONSTITUTION:The node electrode 7 of a stack type capacitor provided at the top of a bit line 4 and the first wiring layer 7a of a peripheral circuit are provided on the same layer. A plate electrode 9, which is the other electrode of the capacitor, is provided at the top of the node electrode 7 through an dielectric film 8 and a second wiring layer 12 is connected with the plate electrode 9 and the first wiring layer 7a.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a memory cell structure of one transistor/one capacitor that stores information using charges accumulated in a data storage region (capacitor). The present invention relates to a semiconductor memory device and a method of manufacturing the same.

0002

2. Description of the Related Art Generally, in semiconductor memory devices, the area of the memory cells is reduced as the integration becomes higher.
A stacked memory cell in which a capacitor section is provided above the data line as shown in Fig. 1 has been proposed (S. Kimu
ra, A New Stacked Capac
itor DRAM Cell Character
Erized by aStorage Cap
accitor on a Bit-line
Structure, IEDM Tech. Di
g. , P.P. 596-599, Dec. 1988. ). In FIG. 3, 21 is a semiconductor substrate, 22 is an isolation region, 2
3 is a transistor, 24 is a bit line, 25 is a first interlayer insulating film, 26 and 26a are openings, 27 is a node electrode,
27a is a first wiring layer, 28 is a capacitive insulating film, 29 is a plate electrode, 30 is a second interlayer insulating film, 31 is an opening, 3
2 is a second wiring layer.

In FIG. 3, a first wiring layer 27a is formed on a capacitor formed of a node electrode 27, a capacitor insulating film 28, and a plate electrode 29.

0004

[Problems to be Solved by the Invention] However, in the above-mentioned conventional configuration, since the node electrode and plate electrode of the capacitor are formed in the memory cell area more than the peripheral circuit area, the difference in level between the memory cell area and the peripheral circuit area is large. This causes problems with the patterning accuracy of the first wiring layer in photolithography, and furthermore, there is the problem of disconnection of the first wiring layer due to the large step difference in the contact area between the peripheral circuitry and the underlying substrate. Ta.

The present invention solves the above-mentioned conventional problems, and provides a semiconductor memory device that prevents disconnection at the contact portion of the first wiring layer and facilitates patterning by photolithography, and a method for manufacturing the same. The purpose is to

[0006]

[Means for Solving the Problems] In order to achieve this object, the semiconductor memory device of the present invention includes a node electrode of a stacked capacitor provided above a bit line and a first wiring layer of a peripheral circuit section. The plate electrode, which is the other electrode of the capacitor, is provided on the same layer and is provided on top of the node electrode via a capacitive insulating film, and the second wiring layer is connected to the plate electrode and the first wiring layer. In addition, the method for manufacturing a semiconductor device of the present invention includes a step of forming a predetermined transistor, a bit line, and a first interlayer insulating film on a semiconductor substrate, and a step of forming an opening in a predetermined region of the first interlayer insulating film. A step of simultaneously forming a node electrode formed using an etching method and connected to a predetermined area of a memory cell in a semiconductor substrate through the opening and a first wiring layer connected to a peripheral circuit section; After forming a plate electrode on the top of the capacitive insulating film, a second wiring layer is connected to the plate electrode and the first wiring layer through an opening provided in a second interlayer insulating film formed on the top of the plate electrode. It has a structure consisting of a step of forming a wiring layer.

[0007]

[Function] With this configuration, the difference in level between the memory cell area and the peripheral circuit area can be reduced, making it easier to pattern the first wiring layer by photolithography, and furthermore, the difference in level between the peripheral circuit area and the underlying substrate can be reduced. Since the contact area of the first wiring layer can be made small, disconnection at the contact portion of the first wiring layer can be prevented.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a DRAM which is an embodiment of a semiconductor memory device according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is an isolation region, 3 is a transistor, 4 is a bit line, 5 is a first interlayer insulating film, 6 and 6a are openings formed at the same time, 7 is a node electrode, and 7a is a first interlayer insulating film. 1 wiring layer,
8 is a capacitive insulating film, 9 is a plate electrode, 10 is a second interlayer insulating film, 11 is an opening, and 12 is a second wiring layer.

In FIG. 1, a semiconductor substrate 1 is shown on which a predetermined isolation region 2, a transistor 3, a bit line 4, and a first interlayer insulating film 5 (description of the interlayer insulating film formed below this is omitted) are formed. A node electrode 7 and a first wiring layer 7 are connected to the base substrate through predetermined openings 6, 6a.
a are formed in the same layer. A capacitor consisting of a capacitive insulating film 8 and a plate electrode 9 is formed on this node electrode 7. Then, the capacitive insulating film 8 and the plate electrode 9
A second wiring layer 12 is formed which is connected through a predetermined opening 11 of the second interlayer insulating film 10 .

The above DRAM includes a node electrode 7 that holds information in the form of charges, a capacitor insulating film 8, and a plate electrode 9.
A bit line 4 for exchanging electric charge with an external circuit, a first wiring layer 7a, a second wiring layer 12, and a transistor 3.

As described above, according to this embodiment, the difference in level between the memory cell area and the peripheral circuit area can be reduced, so that the first
This facilitates patterning of the wiring layer by photolithography, and furthermore, the difference in level between the contact portion of the peripheral circuit portion and the underlying substrate can be reduced, so that disconnection at the contact portion of the first wiring layer can be prevented.

FIG. 2 is a process cross-sectional view of a method for manufacturing a semiconductor memory device according to the present invention. First, as shown in FIG. 2(a), a bit line 4 made of high melting point silicide or its polycide is placed on a semiconductor substrate 1 on which an isolation region 2 formed by a buried isolation method using an insulating film and a transistor 3 are formed. is formed by photolithography, and then a first interlayer insulating film 5 such as a silicon oxide film is formed by, for example, CVD.

Next, as shown in FIG. 2B, after openings 6 and 6a connected to a predetermined area of the base of the memory cell and a predetermined area of the base of the peripheral circuit are simultaneously formed by photolithography, for example, , high melting point metals such as tungsten (W), aluminum metals such as aluminum (Al)-silicon (Si)-copper (Cu), or wiring materials such as Cu.
It is formed by a method or a sputtering method. Thereafter, a predetermined node electrode 7 and a first wiring layer 7a of the peripheral circuit section are simultaneously formed by photolithography. Next, as shown in FIG. 2(c), a ferroelectric film such as titanium sambarium (BaTiO3) or an oxide film such as tantalum (Ta) or titanium (Ti) is used as a capacitive insulating film 8 using CVD or sputtering. A high-melting point metal such as W, an aluminum metal such as Al-Si-Cu, or a wiring material such as Cu is formed on top of the wiring material by CVD or sputtering, and a predetermined pattern is formed using photolithography. A plate electrode 9 is formed. Thereafter, a second interlayer insulating film 10 is formed using, for example, a silicon oxide film formed by a CVD method, and a predetermined area of the plate electrode 9 and the first wiring layer 7a is formed on the second interlayer insulating film 10. A connecting opening 11 is formed using a photolithography method, and after forming an aluminum-based metal using a sputtering method, for example, a second wiring layer 12 is formed using a photolithography method.
form.

[0015]

As described above, the present invention can reduce the level difference between the memory cell area and the peripheral circuit area, making it easier to pattern the first wiring layer by photolithography, and further improving the patterning of the base substrate of the peripheral circuit area. Since the step difference between the contact portion and the first wiring layer can also be reduced, disconnection at the contact portion of the first wiring layer can be prevented, which has a great practical effect. It goes without saying that the process can also be simplified.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a DRAM which is an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a process cross-sectional view of the method for manufacturing a semiconductor memory device according to the present invention.

[Figure 3] Cross-sectional view of a conventional stacked memory cell

[Explanation of symbols]

3 Transistor 4 Bit line 7 Node electrode 7a First wiring layer 8 Capacitive insulation film 9 Plate electrode 12 Second wiring layer

Claims (2)

[Claims] 1. In a dynamic RAM having a one-transistor/one-capacitor structure in which a stack type capacitor is provided above a bit line, a node electrode of the capacitor connected to the transistor and a first wiring layer of a peripheral circuit section are connected to each other. A semiconductor memory device in which a plate electrode, which is the other electrode of the capacitor, is provided on the same layer above the node electrode via a capacitive insulating film, and a second wiring layer is connected to the plate and the first wiring layer. . 2. A step of forming a predetermined transistor, a bit line, and a first interlayer insulating film on a semiconductor substrate;
An opening is formed in a predetermined area of the interlayer insulating film using photolithography, and through this opening, a node electrode is connected to a predetermined area of a memory cell in a semiconductor substrate, and a peripheral circuit is connected. A step of simultaneously forming a first interconnection layer with a capacitance insulating film formed above the node electrode, and then forming an opening in a second interlayer insulating film formed above the plate electrode. A method for manufacturing a semiconductor memory device, comprising the step of forming a second wiring layer through which the plate electrode and the first wiring layer are connected.