JPH042284A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To reduce the apparent horizontal transfer frequency and the power consumption by constituting an output section with four horizontal output registers or over to output two horizontal lines or over simultaneously. CONSTITUTION:The output section 21 consists of 4 horizontal output registers 251-254 in parallel or over, a transfer channel 27 is formed between a storage section ST1 of one phase of a horizontal output register of pre-stage and a storage section ST2 of the other phase of a horizontal output register of post- stage adjacent to each other and signal charges e11, e12, e21, e22 of two horizontal lines or over are read simultaneously by the horizontal output register. Thus, the apparent horizontal transfer frequency is reduced and the power consumption is decreased.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a solid-state imaging device using a CCD.

[Summary of the invention]

The present invention provides a solid-state image sensor that transfers signal charges from each light receiving section in the vertical direction and reads out signal charges for each horizontal line at an output section, in which the output section is configured with four or more horizontal output registers arranged in parallel. , a transfer channel is formed between the accumulation section of one phase of each adjacent preceding horizontal output register and the accumulation section of the other phase of the subsequent horizontal output register;
By simultaneously reading out signal charges for a horizontal line or more by a horizontal output register, the apparent horizontal transfer frequency is reduced and power consumption is reduced.

[Conventional technology]

Three types of CCD solid-state imaging devices are known: a frame transfer type, an interline transfer type, and a frame interline type.

As shown in the principle diagram of Fig. 4, a frame transfer type CCD image sensor has a light receiving area (2) formed by arranging a plurality of light receiving elements (1) in a matrix, and a light receiving area (support) of the light receiving area (2).
A storage region (4) is formed by arranging a plurality of storage elements (3) in a matrix to temporarily store the signal charges obtained in and a horizontal output register (5) for reading.

As shown in the principle diagram of FIG. 5, the interline transfer type CCD image sensor includes a plurality of light receiving sections (6) arranged in a matrix, and is provided on one side of each row of the light receiving sections (6). A plurality of vertical transfer registers (7) vertically transfer signal charges from each light receiving section (6), and a plurality of vertical transfer registers (7) provided on the terminal side of the vertical transfer registers (7).
) for reading signal charges for each horizontal line.

As shown in the principle diagram of FIG. 6, a frame interline type CCD image sensor has a plurality of light receiving sections (11) arranged in a matrix, and a light receiving section (11) is arranged on one side of each row of light receiving sections (11).
A photosensitive area (13) forming a vertical transfer register (12) that vertically transfers signal charges from 11) and a plurality of vertical transfer registers that temporarily store signal charges provided at the end of the vertical transfer register. The storage area (14) has a storage area (14), and a horizontal output register (15) for reading signal charges from the storage area (14) for each horizontal line.

On the other hand, in order to correspond to the higher resolution and smaller size of solid-state image sensors, two horizontal output registers are provided as output units for reading out the signal charges for each horizontal line, and one of the signal charges for each horizontal line is read out. A configuration in which the signal charges of every other line and the other signal charges of every other line are distributed and outputted to two horizontal output registers, respectively, and furthermore, the signal charges of one horizontal line are distributed and outputted to multiple horizontal output registers. A configuration in which the
No. 78 and Japanese Patent Application No. 56-65657).

[Problem to be solved by the invention]

Incidentally, in recent years, as the resolution of solid-state image sensing devices has become higher, it has been desired to reduce the horizontal transfer frequency to save power consumption.

In view of the above-mentioned points, the present invention provides a solid-state image pickup device that has a simple structure, reduces horizontal transfer frequency, and enables power consumption to be reduced.

[Means to solve the problem]

The present invention provides a solid-state image sensor in which signal charges from each light receiving section are transferred in the vertical direction and signal charges for each horizontal line are read out at an output section (21). Output register (25) [(25,) ~ (2
5, )), and a transfer channel is provided between the storage section (ST, ) for one phase of each adjacent previous horizontal output register and the storage section (ST2) for the other phase of the horizontal output register at the subsequent stage. (21?) l: ft5ALz, signal charge of 2 or more horizontal lines (all, el□) + (e2 +
+e2□) are configured to be read out simultaneously by the horizontal output register (25).

[Effect]

In the present invention, the output section (21) is formed by four or more horizontal output registers (25), and each horizontal line's signal charge is
Signal charge of 2 or more horizontal lines (all+e12) + (e21+e22) distributed to the main horizontal output register
By outputting , the apparent horizontal transfer frequency is reduced in all pixel readout, and power consumption can be reduced.

〔Example〕

Hereinafter, an example of a CCD solid-state image sensor according to the present invention will be described with reference to the drawings.

Figure 1 shows a part of the solid-state image sensing device according to this example. In the figure, (VR) ((VR,), (VR2)) is a CCD structure that transfers signal charges from the light receiving part in the vertical direction. A plurality of vertical transfer registers, (21) indicates an output consisting of a horizontal output register coupled to the transfer end of the vertical transfer register (VR). Vertical transfer registers (21) are provided corresponding to the number of light receiving sections (not shown) in the horizontal direction, and each vertical transfer register (VR) is separated by a channel stop region (22) shown by a broken line. Vertical transfer register (
There is a readout game (VR) at the connection position of the output section (2I).
(23) is provided, this reading game) (23)
The transfer of signal charges from the vertical transfer register (VR) to the output section (21) is controlled by the potential applied to the gate electrode (24) of the vertical transfer register (VR).

The output section (21) includes, for example, four horizontal output registers (25
), i.e. first, second, third and fourth horizontal output registers (25,), (25□) of mutually horizontal CCD structure.

It is composed of (25,) and (25,). For each horizontal a force (25,), (252), (253
) and (25,) are the storage section (accumulation section) (ST, ), (ST2) and the transfer section (#,
, transmission section) (TR,), (TR2), and has multiple transfer areas (26) [(26,), (26□)],
A clock pulse φ with a phase of 1 is applied to every other transfer electrode (26,) in each horizontal output register (25).
However, a clock pulse φ2 of a different phase is applied to every other transfer electrode (26,) to transfer signal charges in the horizontal direction by so-called two-phase driving. Between each adjacent horizontal output register (25), there is a transfer channel (25) with a CCD structure for transferring signal charges from the previous horizontal output register to the subsequent horizontal output register.
27) is formed. In this case, the transfer channel (27
) is the entire vertical transfer register (VR) as will be explained later.
is formed every other time. That is, for example, the 1 phase storage section (ST,) of the first horizontal output register (25,) and the second horizontal output register (25,)
A transfer channel (27) is formed between the other phase storage section (ST2) of the second horizontal output register (25,), and the one phase storage section (s'r,
) and the storage section (ST2) of the other phase of the third horizontal output register (253), a transfer channel (27) is formed between the third horizontal output register (25,
) of the first phase storage part (ST, ) and the fourth
A transfer channel (27) is formed in the storage section (s'r,) of the other phase of the horizontal output register (25,). Each horizontal output register (25) and each transfer channel (27) are connected to a channel stop area (2
2). Here, in the output section (21), the 1 phase inversion region (2
The same voltage is applied to the transfer electrodes (not shown) of the transfer regions (262) of the other phase, and the same voltage is applied to the transfer electrodes (not shown) of the transfer regions (262) of the other phase. The same potential is applied to the gate electrodes 27) (not shown). Therefore, the output section (
The horizontal output register (25) is used as the electrode in the horizontal output register (21).
It is composed of three types of electrodes: a transfer electrode in the 1 phase transfer region (26, ), a transfer electrode in the other phase transfer region (26□), and a gate electrode in the transfer channel (27). Each vertical transfer register (VRI) and (VR2)
are stored in the storage sections (s'r,) and (ST2) of the transfer areas (26,) and (26,) of the first horizontal output register (25,), respectively (i.e., one of the horizontal a registers (25)). /2 bits per storage section).

Next, regarding the operation of this embodiment, Figure 2 (potential change diagram during transfer between horizontal output registers) and Figure 3 (
This will be explained with reference to the timing chart. The potential changes in FIG. 2 are shown for the transfer paths marked ■ to ◎ in FIG. 1.

First, the vertical transfer register (VR) [:(VR,),
The signal charge (e+
□), (e, □), turn on the readout gate (23) at time to (Fig. 3), and at the same time turn on the 1 phase transfer area (26, □) of the horizontal output register (25).
), the transfer region (262) of the other phase, and the transfer channel (27) are turned on (high level). As a result, as shown in FIG. 2A, the vertical transfer register (VR,)
The signal charge (e+□) from the 1 phase transfer region (26,) of the first horizontal 8 register (25,)
storage unit (STI), transfer channel (27
) and the storage section (ST2) of the other phase transfer area (262) of the second horizontal output register (252)
i,: The signal charge (e, 2) from the vertical transfer register (VR2) is transferred to the storage section (ST2) of the other phase transfer area (26□) of the first horizontal output register (25,). be transferred.

Next, time 1+ (Figure 3 and Figure 2 B) and time tz (
1 of the horizontal output register (25) in Fig. 3 and Fig. 2 C>
After turning on the transfer channel (27) with the transfer region (26) of the phase turned off (low level), and then turning on the transfer channel (27) and the transfer region (26□) of the other phase, At time t3 (Figure 3), the horizontal output register (
25), the transfer region (26,) of phase 1 and the transfer channel (27) are both turned off, and the transfer region (2) of the other phase is turned off.
62) Turn on. As a result, as shown in No. 211D, the signal charge (e, ) from one vertical transfer register (VRI) is transferred to the second horizontal output register (25,
) is completely transferred to the storage section (ST2) of the other phase. The signal charge (e+□) from the other vertical transfer register (VL) is transferred to the first horizontal output register (2
5,) remains in the storage section (ST, ) of the other phase.

Next, at time 1 < (Figure 3), the transfer channel (27) is kept off, the transfer area (26,) of phase 1 is turned on, and the transfer area (26,) of the other phases is turned off. do. As a result, each signal charge (e
, , ) and (e+□) are the respective ones of the first and second horizontal output registers (25,) and (252), respectively.
172 bits are transferred to storage 1 (ST, ) of the phase.

Next, at times js+t6 and t11 (Fig. 3), the transfer channel (27) is turned on (see Fig. 2F) in sequence, and the transfer area of 1 phase (
26,) is turned off (see Figure 2G), and the transfer region (26,) of the other phase is turned off along with the transfer channel (27).
After turning on (see FIG. 2H), the transfer channel (27) is turned off together with the 1 phase transfer region (26,) at time ts (FIG. 3). As a result, the signal charge (e+□) is transferred to the third horizontal output register (
253) Other phase storage section (ST2)
Then, the signal charge (e,,) is stored in the storage section (ST2) of the other phase of the second horizontal output register (252).
will be forwarded to.

Next, at time ts (Figure 3), while keeping the transfer channel (27) off, the transfer area (26,) of phase 1 is turned on, and the transfer areas (262) of the other phases are turned off. As shown in Figure 2J, the signal charges (e,
, ) is 1 of the third horizontal output register (253)
The signal charge (e
+□) are each transferred 172 bits to the 1 phase storage section (ST+) of the second horizontal output register (252).

Next, time tI. (Read out the game again in Figure 3) (
23) and at the same time turn on the horizontal output register (25).
transfer region (26,) and (2
62), the second data from the vertical transfer register (VRI), (VR,) is turned on as shown in FIG. 2R.
The signal charges (e2.) and (8,2) of the horizontal lines of are transferred to the first horizontal output register (25,), respectively.

Then, at time i+1+ i12 and t+3 (FIG. 3), the above time 1. ．． 1. and t, and the same potentials are sequentially applied to the horizontal output register (25) and the transfer channel (27).
give to As a result, as shown in FIG. 2N, the signal charges (e, , ), (e, ,
) are the fourth and third horizontal output registers (25,)
and (253), that is, the (alternate signal charges (e,,) are distributed to the fourth horizontal output register (253).
5, ) of the transfer area of the other phase (s'
r, ), and every other signal charge (e, 2)
is transferred to the storage section (ST2) of the other phase transfer area of the third horizontal output register (25,), and the signal charges (e2□), (e2
．． ) are the second and first horizontal output registers (252>
and (25,), that is, every other signal charge (e,,) is distributed to the second horizontal output register (25,).
5□) Storage section (ST,
), the other signal charges (e, , ) are transferred to the storage section (ST2) of the other phase transfer region of the first horizontal output register (25,), respectively.

After this, the transfer areas of phase 1 and other phases (26,
) and (26,) respectively with two-phase transfer lock φ
1 and φ2 to four horizontal □ output registers (25
) to drive each signal charge (e,,), (e,=),
(e2.) and (e, 2) are transferred in the horizontal direction. The outputs of these two horizontal lines are serially converted (order corrected) by a multiplexer, for example, and then supplied to a subsequent signal processing system.

According to this configuration, four horizontal output registers (25,
) to (254) to calculate the signal charge of two horizontal lines (
By reading out all + e12) and (e21 + e22) at the same time, for example, in an all-pixel readout image sensor, the apparent horizontal transfer frequency is lower than when reading out one horizontal line with two conventional horizontal output registers. 172, and as a result, power consumption can be reduced by half. In addition, although it has four horizontal output registers (25), only three types of electrodes are required, and the output part (
21) can be configured. Also, without affecting the transfer efficiency of horizontal transfer, the horizontal output register (25)
Transfers can be made between.

When transferring charges between horizontal output registers (25), signal charges (e, ,), (e, 2), (e=,)
, (e-2), etc. can be easily and reliably transferred without mixing, and signals of two horizontal lines can be output simultaneously without phase shift. still,
In the upper part, four horizontal output registers are used to simultaneously output the signal charges of two horizontal lines.
25) so that signal charges of two or more horizontal lines can be output simultaneously.

Further, the output section (21) according to the present invention can be applied to the output section of the solid-state image sensor of the above-mentioned frame transfer type, interline transfer type, frame interline type, etc.

〔Effect of the invention〕

According to the present invention, in a solid-state image sensor, the apparent horizontal transfer frequency can be reduced by configuring the output section with four or more horizontal output registers and outputting signal charges of two or more horizontal lines at the same time. , it is possible to reduce power consumption.

In addition, a transfer channel is formed between the 1 phase accumulation section of each adjacent preceding horizontal output register and the other phase accumulation section of the subsequent horizontal output register, so charge transfer between the horizontal output registers is facilitated. In addition, signal charges can be output through each horizontal output register without phase shift.

Therefore, it is particularly suitable for application to solid-state imaging devices that are downsized or have high resolution.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing the main parts of the solid-state image sensor according to the present invention, Fig. 2 is a potential change diagram during transfer between horizontal output registers, Fig. 3 is a timing chart, and Figs. 4 to 6.
Each figure is a diagram showing the basic configuration of a solid-state image sensor. (VR,) (VR2) is the vertical transfer register, (21)
is an output section, (25,) to (25,) are horizontal output registers, (26,) (26,) is a transfer area, and (27) is a transfer channel.

Claims (1)

[Claims] In a solid-state image sensor that transfers signal charges from each light receiving section in the vertical direction and reads out signal charges for each horizontal line at an output section, the output section includes four or more horizontal output registers arranged in parallel. At the same time, a transfer channel is formed between the accumulation section of one phase of each adjacent preceding horizontal output register and the accumulation section of the other phase of the subsequent horizontal output register, and the signal charge of two or more horizontal lines is transferred. are simultaneously read out by the horizontal output register.