JPH0423006A - Execution processor for sequence instruction - Google Patents

Abstract

PURPOSE:To relieve an error if detected in a mask ROM and to use this ROM as it is by providing a RAM into a sequence instruction executing processor in order to store an additional microprogram in the RAM and carrying out this program. CONSTITUTION:A RAM 43 is provided to a sequence instruction executing processor 40 which contains a mask ROM 42 storing a microprogram which carries out a sequence instruction of a programmable controller PC. A control circuit 41 decides whether the program stored in the ROM 42 includes an error or not. If so, a relieving additional program stored in a register 45 from outside is written in the RAM 43. As a result, the sequence instruction is carried out with no interruption by means of the program of the RAM 43 if the program of the ROM 42 includes an error when a sequence program stored temporarily in a register 44 is carried out via the circuit 41.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sequence instruction execution processor used in a PC (programmable controller), and particularly to a microprogram control type sequence instruction execution processor.

[Conventional technology]

As sequence program control becomes more precise and faster, main processors become more
Controlling all of C slows down the processing speed and has reached its limit.

Therefore, sequence instructions consisting of basic instructions (LD, AND, 0RSOUT, etc.) and more advanced and complex functional instructions (timer, counter, transfer, four arithmetic operations, etc.) have come to be processed by sequence instruction execution processors.

A microprogram control method is one method for processing sequence instructions at high speed with a sequence instruction execution processor. Microprogram control methods are widely used because they can process highly functional machine language instructions without complicating the hardware configuration, and are highly versatile, flexible, and expandable.

On the other hand, memories for storing microprograms in LSIs of sequence program execution processors have also become more dense, and mask ROMs have been widely adopted from the viewpoints of packaging density, access time, and cost. Particularly as a microprocessor-controlled program storage memory capable of high-speed processing, mask ROM is not rewritable, but once completed, it is advantageous in terms of reliability and cost, and is widely used.

[Problem to be solved by the invention]

However, once the mask ROM in the sequence instruction execution processor LSI is completed, it cannot be rewritten.
If there is an error in the microprogram, the processor cannot be used and must be discarded. Moreover, even if it were to be manufactured again, development and costs would be required, and the development period would be particularly long.

The same applies when adding a new microprogram.

Furthermore, if the microprogram ROM is placed outside the sequence instruction execution processor LSI, the microprogram can be easily depacked, but the number of bins of the sequence instruction execution processor LSI increases, the size of the LSI increases, and the microprogram A space is also required to mount the ROM.

The present invention has been made in view of the above-mentioned problems, and is designed to enable the use of a mask ROM in which a microprogram has a partial error.
It is an object of the present invention to provide a sequence instruction execution processor provided with an additional RAM inside an SI.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a sequence instruction execution processor having a built-in mask ROM storing a microprogram for executing sequence instructions in a PC (programmable controller). A RAM for storing microprograms, a register for storing sequence instructions from an external memory, and determining whether or not relief is required from the sequence instructions stored in the registers, and storing them in the RAM when necessary. A sequence instruction execution processor is provided, characterized in that it has a control circuit that selects a microprogram.

[Effect]

Normal sequence instructions are read into registers and processed by a mask ROM microprogram. However, if the sequence instruction has an error in the microprogram, the control circuit determines from the sequence instruction that the microprogram in the mask ROM cannot be used, selects and executes the rescue microprogram in the RAM.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 2 is a hardware block diagram of a PC (programmable controller) equipped with the sequence instruction execution processor of the present invention. In the figure, CPUII is P
This is the main processor that controls the entire CIO. The input circuit 12 receives a signal from the outside, converts the signal level, and transfers the signal to the bus 15. Pressure circuit 13 outputs the output signal from bus 15 to the outside.

A management program 20a that manages the execution of ladder programs is stored in the ROM 20.

The RAM 30 stores various data, and also stores a ladder program 31. Ladder program 31
is a type of sequence program created in ladder format for controlling machine tools, etc. In addition, sequence programs may be created in a high-level language such as Pascal.

Further, the RAM 30 also stores an additional microprogram 32 for relief that corresponds to a sequence command of an erroneous microprogram among the microprograms 42a stored in a mask ROM 42, which will be described later.

The interface 60 for the program creation device is the bus 15.
This is an interface circuit for connecting the program creation device 61 and the program creation device 61.

The program creation device 61 is a device for creating and daybugging the ladder program 31, and the liquid crystal display device 6
2. It has a keyboard 63.

The sequence instruction execution processor 40 is equipped with a mask ROM 42 in which a microprogram 42a is stored and a RAM 43 in which an additional microprogram 43a is stored, and is a sequence instruction execution processor that exclusively executes the ladder program 31. The I10 image RAM 52 stores images of input signals and output signals. FIG. 1 is a circuit diagram of a sequence instruction execution processor according to an embodiment of the present invention. The sequence instruction execution processor 40 is configured as a one-chip LSI.

As shown in FIG. 2, the sequence instruction execution processor 40 is connected to the main processor 11 and a RAM 30, and the RAM 30 stores an additional microprogram 32 and a ladder program 31.

The main browser 11 instructs the control circuit 41 to load the additional microprogram 32, execute and stop the ladder program 31, etc.

The control circuit 41 mainly reads sequence instructions and determines whether the sequence instructions require relief. A microprogram 42a is stored in the mask ROM 42. Additional microprogram 43a in RAM43
is stored.

The additional microprogram 43a is a microprogram that rescues an erroneous microprogram stored in the mask ROM 42. This additional microprogram 4
3a, the additional microprogram 32 in the RAM 30 is loaded by the control circuit 41 via the register 45 in accordance with instructions from the main processor 11.

The register 44 is a register that temporarily stores sequence instructions. The register 45 is a register in which the additional microprogram 32 for relief is stored and transferred to the RAM 43. For example, if the RAM 30 has a bit width of 16 bits and the additional microprogram 43a of the RAM 43 has a bit width of 64 bits, the register 45 converts the bit width and stores it in the RAM 43. be transferred.

The selector 46 selects either the sequence command from the register 44 or the microcode from the register 48 and sends it to the sequencer 47. Which one is selected is determined by the microcode in register 48.

The sequencer 47 specifies the start addresses of the microprograms 42a and 43a stored in the mask ROM 42 and RAM 43.

The microcode register 48 stores the microcode of the microprogram to be executed, and outputs it to the sequencer 47, arithmetic unit (ALTJ) 51, and selector 50, respectively. The output to the sequencer 47 is for selecting the next instruction to be executed, controlling jump instructions, etc. The output to the selector 50 is a control signal that selects either the register 44 or the internal register 49 as the input of the arithmetic unit 51.

The output to the arithmetic unit 51 is a control signal that selects the arithmetic function of the arithmetic unit 51. Also, the calculation result of the calculation unit 51 is I10
It is output to the image RAM 52.

The control circuit 41 decodes the instruction code stored in the register 44 and sends it to the sequencer 47 via the selector 46.
Specify the start address of the microprogram.

In this case, the control circuit 41 determines from the definition of the instruction code whether the microprogram 42a or the additional microprogram 43a is to be used, and outputs chip select signals C81 and C52. That is, if the instruction code requires relief, the signal C32 is pressed, and if it is not necessary, the signal C81 is output.

The sequencer 47 normally specifies an address for the mask ROM 42. If the instruction code requires repair, the address is specified in the RAM 43. Mask RO
The microprogram 42a1 stored in the M42 or the additional microprogram 43a stored in the RAM 43 is executed from the specified address and outputs the microcode. This microcode includes control signals for controlling access to the sequencer 47, arithmetic unit 51, internal register 49, I10 image RAM 52, and the like.

The sequencer 47 issues the next address to the mask ROM 42 based on the control signal included in the microcode, and sequentially executes the microprograms. Arithmetic unit 5
1 reads and writes data from the I10 image RAM 52 into the internal register 49, performs four arithmetic operations, etc. based on the control signal of the microcode.

FIG. 3 is a flow chart of one embodiment of the present invention. In the figure, the number following S indicates the step number.

[S1] The control circuit 41 reads the sequence command of the ladder program 31 from the RAM 30 and stores it in the register 44.

[S2] Determine whether relief is necessary from the instruction code of the sequence instruction. If necessary, proceed to S3; otherwise, proceed to S4.

[S3] Since the sequence instruction has an instruction code that requires relief, the address where the microprogram is stored is read and the corresponding start address of the RAM 43 is designated.

[S4] Specify the start address of the mask ROM 42 corresponding to the sequence command.

[S5] Output the microcode of the corresponding microprogram to the register 48.

[S6] A sequence instruction is executed by the microcode of the register 48.

In this way, a sequence instruction is read out, and if it is a normal sequence instruction, the microprogram in the mask ROM 42 is executed, and if the sequence instruction requires relief, an additional microprogram in the RAM 43 is executed. This makes it possible to correct errors in the microprogram 42a.

In the above explanation, the error in the microprogram stored in the mask ROM 42 is repaired, but when necessary sequence instructions are added after the mask ROM 42 is completed, the necessary microprogram can be added to the additional microprogram in the same way. By including it in the program 32, the added sequence instructions can be executed in the same way.

Further, in the above explanation, the additional microprograms are transferred to the RAM 43a in a batch, but when the number of additional microprograms is large, the capacity of the RAM 43 may be insufficient.

Since it is difficult to increase the capacity of the RAM 43 due to the LSI configuration, the control circuit 41 responds to the sequence instruction from the RAM 30 whenever the sequence instruction read into the register 44 requires relief. Additional microprograms may also be loaded into RAM 43 and configured to execute sequence instructions.

Furthermore, in the above description, the memory for storing the additional microprogram and the ladder program is the RAM 30, but it is also possible to use FROM or the like instead of RAM'M.

〔Effect of the invention〕

As explained above, in the present invention, a RAM is provided inside the sequence instruction execution processor, and an additional microprogram for relief is stored and executed. However, the sequence instruction execution processor can be used as is, which eliminates the development time and cost of re-creating the sequence instruction execution processor LSI.

In addition, even if it is necessary to add a new sequence instruction, you can simply add the corresponding microprogram without having to rebuild the sequence instruction execution processor LSI.
It can be used as is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a sequence instruction execution processor which is an embodiment of the present invention, FIG. 2 is a block diagram of the hardware of a PC equipped with the sequence instruction execution processor of the present invention, and FIG. 3 is an embodiment of the present invention. It is a flow chart of an example. 2a 3a PC (programmable controller) Main processor OM AM Ladder program additional microprogram sequence instruction execution processor Control circuit mask ROM Microprogram AM Additional microprogram register register Sequencer register Internal register operator I10 Image RAM Patent applicant Fanuc Corporation Agent Patent Attorney Takeshi Fukuya

Claims (4)

[Claims] (1) In a sequence instruction execution processor that has a built-in mask ROM that stores a microprogram that executes sequence instructions in a PC (programmable controller), a mask ROM that stores the microprogram, a RAM that stores a rescue microprogram, a register that stores sequence instructions from an external memory; and a control circuit that determines whether or not relief is required based on the sequence instructions stored in the register, and selects a microprogram stored in the RAM when necessary. A sequence instruction execution processor characterized by having the following. (2) The control circuit collectively stores the plurality of relief microprograms from the external memory.
2. The sequence instruction execution processor according to claim 1, wherein the sequence instruction execution processor is configured to transfer to an AM. (3) The sequence according to claim 1, wherein the control circuit is configured to transfer the relief microprogram from the external memory to the RAM when a necessary sequence instruction is read. Instruction execution processor. (4) The relief microprogram includes the mask R.
2. The sequence instruction execution processor according to claim 1, further comprising new microcode not included in OM.