JPH04230178A - Cyclic type noise reduction circuit for video signal - Google Patents

Abstract

PURPOSE:To form the circuit with components operated at a comparatively low speed by selecting a delay time generated between a time difference between write and read by a picture memory circuit to be a specific value. CONSTITUTION:An input video signal is delayed by a delay time delay circuit 7 through a control circuit 6 and multiplied by (1-K) at an arithmetic circuit 2. An output signal of a picture memory circuit 10 is delayed by a delay time delay circuit 8 through the control circuit 6 and multiplied by K at an arithmetic circuit 3. An output signal of the picture memory circuit 10 is subtracted from the input video signal by a subtractor circuit 5 and the K is controlled by the control circuit 6 attended with the said output. Then a delay time generated by write read of the picture memory circuit 10 is set to (one frame period - delay time by control circuit 6-delay time by arithmetic circuit 2). Thus, the timing of the signal outputted from the control circuit 6 and the input timing of the arithmetic circuits 2,3 are coincident.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cyclic noise reduction circuit for video signals which performs noise reduction by processing a video signal using a cyclic filter.

0002

2. Description of the Related Art A conventional cyclic noise reduction circuit for video signals, as shown in FIG. A first arithmetic circuit 2 that multiplies and an image memory circuit 1
a second arithmetic circuit 3 that multiplies the signal output from the first arithmetic circuit 3 by K;
An adder circuit 4 adds the output of the arithmetic circuit 2 and the output of the second arithmetic circuit 3 and outputs the output as a noise reduction output and stores it in the image memory circuit, and the signal output from the image memory circuit 1 is added to the input image. A subtraction circuit 5 that subtracts from the signal, and a control circuit 6 that controls the K value of the first arithmetic circuit 2 and the K value of the second arithmetic circuit 3 in accordance with the output of the subtraction circuit 5.
The output signal of the noise reduction circuit is delayed by one frame in the image memory circuit 1, and the signal obtained by multiplying the output signal of the noise reduction circuit delayed by one frame by K and the input video signal are (1 -K) Noise reduction is performed by adding the multiplied signal. Note that K is 0<K<1.

0003

In the conventional cyclic noise reduction circuit for video signals described above, a delay of one frame period (Tf) is performed in the image memory circuit 1. However, if a delay of one sample period or more occurs between the input and output of the video cyclic noise reduction circuit, the time difference between the two inputs in the subtraction circuit 5 will no longer be one frame period (Tf). However, since the subtraction circuit 5 must take the difference between the input video signal and the output of one frame before, in the conventional cyclic noise reduction circuit for video signals, one frame is required between the inputs of the subtraction circuit 5. All processing must be done within one sample period to make a difference. For this purpose, there was a problem in that the circuit had to be composed of elements that operated at high speed. SUMMARY OF THE INVENTION An object of the present invention is to provide a cyclic noise reduction circuit for video signals that can be constructed from elements that operate at relatively low speeds.

0004

[Means for Solving the Problems] A cyclic noise reduction circuit for video signals of the present invention includes an image memory circuit, a first arithmetic circuit that multiplies an input video signal by (1-K), and an output signal from the image memory circuit. a second arithmetic circuit that multiplies the signal by K;
An addition circuit that adds the output of the first arithmetic circuit and the output of the second arithmetic circuit and outputs the output as a noise reduction output and stores it in the image memory circuit; In a cyclic noise reduction circuit for a video signal, which includes a subtraction circuit that performs subtraction and a control circuit that controls the K values of the first and second arithmetic circuits in accordance with the output of the subtraction circuit, a delay time input video signal by the control circuit is provided. a first delay circuit that delays and outputs the signal to the first arithmetic circuit, and a second delay circuit that delays the signal output from the delay time image memory circuit by the control circuit and outputs the signal to the second arithmetic circuit. The delay time generated by the time difference between writing and reading by the memory circuit is (1
(frame period - delay time caused by the control circuit - delay time caused by the first arithmetic circuit).

[Effect]

In the cyclic noise reduction circuit for video signals of the present invention, the delay time caused by the control circuit is compensated for by the first delay circuit and the second delay circuit, and the timing of the signal output from the control circuit and the first calculation are adjusted. The timing of input to the circuit and the timing of input to the second arithmetic circuit match. There is almost no delay time caused by the subtraction circuit and the addition circuit, and the delay time caused by the first arithmetic circuit and the delay time caused by the second arithmetic circuit are almost equal. On the other hand, since the delay time generated by the time difference between writing and reading by the image memory circuit is set to be shorter than one frame period by the sum of the delay time by the control circuit and the delay time by the first arithmetic circuit, the subtraction circuit There is a time difference of one frame period between the two inputs at the input end of the signal.

[0006]

[Examples] The present invention will be explained below with reference to Examples. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The cyclic noise reduction circuit for video signals of this embodiment supplies the input video signal and the output signal from the image memory circuit 10 to the subtraction circuit 5, and subtracts the output signal from the image memory 10 from the input video signal. , a control circuit 6 that controls the value of the coefficient K based on the output signal of the subtraction circuit 5 according to the output of the subtraction circuit 5.
to control the value of the coefficient K. The input video signal is supplied to a delay circuit 7 to delay the video signal by the delay time provided by the control circuit 6. The output from the delay circuit 7 is the input signal (
The signal is supplied to an arithmetic circuit 2 which multiplies the delayed video signal by (1-K) and outputs the delayed video signal by (1-K). The output signal from the image memory circuit 10 is supplied to the delay circuit 8 and delayed by the delay time by the control circuit 6. The output signal from the delay circuit 8 is supplied to the arithmetic circuit 3 which multiplies the input signal by K, and outputs the multiplied signal by K. The output signal from the arithmetic circuit 2 and the output signal from the arithmetic circuit 3 are supplied to an adder circuit 4 and added, and the added output is output as an output signal of a cyclic noise reduction circuit for video signals and is also sent to an image memory circuit 10. and stored in the image memory circuit 10. Here, the image memory circuit 10
The delay time generated by the time difference between writing and reading is set to the time obtained by subtracting the sum of the delay time caused by the control circuit 6 and the delay time caused by the arithmetic circuit 2 from one frame period.

[0007] In this embodiment configured as described above,
The input video signal is delayed by the delay time delay circuit 7 provided by the control circuit 6, supplied to the arithmetic circuit 2, and multiplied by (1-K). The output signal of the image memory circuit 10 is delayed by the delay time delay circuit 8 by the control circuit 6 and then sent to the arithmetic circuit 3.
is supplied and multiplied by K. On the other hand, the output signal of the image memory 10 is subtracted from the input video signal, and the value of K is controlled in the control circuit in accordance with this subtraction output, and the value of K in the calculation circuits 2 and 3 is set respectively. However, there is almost no delay time caused by the subtraction circuit 5, and the timing of the signal output from the control circuit to the arithmetic circuits 2 and 3 coincides with the timing of the input to the first arithmetic circuit and the timing of the input to the second arithmetic circuit.

Further, in the arithmetic circuit 2, the output signal from the delay circuit 7 is multiplied by (1-K), and in the arithmetic circuit 3, the output signal from the delay circuit 8 is multiplied by K, and then added in the adder circuit 4. However, the delay times caused by the arithmetic circuits 2 and 3 are almost equal, and the timings of both signals at the input end of the adder circuit 4 match. The output of the adder circuit 4 is output as a noise reduction output and is also stored in the image memory circuit 10, and the signal read from the image memory circuit 10 is supplied to the subtracter circuit 5 and the delay circuit 8. Here, the delay time generated by writing and reading from the image memory circuit 10 is set to (1 frame period - delay time by control circuit 6 - delay time by arithmetic circuit 2). Further, the delay time caused by the subtraction circuit 5 and the addition circuit 4 is almost negligible and can be ignored. Therefore, there is a period difference of one frame between the two inputs placed at the input terminal of the subtraction circuit 5.
Furthermore, the timings of both inputs at the input end of the adder circuit 4 also match, and an output signal with reduced noise can be obtained from the adder circuit 4. Furthermore, since the delay times caused by the arithmetic circuits 2 and 3 are almost equal, the delay time generated by writing and reading from the image memory circuit 10 is (1
- Frame period - Delay time by control circuit 2 - Arithmetic circuit 3
The same is true even if the delay time is set to

As described above, since the delay circuits 7 and 8 delay the respective input signals by the delay time of the control circuit 6, even if a delay of one sample period or more occurs between the input and output, the noise reduction There is no problem even if the processing time takes one sample period or more, and a cyclic noise reduction circuit for video signals can be configured with elements that operate at a relatively low speed.

0010

As explained above, according to the present invention, the input video signal is multiplied by (1-K), the output from the image memory circuit is multiplied by K, and the signal output from the image memory circuit is converted into the input video signal. A video image in which noise reduction is performed by subtracting from a signal, controlling the value of a coefficient K according to the subtraction output, and adding the video signal multiplied by (1-K) and the output from the image memory circuit multiplied by K. In a signal cyclic noise reduction circuit, a delay time input video signal by a control circuit that controls the value of a coefficient K according to a subtraction output is delayed and multiplied by (1-K), and the output from the image memory circuit is delayed by the delay time. By delaying the time and multiplying it by K, the delay time generated by the time difference between writing and reading by the image memory circuit is (1 frame period -
Since the delay time due to the control circuit - (1-K) times the delay time due to the arithmetic circuit), even if the noise reduction processing time takes more than one sample period, there is a period of one frame period between both inputs at the subtraction input terminal. This has the advantage that the time difference can be set, and the cyclic noise reduction circuit can be configured with elements that operate at a relatively low speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional example.

[Explanation of symbols]

2 Arithmetic circuit 3 Arithmetic circuit 4 Adder circuit 5 Subtraction circuit 6 Control circuit 7 Delay circuit 8 Delay circuit 10 Image memory circuit

Claims (1)

[Claims] Claim 1: An image memory circuit and an input video signal (
1-K) A first arithmetic circuit that multiplies the signal output from the image memory circuit, a second arithmetic circuit that multiplies the signal output from the image memory circuit, and an output that adds the output of the first arithmetic circuit and the output of the second arithmetic circuit. an addition circuit that outputs as a noise reduction output and stores it in the image memory circuit; a subtraction circuit that subtracts the signal output from the image memory circuit from the input video signal; and first and second arithmetic circuits according to the output of the subtraction circuit. In the cyclic noise reduction circuit for video signals, the first delay circuit delays the input video signal by the delay time of the control circuit and outputs it to the first arithmetic circuit; A second delay circuit delays the signal output from the image memory circuit and outputs the delayed signal to the second arithmetic circuit. 1. A cyclic noise reduction circuit for a video signal, characterized in that: period - delay time caused by the control circuit - delay time caused by the first arithmetic circuit.