JPH0442669A - Noise reduction device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise reduction device that uses correlation to reduce noise in a television signal.

[Prior Art] FIG. 3 shows a basic configuration block diagram of a noise reduction circuit that utilizes field/frame correlation of television signals. In FIG. 3, 10 is an input terminal for a signal, 12 is a subtracter, 14 is a limiter that limits the amplitude of the output of the subtracter 12, 24 is a multiplier for coefficients, and 18 is a multiplier 1.
an adder that adds the input signal of the input terminal 10 to the output of the input terminal 6;
20 is an output terminal for a noise-reduced television signal;
2 is a delay circuit that delays the output signal of the output terminal 20 by one frame (or field, the same applies hereinafter).

In FIG. 3, the subtracter 12 subtracts the input signal at the input terminal 10 from the noise reduction-processed output signal delayed by one frame by the delay circuit 16. Limiter 14 is subtracter 1
When the amplitude of the second output is in the range of -L to +L, it is output as is, and outside that range, it is output with the amplitude limited to -L or +L. The multiplier 16 multiplies the output of the limiter 14 by a coefficient K, and the adder 18 multiplies the input signal of the input terminal 10 by the multiplier 1.
Add the outputs of 6. The output of adder 18 is output terminal 20
and is supplied to the delay circuit 22.

The delay circuit 16 and the subtracter 12 provide an interframe difference signal. By multiplying this difference signal by a coefficient K and adding it to the input signal at the input terminal 100 in the adder 18, the amplitude of the inter-frame correlation signal such as noise is ((
1-K) / (1+K)) attenuates to 1/3. The coefficient is called a cyclic coefficient because it determines the feedback amount, ie, the cyclic amount, of the output signal of the output terminal 20, and is set to a constant value in the range of 0≦≦1.

However, if there is a motion component in the input signal to the input terminal 10 due to movement of the subject, etc., if the inter-frame difference signal is directly multiplied by the constant coefficient K, the motion component will also be attenuated. Generally, motion components tend to have large inter-frame difference values, while noise tends to have small difference values, so the limiter 14 is used to change the effective cyclic coefficient K in accordance with the difference value. That is, in the amplitude limiting range -L to +L of the limiter 14, the effective cyclic coefficient is K itself, but outside the limited range, the effective cyclic coefficient becomes zero.

[Problem to be solved by the invention] In order to take a closer look at the noise reduction effect of the circuit shown in Fig. 3,
The input/output characteristics (first quadrant) of the portion consisting of the limiter 14 and the multiplier 16 are shown in FIG. The following two points can be understood from Figure 4. That is, first, the amount of circulation, that is, the degree of noise suppression, changes rapidly between components below the amplitude limit value of the limiter 14 and components exceeding it. Second, all components below the amplitude limit value of the limiter 14 have the same degree of noise suppression regardless of the magnitude of the value.

In the conventional example shown in FIG. 3, when the difference value between the output of the frame delay circuit 22 and the input signal of the input terminal 10 is large, there is a high probability that the difference signal is a motion component, and when the difference value is small, the difference signal The assumption was that there is a high probability that the signal is a noise signal. Based on this premise, the cyclic coefficient should change continuously and smoothly with respect to the difference value, but this has not been the case in the conventional example.

Therefore, an object of the present invention is to provide a Z noise reduction device that solves these problems.

[Means for Solving the Problems] A first subtraction means that calculates a difference value between a delayed signal and an input signal, an amplitude limiting means that limits the amplitude of the difference value, and a predetermined value for the output of the amplitude limiting means. Perform exponentiation processing of
a calculation means for multiplying by a predetermined coefficient, a second subtraction means for subtracting the output of the calculation means from the output of the amplitude limiting means, and an input signal added to the output of the second subtraction means to produce a noise-reduced output. It is characterized by comprising an adding means for outputting a signal.

[Operation] By the above calculation means and second subtraction means, it is possible to obtain a cyclic amount that continuously and smoothly changes with respect to a difference value between pixels (signals) with high correlation.

[Example code] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration block diagram of an embodiment of the present invention. 30 is an input terminal for a television signal whose noise is to be reduced; 32 is a subtracter; 34 is a limiter that limits the amplitude of the output of the subtracter 32; 36 is a terminal with the same sign as the output X of the limiter 34 and whose amplitude is its absolute value n a power calculation circuit that outputs a signal IXI'.
is a subtracter that subtracts the output of the multiplier 38 from the output of the limiter 34; 42 is an adder that adds the output signal of the subtracter 40 to the input signal of the input terminal 30; and 44 is an output terminal for the noise-reduced television signal. , 46 are delay circuits that delay the output signal of the adder 42 by one frame (or field).

The changes in this embodiment with respect to FIG. 3 are circuits 36 and 38.
．． 40, the operation of this part will be mainly explained. The output signal X of the limiter 34 is amplitude-limited to a range of +L to -L, and the exponentiation calculation circuit 36 outputs lx l'·X with respect to this X. For example, if n=2, multiply the absolute value of X by X, and if n=3, simply multiply X by 3.
Multiply times.

The multiplier circuit 38 applies a coefficient (1-
K), and the subtracter 40 subtracts the output of the multiplier 38 from the output X of the limiter 34. Therefore, the output of the subtracter 40 is x-(1-K)Ixl"x = (1-(1-K)IxI")x.

The total input/output characteristics from the limiter 34 to the subtracter 40 are shown in FIGS. 5 and 6 for n=1.2.3, respectively.
As shown in FIG. 7 and FIG. When n=1, the output of the subtracter 40 is Kx, which is the same as in the conventional example of FIG. When n-=2, the output of the subtracter 40 is x-(
1-K) x' (0≦X≦L), and the cyclic coefficient for the component near
K) becomes x.

In this case, as the value of X increases and the probability that the difference value is a motion component increases, the cyclic coefficient gradually decreases. When n=3, the output of the subtracter 40 is x-(1-K
)x” (0≦X≦L), and the cyclic coefficient for the component near
In this case as well, as the value of Note that in any case where n = 1.2.8, if the difference value by the subtracter 32 exceeds the amplitude limit value of the limiter 34, there is no cyclic signal, and the cyclic coefficient of that component is zero. be.

Therefore, by setting an appropriate value of 2 or more as the value of n, it is possible to continuously change the cyclic coefficient in conjunction with the difference value. However, so that the cyclic coefficient (the first derivative of the output of the subtracter 40 of X) does not become smaller than zero,
K, L, and n must be set to satisfy the relationship K≧1−1/(nLa−ri).

FIG. 2 shows a circuit configuration block diagram of another embodiment that can simplify the exponentiation calculation circuit 36 of FIG. 1.

The same components as in FIG. 1 are given the same reference numerals.

An absolute value converting circuit 48 for converting a two's complement code into a sine absolute value code is arranged between the reducer 32 and the limiter 34, and an absolute value converting circuit 48 for converting the sine absolute value code into a two's complement code is arranged between the subtracter 40 and the adder 42. A two's complement circuit 50 for converting into code is provided. Since the absolute value circuit 48 ensures that the output of the limiter 34 is always greater than or equal to 0, the exponentiation circuit 36 simply
All you have to do is calculate. That is, the exponentiation calculation circuit 36 does not need to perform any special calculation even when n is an even number, and can be realized with a simple circuit configuration for any n. The sign of the output signal of subtractor 32 is recovered in two's complement circuit 50.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, the amount of circulation for noise reduction processing is continuously and smoothly determined according to the difference value between pixels (signals) with high correlation. can be changed to

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration block diagram of an embodiment of the present invention, and FIG.
The figure is a circuit configuration block diagram of another embodiment, FIG. 3 is a circuit configuration block diagram of a conventional example, FIG. 4 is a characteristic diagram of the same left value of the frame (or field) of FIG. 3 and the amount of circulation, and FIG. 5 , FIG. 6, and FIG. 7 are characteristic diagrams of the frame (or field) same left division value and the amount of circulation at n=1.2.3 in FIG.

Claims (1)

[Claims] a delay means for delaying an output signal for a predetermined period; a first subtraction means for calculating a difference value between the signal delayed by the delay means and the input signal; an amplitude limiting means for limiting the amplitude of the difference value; a calculation means that performs a predetermined exponentiation process on the output of the limiting means and multiplies it by a predetermined coefficient; a second subtraction means that subtracts the output of the calculation means from the output of the amplitude limitation means; and an output of the second subtraction means. 1. A noise reduction device comprising: an addition means for adding an input signal to an input signal and outputting a noise-reduced output signal.