JPH0423112A - Analog output circuit - Google Patents

Abstract

PURPOSE:To automatically convert the input signal voltage into an output current even after detection of a trouble of a transistor TR and then the changeover of a contact by providing an on-delay timer and a flip-flop. CONSTITUTION:When a 1st TR 4A has a trouble, an output signal B of a trouble detection signal B is set at an H level. If the H level of the signal B lasts longer than the time limit of an on-delay timer 17, an output signal C of the timer 17 is set at an H level. At the same time, an output terminal Q of a flip-flop 19 is also set at an H level and this state is stored. When an output signal D of the flip-flop 19 is set at an H level, a switch 13 works to switch a switch 6 toward a contact (a). Then a DC power supply 8 or a current I flows to a load resistance 7 via a 2nd TR 16 and a resistor 5. Thus the mode can be automatically and smoothly switched to a voltage/current conversion mode by the TR of the other side. As a result, the input signal voltage can be continuously converted into an output current as desired with high reliability and with no intervention of manual operations.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog output circuit that converts an analog input signal voltage into an analog current of a predetermined level and outputs it to a resistive load.

[Conventional technology]

Figure 4 shows a conventional analog output circuit.
1 is an arithmetic unit, 2 is an operational amplifier that receives the input signal voltage V from the arithmetic unit 1 at one input terminal (+ terminal), 3 is a resistor, and 4 is a load circuit for a load circuit controlled by the output of the operational amplifier 2. A transistor and a resistor 5 constitute a voltage-current circuit.

6 is a switch of the switching device 13, 7 is a load resistor connected to the collector of the transistor 4 via the switch 6, and 8 is a DC stabilized power supply device that supplies current to the collector of the transistor 4 via the load resistor 7. A DC power supply supplies the current for driving the current output. The emitter of the transistor 4 and the other input terminal (one terminal) of the operational amplifier 2 are
They are connected by a feedback line Q with a feedback voltage V. Further, 9 is a differential voltage detector for determining the difference between the input signal voltage V and the feedback voltage VF,
The input impedance of each input terminal of this is close to infinity (more than 10 megaohms), and a differential voltage (V-V, ) is output. 10 is an absolute value circuit that takes the absolute value of this differential voltage (vvp), 11 is a voltage setter that outputs a set voltage ΔV, 1
Reference numeral 2 denotes a voltage comparator that compares this set voltage ΔV and the above-mentioned absolute value voltage IVVFI to detect a failure signal.

Note that D is a failure detection circuit. Further, 13 is a switch that receives a failure signal from the voltage comparator 12 and switches the switch 6, and 14 is a variable resistor connected to the load resistor 7 via the switch 6 of the switch 13.

Next, the operation will be explained.

When the input signal voltage V from the arithmetic unit 1 is O volts, the operational amplifier 2 controls the impedance of the transistor 4 so that the feedback voltage VF applied to its input terminal (one terminal) is also O volts. Next, when the input signal voltage V becomes a positive value.

Since the voltage of the above input terminal (+ terminal) is O volts,
Ten potentials are output to the base of the transistor 4 to make it conductive. Therefore, between the collector and emitter of this transistor 4, the switch 6, the load resistance 7. An output current (2) is passed from a DC power source 8 to a load circuit consisting of a resistor 5, and a feedback voltage vF is obtained across the resistor 5. This feedback voltage V is input to the ten terminals of the operational amplifier 2, and the transistor 4 is controlled so that the voltages input to the ten terminals and the one terminal thereof are equal. Here, if the resistance value of the resistor 5 is R, then I=V/R.

In this way, when the circuit is in a normal state, the input signal voltage V
and the feedback voltage V are equal, so the output of the differential voltage detector is 0 volts and the output of the absolute value circuit 10 is also 0 volts. As a result, the output of the voltage comparator 12 becomes low level, and the switch 13 does not operate.

On the other hand, if the transistor 4 fails, the input signal voltage ■ and the feedback voltage ■1 will not be equal.

The output voltage of the absolute value circuit 10 also becomes 1VVpl≠O, and this is input to the voltage comparator 12 together with the set voltage from the voltage setter 11 that serves as a reference for failure determination. And 1
When v-vr l>ΔV, the output becomes high level, a failure is detected, and the switch 13 operates,
The switch 6 changes from the b contact to the a contact. For this reason,
Current ■ flows through the load resistor 7 from the DC current g8. This electric current can be adjusted by a variable resistor 14. Further, FIG. 5 is a characteristic diagram illustrating the relationship between input signal voltage and output current in comparison with a voltage within an allowable range.

[Problem to be solved by the invention]

Since the conventional analog output circuit is configured as described above, when a failure of the transistor 4 is detected and the switch 6 is switched by the changeover device 13, the magnitude of the current flowing through the load resistor 7 can be manually controlled. There were problems such as the need for control by operating the variable resistor 14.

Incidentally, as an approximate conventional technique, there is Japanese Patent Application No. 63-310178.

This invention was made to solve the above-mentioned problems, and it is an analog output that can automatically convert input signal voltage to output current even after a transistor failure is detected and the contact is switched. The purpose is to obtain a circuit.

[Means to solve the problem]

The analog output circuit according to the present invention includes an on-delay timer that delays a failure output signal output by a failure detection circuit that detects a circuit failure for a fixed period of time, and a switch that switches the on-delay timer until a reset input is received based on the output of the on-delay timer. A flip-flop that switches and holds one of the transistors in item 2 and a switch that connects either one of the transistors to the load circuit using the switch based on the output of the flip-flop.

[Effect]

The on-delay timer of the present invention can detect a failure of one transistor with high reliability by eliminating the effects of instantaneous malfunction of the failure detection means, and the flip-flop stores the failure confirmation signal from the on-delay timer and switches the switch. Switching to the other transistor side allows the voltage-to-current conversion operation to continue normally.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, a resistor 3A is connected between the base of a first transistor 4A similar to the above and the output terminal of the operational amplifier 2. In FIG. ]-5 is a resistor, one end of which is connected to the output end of the operational amplifier 2, and the other end connected to the base of the second transistor 16. The collector of the second transistor 16 is connected to the a contact point of the switch 6, and the emitter is connected to one end of the resistor 5 and the emitter of the first transistor 4A. 17 is an on-delay timer whose input terminal is connected to the output terminal of the voltage comparator]2, and the output terminal of the on-delay timer 17 is connected to the flip-flop 1.
It is connected to the set input terminal S of 9. 18 is an initial circuit that generates a reset pulse when the power is turned on, and its output terminal is connected to the reset input terminal R of the flip-flop 19.
It is connected to the. 19 is the above flip-flop,
The output terminal Q of this is connected to the switch 13. Second
The figure is a table showing the operating characteristics of this flip-flop 19.

Note that other parts that are the same as those shown in FIG. 4 are designated by the same reference numerals, and redundant explanation thereof will be omitted.

Next, the operation will be explained with reference to the timing chart shown in FIG.

A is the operation signal of the initial circuit 18, and the reset signal is valid at the ゛H level. B is the failure output signal of the voltage comparator 12, and 6C is the output signal of the on-delay timer 17, which indicates a failure detection at the ``H level'' and becomes the ``H level'' when the 1:00 drive operation is completed. D is the output signal of the flip-flop 19, which becomes the "H" level when the "H" level signal is input to the set input terminal. Now, as shown in FIG. 3, it is time t.

When the control power of the analog output circuit of the present invention is turned on, a set pulse is output from the initial circuit 18 until time t1. Therefore, the flip-flop 19 is reset, its output terminal Q becomes the "L" level, the switch 13 does not operate, and the switch 6 is connected to the b contact side.

In this case, if the first transistor 4A is normal, the load resistor 7. A current is passed through a load circuit consisting of the b contact of the switch 6, the first transistor 4A, and the resistor 5. That is, the input signal voltage phase difference voltage V from the arithmetic unit 1 is converted from a voltage to a current by a voltage-current circuit composed of an operational amplifier 2, a resistor 3A, a first transistor 4A, and a resistor 5.

On the other hand, for example, at time t2, the first transistor 4A fails, or the base, emitter of the first transistor 4A
When a failure occurs in the connection to the collector, a difference occurs between the voltage phase difference voltage (2) generated across the resistor 5 and the input signal voltage V.

When V-VF l>Δ■, the output signal B of the voltage comparator 12 becomes the “H” level, and a failure is detected.

Output signal B becomes ゛H level, and on-delay timer 1
If the ``H level'' is continued for more than the time limit TD of 7 (time t3
), its output signal C becomes the ゛H level. When the output signal C becomes the "H" level, the output terminal Q of the flip-flop 19 also becomes the "H" level, and this state is stored. When the output signal of the flip-flop 19 reaches the "H" level at time t:l, the switch 13 is activated, the switch 6 is switched to the a contact side, and the load resistor 7. A contact of switch 6, second transistor 16. A load circuit is formed by the resistor 5, and a current I is caused to flow from the DC power supply 8 to the load resistor 7 (at time t4
). At this time, the input signal voltage V and the feedback voltage (2) become equal, and the fault is canceled, but the output Q of the flip-flop 19 is stored at the level 'H', and after time t4, the load resistance 7. A contact of switch 6.

Second transistor 16. The load circuit constituted by the resistor 5 continues the voltage-current operation under automatic control.

〔Effect of the invention〕

As described above, according to the present invention, the on-delay timer delays the failure output signal output from the failure detection circuit for a certain period of time, and based on the output of the on-delay timer, the flip-flop switches the above-mentioned switch until a reset input is received. is switched to one of the transistors, and based on the output of this flip-flop, the switch is configured to cause the switch to connect one of the transistors to the load circuit, so that if one of the transistors fails, Even if a voltage-to-current conversion operation occurs, the other transistor can automatically switch to the voltage-to-current conversion operation, and the conversion operation from the desired input signal voltage to the output current can be performed with high reliability and without requiring any manual effort. It has the effect of giving you something that you can continue without.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an analog output circuit according to an embodiment of the present invention, FIG. 2 is a table of operating characteristics of the flip-flop in FIG. 1, and FIG. 3 is a timing diagram showing signals of various parts of the circuit in FIG. 1. 4 is a block diagram showing a conventional analog output circuit, and FIG. 5 is an input signal voltage-output current characteristic diagram in FIG. 4. 2 is an operational amplifier, 4A, 16 is a transistor, 6 is a switch, 7 is a load resistor, 8 is a DC power supply (DC stabilized power supply), 13 is a switch, 17 is an on-delay timer, 19
is a flip-flop. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation 1---=-3 Fig.

Claims (1)

[Claims] an operational amplifier that receives an input signal voltage at one input terminal and controls two transistors connected to a DC power source via a load resistor and a switch; A resistor that converts the output current flowing through the load circuit into a voltage and inputs it as feedback to the other input terminal of the operational amplifier, and a fault that detects a circuit failure based on the feedback voltage obtained from this resistor and the input signal voltage. A detection circuit, an on-delay timer that delays the fault output signal output by the fault detection circuit for a fixed period of time, and a flip-flop that switches and holds the switch to one of the transistors until a reset input is received based on the output of the on-delay timer. and a switch for connecting either one of the transistors to the load circuit using the switch based on the output of the flip-flop.