JPH0423128A - Microprogram controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Example (a) An Embodiment of the Present Invention (Figs. 2 to 3) Fig. 4) (b) Other embodiments of the present invention (Fig. 5) Effects of the invention [Summary] Improvement of a microprogram control device that controls a microprogram that is a collection of microinstructions that subdivide the command operations of a computer. Regarding this, even if the microprogram has a large number of complicated conditional branches, it is possible to minimize the provision of steps with the same content in the control storage section, thereby achieving efficient use of the control storage section and higher functionality of the device. The object of the present invention is to provide a microprogram control device, which includes a control storage section that stores a microprogram, a micro output latch circuit that holds micro instructions read from the control storage section, and a conditional branch in the micro output latch circuit. A branch condition selection circuit that selects branch control information based on the selection specification of the conditional branch microinstruction when the instructing conditional branch microinstruction is held; and branch control information selected by the branch condition selection circuit. a branch address selection circuit that selects a first or second field in the conditional branch microinstruction based on the conditional branch microinstruction, and a microaddress generation circuit that generates a microaddress for accessing the control storage section, The first field of the branch microinstruction includes a first base address for generating a branch address when the condition is met, and the second field includes a second base address for generating a branch address when the condition is not met. , and the microaddress generation circuit uses the address from which the conditional branch microinstruction was read and the first or second base address selected by the branch address selection circuit, It is designed to generate a branch destination address.

[Industrial application field]

The present invention relates to an improvement in a microprogram control device that controls a microprogram, which is a collection of microinstructions that subdivide the instruction operations of a computer.

BACKGROUND ART In recent years, as computers have become more sophisticated, microcomputers have adopted a method of controlling operations using a microprogram method. This microprogram type computer has a simple structure, so it is generally inexpensive, but because it has a general structure that can withstand improvements and changes, it is not necessarily suitable for specific specifications. Not the best hardware.

In particular, in order for the microprogram to perform highly functional processing, there are many complex conditional branches, etc. (as a result, the microprogram stored in the control storage unit becomes enormous, and the capacity of the control storage unit must be increased. What is needed is a microprogram controller that does not require this large amount of control storage.

[Conventional technology]

Conventionally, as this type of microprogram control device, the sixth
There was something shown in the figure. FIG. 6 is a block diagram of the address control section of the conventional device.

In the figure, the conventional microprogram control device has a microprogram R for storing microprograms.
A control storage unit 1 formed of an OM, a micro output latch circuit 2 that holds microinstructions of a microprogram read from the control storage unit 1, and a selection designation in the microinstructions held in the micro output latch circuit 2. C of
Select one of the branch control information bc - bc7 output from the status register 8 on the arithmetic control unit side based on the contents indicated in the C field (condition field), and output the selected branch condition input value be. a microaddress generation circuit 5 that generates a microaddress based on a part of the microinstruction of the microoutput latch circuit 2 and the branching condition input value bC of the branching condition selection circuit 3; The configuration includes an address register 6 that stores the microaddress of the generation circuit 5.

Each microinstruction stored in the control storage unit 1 includes an MD field indicating whether it is a conditional branch or an unconditional branch, a CC field indicating the contents of the selection specification, and a BA field (base address field) indicating the branch destination address at the time of a conditional branch. ) for controlling the execution address of the next microinstruction, and a CT for controlling each operation of the microinstruction.
field (control field).

Next, based on the above configuration, the operation of the conventional device is shown in Fig. 7 (A).
, (B). FIG. 7(A) shows MD (mode), CC, and BA fields (address designation fields) for controlling the execution address of the next microinstruction. In addition, (B) of the same figure shows 8 bft of the microaddress generated by the microaddress generation circuit 5.
A configuration example is shown.

First, a microinstruction read from the control storage section 1 is held in the latch circuit 2. The branch condition circuit 3 and the microaddress generation circuit 5 each operate according to the contents of the MD field of this held microinstruction.

If the contents of the MD field are unconditional branch "1", all bits constituting the next microaddress are specified in the MD field for specifying the microaddress,
The content MA is directly selected by the 7-micro address generation circuit 5 and stored in the address register 6. Based on the contents of the microaddress stored in the address register 6, the microinstruction to be executed next is read from the control storage section 1.

When the content of the MD field is conditional branch "0", the branch condition selection circuit 3 selects the branch condition output from the status register on the arithmetic control unit side based on the content of the CC field to state the device. A branch condition input value bc representing the value bc is output to the microaddress generation circuit 5.

Note that the branch condition input value be is specifically a 1-bit flag stored in the status register 8. Since CC is 3 bits, there are eight flags bCO to bc7 in status register 8, and one of the eight flags is selected according to the value of CC. This selected branch condition input value bc is input to the microaddress generation circuit 5. At the time of conditional branching, the jump destination changes depending on whether this flag is "1" or "10".

The micro address generation circuit 5 generates a branch condition input value bc of the selected condition (such as a carry indicating the state of the device).
A part of the microaddress is generated from the contents of the BA field and the contents of the BA field, and is stored in a part of the address register 6. For bits in this address register 6 that use the contents (MAR) of the previous microaddress as they are, the previous data MAR is held as is. This held previous data MARs-7 and part of the microaddress generated by the microaddress generation circuit 5 (branch destination address BA5-).

and branch condition input value be) will be stored in the address register 6.

In this way, in the case of a conditional branch, the addresses at which the branch can be taken are limited and realized using bit information of the same length (8 bits) as in the case of an unconditional branch. Therefore, the microaddress of 8bjt is the MAR of the contents of the previous microaddress.
The field is 2 bits, part of the BA field indicating the branch destination address is 5 bits, and the branch condition input value bc (flag in the status register) indicates the device status.
The MAR field is composed of 1 bit;
The next execution address was generated using part of the BA field and the input value bc.

[Problem to be solved by the invention]

Conventional microprogram control devices are configured to take the branch condition input value bc (flag value) itself as an address as described above, so in the case of conditional branching, the condition specified by the branch condition input value be There is a problem that conditional branching is restricted unless the branch destination addresses for conditions established (corresponding to flag = “1”) and conditions not satisfied (corresponding to flag = “0”) exist as a set that differs by only a specific 1 bit. Was. Therefore, even if you want to conditionally branch from one address to another address, if you want to change the behavior after the condition is satisfied or not, write the same content to another address and Therefore, if a microprogram uses many complex conditional branches to perform sophisticated processing, many microinstructions with the same content are required, and the control memory This poses a problem in that the number of steps of the microprogram stored in the control storage section increases, deteriorating the storage efficiency of the control storage section.

The present invention has been made to solve the above problem, and even in a microprogram having many complex conditional branches, the provision of steps with the same content in the control storage unit is suppressed as much as possible, thereby improving the efficiency of the control storage unit. The object of the present invention is to provide a microprogram control device that can be used for a variety of purposes and improve the functionality of the device.

Means to solve problem 1] FIG. 1 shows a diagram explaining the principle of the present invention.

In the figure, the microprogram control device according to the present invention includes a control storage section 1 that stores a microprogram, a micro output latch circuit 2 that holds micro instructions read from the control storage section 1, and the micro output latch circuit. 2, when a conditional branch microinstruction instructing a conditional branch is held, a branch condition selection circuit 3 that selects branch control information bc based on the selection designation of the conditional branch microinstruction; and the branch condition selection circuit 3. a branch address selection circuit 4 for selecting the first or second field A or B in the conditional branch microinstruction based on the branch control information be selected by the circuit 3; a micro-address generation circuit 5 for generating a micro-address; the first field of the conditional branch micro-instruction includes a first base address for generating a branch address when the condition is met; The field contains a second base address for generating a branch address when the condition is not met, and the microaddress generation circuit 5 selects the address from which the conditional branch microinstruction was read and the branch address selection circuit. The branch destination address is generated using the first or second base address selected in the above.

[Effect]

In the present invention, a conditional branch micro-instruction is provided with first and second fields ASB for specifying each branch address when the branch condition is met and when the condition is not met using multiple bit information,
The branch address selection circuit 5 selects either the first field A or the second field B based on the branch control information bc selected based on the contents of the selection specification of the conditional branch microinstruction, and the information is transferred to the next field. By using it as part of the address of the microinstruction to be executed, the first or second field ASB specified by the microinstruction can be used as part of the address of the microinstruction to be executed, regardless of the branch control information bc selected in the selection specification of the conditional branch microinstruction. The information of any plurality of bits of the branch address becomes part of the address of the next microinstruction to be executed.

As a result, if the specified number of bits is N, then 2N
Within these addresses, you can freely set the branch destination address when the conditional branch is taken or not taken.

Therefore, if you want to make a conditional branch from an arbitrary address to the same address, and you change the behavior after the condition is met or not, you will have 2N-1 addresses and conditional branches for one address. Therefore, 2-1 microinstructions can be shared.

〔Example〕

(a) One Embodiment of the Present Invention An embodiment of the present invention will be described below with reference to FIGS. 2 to 4. FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram showing an aspect of an address specifying portion of a microinstruction, and FIG. 4 is a detailed circuit diagram of the microaddress generation circuit shown in FIG.

In each of the above figures, the microprogram control device according to this embodiment is composed of an address control section and an arithmetic control section, and the address control section is connected to the control storage section 1 and the micro output latch of the conventional device (shown in FIG. 6). A circuit 2, a branch condition selection circuit 3, a micro address generation circuit 5, and an address register 6 are commonly provided, and in addition to this configuration, the micro output latch circuit 2 The first field person (hereinafter referred to as A) in the conditional branch microinstruction stored in the microinstruction
This configuration includes a branch address selection circuit 4 that selects a second field B (hereinafter referred to as B field).

The microinstruction stored in the control storage unit 1 includes, in addition to the MD field, CC field, and CT field, an A field that specifies the branch address when the condition is met using multi-bit information in the case of a conditional branch, and an A field that specifies the branch address when the condition is met using multi-bit information. It is formed with a B field that specifies a branch address using multiple bit information.

The branch address selection circuit 4 determines when a condition is satisfied in the micro output latch circuit 2 based on the CC field which is the content of the selection designation of the micro instruction held in the micro output latch circuit 2.

The configuration is such that either the A or B field that specifies the branch address when the condition is not met is selected, and the selected A (or B) field is output to the microaddress generation circuit 5.

Furthermore, the microaddress generation circuit 5 in FIG.
MA field MA for specifying a micro-address indicating the next execution address at the time of an unconditional branch in the micro-instruction held in the micro-output latch circuit 2; and factors other than the micro-instruction (for example, a user's instruction,
a first selection circuit 51 that selects the next execution address created based on the state of the arithmetic control unit, etc., based on the contents of an MD field indicating whether it is a conditional branch or an unconditional branch;
The MA field rule B selected by the selection circuit 51 of
) is selected based on the contents of the MD field.
The configuration includes a selection circuit 52.

Next, the operation of this embodiment based on the above configuration will be explained.

First, in the normal operation of sequentially reading out microinstructions in a microprogram (-), the microinstructions are read out from the control storage section 1 constituted by a micro ROM and held in the micro output latch circuit 2. The micro-instruction of this micro-output latch circuit 2 has an MA field (MD field) for controlling the execution address of the next micro-instruction.
CC field, A field, B field) and a CT field for each calculation control, and the M
The MD field, CC field, A field, and B field of the A field are output to the address control section, and the CT field is output to the arithmetic control section.

Depending on the contents of the MA field, the branch is divided into an unconditional branch or a conditional branch, and operates as follows.

■In the case of an unconditional branch This unconditional branch (when the MD field is "1")
The CC field, A field, and B field become the MA field that specifies the next execution field (the third
(see figure (A)). In FIG. 3(A) rMD=IJ, MA in the MA field indicating the next execution address is selected from the branch mode of the microinstruction.

This is stored in the address output register 6 as a field for controlling the execution address of the selected next microinstruction (see Figure 3 (B)), and the next microinstruction to be executed is controlled based on the stored contents. It will be read from the storage unit 1. After that, this process is repeated for unconditional branches.

■For conditional branch Conditional branch (when the MD field is “0”)
Branch control information b c -b C7 output from the status register 8 on the arithmetic control unit side based on the selection designation contents shown in the C field is selected by the branch condition selection circuit 3, and this selection result is sent to the device (arithmetic control unit ) is output as a branch condition input value be representing the state on the side. This branch condition input value bc is input to the branch address selection circuit 4, and this branch address selection circuit 4 receives the branch condition input value b
Based on c, select either field A, which is 3-bit information when the condition is met, or field B, which is 3-bit information when the condition is not met.

Based on this selected information (A field A or -OB field B), only a plurality of arbitrary bits of the address register 6 are rewritten. In this way, an address with different values of any plurality of bits from the current microaddress is identified. The microinstruction to be executed next based on the specified microaddress is read from the control storage section 1 and held in the microoutput latch circuit 2. In the case of a conditional branch, the above operation will be repeated.

Note that when the normal operation of the unconditional branch and conditional branch is completed and the transition is made to the microprogram, the output from the instruction register 12 is the first one of the microaddress generation circuit 5.
The first microaddress of the next microprogram is generated by the microaddress generation circuit 5, and after this generated microaddress is stored in the address register 6, it is input to the selection circuit 51 (see FIG. 4). It will be read from 1.

Furthermore, the contents of the CT field for the arithmetic control unit among the microinstructions held in the micro output latch circuit 2 are input to the AlO2 of the arithmetic control unit, the decoder of the general-purpose register 9, and the program counter 10, respectively.

The ALU 7 performs an arithmetic operation based on the contents of the CT field, stores the result of the arithmetic operation in the general-purpose register, and outputs the status of the arithmetic operation to the status register 8. The contents of this status register 8, such as carry, overflow, etc., are determined by the branch condition selection circuit 3.
and is selected by the branch condition selection circuit 3 based on the contents of the CC field.

(b) Another embodiment of the present invention FIG. 5 shows an aspect diagram of an address specifying part of a microinstruction of a device according to another embodiment, and (A) of the same figure shows an address field,
(B) of the same figure shows each microaddress.

In the embodiment mentioned above, the fields of the microinstruction for controlling the execution address of the next microinstruction include the MD field that specifies whether the branch is conditional or unconditional, the CC field that specifies the branch condition, and the field that specifies the branch condition when the condition is met. an A field that specifies arbitrary multiple bit information of the branch address of;
Although the B field specifies information of a plurality of arbitrary bits of the branch address when the condition is not met, in addition to these, it is also possible to configure as shown in FIG.

That is, in addition to the above embodiment, a third field AB may be provided that specifies information on some bits of the branch address regardless of whether the condition is satisfied or not at the time of conditional branching. By providing a third field AB of this part of common bit information, in the case of a conditional branch, the information in the third field AB can be rewritten to any bit of the address register 6, regardless of the condition. Good too.

In this case, in the microinstruction, the third field AB is shared by the MA field indicating the branch address at the time of an unconditional branch, so the bit information of the address of the MA field corresponding to the bit position of the third field AB is the same bit. In this case, the scale of the hardware is the same as in the above-mentioned embodiment, and it is only necessary to increase the number of bits to be rewritten in the address register 6. In other words, this can be achieved only by changing the connections.

〔Effect of the invention〕

As explained above, in the present invention, first and second fields A and B are provided in the conditional branch micro-instruction to specify each branch address when the branch condition is met and when the condition is not met using multiple bit information. The branch address selection circuit selects either the first field A or the second field B information based on the control information bC selected based on the content of the branch microinstruction selection specification, and the information is used in the next microinstruction to be executed. Because it is configured to be used as part of the address, regardless of the control information bc selected in the selection specification of the conditional branch microinstruction, the information in the first or second field A or B specified by the microinstruction is Since the information of any multiple bits of the branch address becomes part of the address of the next microinstruction to be executed and can be shared, it is important to make every effort to create steps with the same content in the microprograms stored in the control memory. It has the effect of being controllable.

Furthermore, the number of microinstructions in the microprogram is reduced, which improves the storage efficiency of the control storage unit, and has the effect that a highly functional microcomputer can be provided at low cost.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. FIG. 4 is a detailed circuit configuration diagram of the address generation circuit shown in FIG. 2. FIG. 6 is a block diagram of the address control section of the conventional device. FIG. ) is a diagram showing an address designation field, and (B) of the same figure shows a microaddress. 1... Control storage unit 2... Micro output latch circuit 3... Branch condition selection circuit 4... Branch address selection circuit 5... Micro address generation circuit 6... Address register 7... ALU 8...Status register 1...First selection circuit 2...Second selection circuit

Claims (1)

[Claims] 1. A control storage unit (1) that stores a microprogram, a micro output latch circuit (2) that holds micro instructions read from the control storage unit (1), and the micro output latch When a conditional branch microinstruction that instructs circuit (2) to perform a conditional branch is held, branch control information (bc_n
); and a branch condition selection circuit (3) that selects the first or second field (A) in the conditional branch microinstruction based on the branch control information (bc_n) selected by the branch condition selection circuit (3). or B); and a microaddress generation circuit (5) that generates a microaddress for accessing the control storage section (1), The first field contains a first base address for generating a branch address when the condition is met, and the second field contains a second base address for generating a branch address when the condition is not met. The micro address generation circuit (5
) generates a branch destination address using the address from which the conditional branch microinstruction was read and the first or second base address selected by the branch address selection circuit. Microprogram control device. 2. The conditional branch microinstruction has a third field (AB) including a third base address that is shared for generating a branch address when the condition is met or not met, and the microaddress generation circuit (5) determines the branch destination address using the address from which the conditional branch microinstruction was read, the first or second base address selected by the branch address selection circuit (4), and the third base address. 2. The microprogram control device according to claim 1, wherein the microprogram control device generates the program. 3. The microprogram control device according to claim 1, wherein the first and second fields (A, B) of the conditional branch microinstruction stored in the control storage section are specified by a plurality of bit information.