JPH0423324A - Manufacture of soi substrate - Google Patents

Manufacture of soi substrate

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Publication number
JPH0423324A
JPH0423324A JP12381490A JP12381490A JPH0423324A JP H0423324 A JPH0423324 A JP H0423324A JP 12381490 A JP12381490 A JP 12381490A JP 12381490 A JP12381490 A JP 12381490A JP H0423324 A JPH0423324 A JP H0423324A
Authority
JP
Japan
Prior art keywords
wafer
thin film
thickness
pasted
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12381490A
Other languages
Japanese (ja)
Inventor
Toru Miyayasu
宮保 徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12381490A priority Critical patent/JPH0423324A/en
Publication of JPH0423324A publication Critical patent/JPH0423324A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To obtain a pasted SOI substrate whose irregularity in a thickness is extremely small and which is provided with a thin element substrate by a method wherein the mirror-polished face of a second Si wafer is pasted on a first Si wafer having a uniform thickness, the second Si wafer is ground to form a thin film of the second Si wafer, an oxide film is formed on the thin film, a third Si wafer is pasted and, after that, the third Si wafer is stripped off and removed. CONSTITUTION:The following are prepared: a first Si wafer 1 whose irregularity TTV in a thickness inside the wafer face is 0.5mum or lower; and a second Si wafer 2 whose surface has been mirror-polished. The mirror-surface of the Si wafer 2 is pasted on the Si wafer 1 in such a way that it is not stripped off during a grinding process of the Si wafer 2 and adjusted to a strength so as to be stripped off when it is stripped off finally. In addition, the Si wafer 2 is ground from a face opposite to the pasted face; and the Si wafer 2 is worked to be a thin film 3 having a thickness of 0.7mum. Then, the thin film 3 is oxidized at a low temperature; and an oxide film 4 is formed. An Si wafer 5 is used as a third Si wafer; it is pasted on the oxide film 4; and after that, the Si wafer 1 is stripped off from the pasted face of the Si wafer 2 (the thin film). Thereby, it is possible to obtain an SOI substrate which uses the Si wafer 5 as a support substrate and which uses the thin film 3 as an element substrate.

Description

【発明の詳細な説明】 (概要〕 Sol基板の製造方法に係り、特に張り合わせSOI基
板の製造方法に関し 厚さが小さく且つ均一な厚さの素子基板を有する張り合
わせSO■基板の提供を目的とし。
DETAILED DESCRIPTION OF THE INVENTION (Summary) The present invention relates to a method of manufacturing a Sol substrate, particularly a method of manufacturing a laminated SOI substrate, and aims to provide a laminated SOI substrate having an element substrate with a small and uniform thickness.

均一な厚さを有する第1のSiウェハーに第2のSiウ
ェハーの鏡面研磨された面を張り合わせた後、第2のS
iウェハーを研削して第2のSiウェハーの薄膜を形成
する工程と、前記薄膜を酸化して、前記薄膜表面に酸化
膜を形成する工程と前記酸化膜に第3のSiウェハーを
張り合わせた後、前記第1のSiウェハーを剥がして除
去する工程とを有するSOI基板の製造方法により構成
する。
After bonding the mirror-polished surface of the second Si wafer to the first Si wafer having a uniform thickness, the second Si wafer is
A step of grinding the i-wafer to form a thin film of a second Si wafer, a step of oxidizing the thin film to form an oxide film on the surface of the thin film, and a step of bonding a third Si wafer to the oxide film. , and a step of peeling off and removing the first Si wafer.

また、均一な厚さを有する第1のSiウェハーに第2の
Siウェハーの鏡面研磨された面を張り合わせた後、第
2のSiウェハーを研削して第2のSiウェハーの1嗅
を形成する工程と、前記薄膜に1表面に酸化膜の形成さ
れた第3のSiウェハーの表面を張り合わせた後、前記
第1の34ウエハーを剥がして除去する工程とを有する
SOI基板の製造方法により構成する。
In addition, after bonding the mirror-polished surface of the second Si wafer to the first Si wafer having a uniform thickness, the second Si wafer is ground to form one layer of the second Si wafer. and a step of laminating the surface of a third Si wafer having an oxide film formed on one surface on the thin film, and then peeling off and removing the first 34 wafers. .

〔産業上の利用分野〕[Industrial application field]

本発明はSol基板の製造方法に係り、特に張り合わせ
Sol基板の製造方法に関する。
The present invention relates to a method for manufacturing a Sol substrate, and particularly to a method for manufacturing a bonded Sol substrate.

Sol基板は素子特性や素子間分離の点でバルク基板よ
りすぐれており、その中でもバルクの結晶性が活かせる
張り合わせSOI基板が注目されている。さらに、近年
ではSi活性層の膜厚の面内ばらつきが0.5μm以下
の均一なSi活性層をもつSO■基板が注目されている
Sol substrates are superior to bulk substrates in terms of element characteristics and isolation between elements, and among them, bonded SOI substrates that take advantage of bulk crystallinity are attracting attention. Furthermore, in recent years, SO2 substrates having a uniform Si active layer with an in-plane thickness variation of 0.5 μm or less have been attracting attention.

〔従来の技術]。[Conventional technology].

第3図(a)乃至(c)は張り合わせSol基板を製造
する従来の工程を説明するための断面図である。
FIGS. 3(a) to 3(c) are cross-sectional views for explaining the conventional process of manufacturing a bonded Sol substrate.

まず2表面に酸化膜1aの形成された第1のSiウェハ
ー1と3表面に酸化tPiJ2aの形成された第2のS
iウェハー2の酸化膜同志を向かい合わせる(第3図(
a)参照)。
First, a first Si wafer 1 with an oxide film 1a formed on two surfaces, and a second Si wafer 1 with an oxide tPiJ2a formed on the third surface.
The oxide films of i-wafer 2 are faced to each other (Fig. 3 (
a)).

第1のSiウェハー1と第2のSiウェハー2を張り合
わせ、アニールにより両者の接合を完全にする。酸化膜
1aと酸化膜2aは酸化膜4を形成する(第3図(b)
参照)。
A first Si wafer 1 and a second Si wafer 2 are pasted together, and the bonding between them is completed by annealing. The oxide film 1a and the oxide film 2a form an oxide film 4 (FIG. 3(b))
reference).

第1のSiウェハー1を研削・研磨して薄膜化して薄膜
3を形成する(第3図(c)参照)。
The first Si wafer 1 is ground and polished to form a thin film 3 (see FIG. 3(c)).

このようにして、薄膜3を素子基板(活性層)。In this way, the thin film 3 is formed into an element substrate (active layer).

第2のSiウェハー2を支持基板とするSol基板が得
られる。
A Sol substrate using the second Si wafer 2 as a support substrate is obtained.

第4図(a)乃至(c)は従来の問題点を説明するため
の断面図である。
FIGS. 4(a) to 4(c) are sectional views for explaining conventional problems.

まず、第1のSiウェハー1と第2のSiウェハー2に
は、第4図(a)に模式的に示すように厚さのばらつき
がある。
First, the first Si wafer 1 and the second Si wafer 2 have variations in thickness, as schematically shown in FIG. 4(a).

第1のSiウェハー1と第2のSiウェハー2を張り合
わせ、第1のSiウェハー1を研削して薄膜化すると、
第2のSiウェハー2の厚さのばらつきに対応して薄膜
3にも厚さのばらつきを生じる。この時、研削盤のくせ
による厚さのばらつきも加わる。薄膜3の表面には研削
加工によるダメージ層1bが存在している(第4図(b
))。
When the first Si wafer 1 and the second Si wafer 2 are bonded together and the first Si wafer 1 is ground to become a thin film,
Corresponding to variations in the thickness of the second Si wafer 2, variations in the thickness of the thin film 3 also occur. At this time, variations in thickness due to the habits of the grinding machine are also added. There is a damaged layer 1b on the surface of the thin film 3 due to the grinding process (see Fig. 4(b)).
)).

次にメカノケミカル研磨によりダメージ層1bを除去す
るとともに、研削による面荒れも除去し表面を平滑にす
る。しかし、この時ウェハー面内で除去される量は必ず
しも一様でなく、薄膜3の厚さに、ばらつきがさらに加
わる (第4図(C))。
Next, the damaged layer 1b is removed by mechanochemical polishing, and the surface roughness caused by the grinding is also removed to make the surface smooth. However, at this time, the amount removed within the wafer surface is not necessarily uniform, and further variations are added to the thickness of the thin film 3 (FIG. 4(C)).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従って、従来の張り合わせSOI基板では、支持基板と
なる第2のSiウェハー2の厚さのばらつきと、研削に
より生じる厚さのばらつきと、メカノケミカル研磨によ
る厚さのばらつきが加算され、素子基板(活性層)とな
る薄11!3の厚さのばらつきが大きくなる。
Therefore, in the conventional bonded SOI substrate, the thickness variations of the second Si wafer 2 serving as the supporting substrate, the thickness variations caused by grinding, and the thickness variations due to mechanochemical polishing are added, and the element substrate ( The variation in the thickness of the thin layer 11!3 which becomes the active layer becomes large.

未発明は、上記の問題に鑑み、厚さばらつきの極めて小
さい、しかも薄い素子基板(活性層)を有する張り合わ
せS○1基板を実現する製造方法を提供するものである
In view of the above problems, the present invention provides a manufacturing method for realizing a laminated S○1 substrate having extremely small variation in thickness and having a thin element substrate (active layer).

〔課題を解決するための手段〕[Means to solve the problem]

第1図(a)乃至(e)、第2図(a)乃至(e)は、
それぞれ、未発明の実施例I、実施例Hの工程を説明す
るための断面図である。
Figures 1 (a) to (e) and Figures 2 (a) to (e) are
FIG. 3 is a cross-sectional view for explaining the steps of uninvented Example I and Example H, respectively.

上記課題は、均一な厚さを有する第1のSiウェハー1
に第2のSiウェハー2の鏡面研磨された面を張り合わ
せた後、第2のSiウェハー2を研削して第2のSiウ
ェハーの1摸3を形成する工程と、前記薄膜3を酸化し
て、前記薄膜3表面に酸化膜4を形成する工程と、前記
酸化膜4に第3のSiウェハー5を張り合わせた後、前
記第1のSiウェハー1を剥がして除去する工程とを有
するSOI基板の製造方法によって解決される。
The above problem is solved by the first Si wafer 1 having a uniform thickness.
A step of bonding the mirror-polished surface of the second Si wafer 2 to the substrate, and then grinding the second Si wafer 2 to form a copy 3 of the second Si wafer, and oxidizing the thin film 3. , an SOI substrate comprising the steps of forming an oxide film 4 on the surface of the thin film 3, and bonding a third Si wafer 5 to the oxide film 4, and then peeling off and removing the first Si wafer 1. The problem is solved by the manufacturing method.

また、均一な厚さを有する第1のSiウェハー1に第2
の31ウエハー2の鏡面研磨された面を張り合わせた後
、第2のSiウェハー2を研削して第2のSiウェハー
の1嘆3を形成する工程と前記薄膜3に1表面に酸化膜
4の形成された第3のSiウェハー5の表面を張り合わ
せた後、前記第1のSiウェハー1を剥がして除去する
工程とを有するSOI基板の製造方法によって解決され
る。
In addition, a second Si wafer 1 having a uniform thickness is
After bonding the mirror-polished surfaces of the 31 wafers 2 together, a step of grinding the second Si wafer 2 to form a second Si wafer 3 and forming an oxide film 4 on one surface of the thin film 3 is performed. The problem is solved by a method for manufacturing an SOI substrate, which includes a step of bonding the surfaces of the third Si wafer 5 formed and then peeling off and removing the first Si wafer 1.

〔作用〕[Effect]

本発明では、第1のSiウェハー1は均一な厚さをもっ
ているので、将来素子基板となる第2のSiウェハー2
が例え均一な厚さを有していないとしても、それを第1
のSiウェハー1に張り合わせて研削し薄膜化すると、
薄膜3は第1のSiウェハー1を基準として形成される
ので、薄膜3の厚さは均一となる。
In the present invention, since the first Si wafer 1 has a uniform thickness, the second Si wafer 2, which will become an element substrate in the future,
Even if the thickness is not uniform, it is
When bonded to Si wafer 1 and ground to make a thin film,
Since the thin film 3 is formed using the first Si wafer 1 as a reference, the thickness of the thin film 3 is uniform.

第1のSiウェハー1を均一な厚さに加工する研削と第
2のSiウェハー2を研削して薄膜化する研削に同一の
研削盤を使用すれば、第1のSiウェハー1と第2のS
iウェハー2は研削盤から同し影響を受けるから、研削
盤のくせに起因する厚さのばらつきが現れない。
If the same grinding machine is used for grinding the first Si wafer 1 to a uniform thickness and grinding the second Si wafer 2 to form a thin film, S
Since the i-wafer 2 is similarly affected by the grinder, variations in thickness due to the habit of the grinder do not appear.

また、薄膜3を第3のSiウェハー5の表面に張り合わ
せた後、第1のSiウェハー1を剥がして除去すれば、
第2のSiウェハー2の張り合わせ面は鏡面研磨された
面であるから、厚さにばらつきを生じるようなメカノケ
ミカル研磨の必要はない。
Furthermore, if the thin film 3 is attached to the surface of the third Si wafer 5 and then the first Si wafer 1 is peeled off and removed,
Since the bonding surface of the second Si wafer 2 is a mirror-polished surface, there is no need for mechanochemical polishing that would cause variations in thickness.

〔実施例] 第1図(a)乃至(e)は実施例■の工程を説明するた
めの断面図であり、以下、これらの図を参照しながら説
明する。
[Example] FIGS. 1(a) to 1(e) are cross-sectional views for explaining the steps of Example (2), and the following description will be made with reference to these figures.

第1図(a)参照 ウェハ面内の厚みばらつきT T V (TotalT
hickness Variation)が2〜4μm
程度の市販の6インチSiウェハを高精度平面研削装置
を用いて研削し、ウェハ面内の厚みばらつきTTVが0
.5μm以下の第1のSiウェハ1を準備する。
Refer to Fig. 1(a) In-plane thickness variation T T V (Total T
thickness variation) is 2 to 4 μm
A commercially available 6-inch Si wafer of about
.. A first Si wafer 1 with a thickness of 5 μm or less is prepared.

さらに、市販の6インチSiウェハの表面を鏡面研磨し
た第2のSiウェハ2を準備する。
Furthermore, a second Si wafer 2 is prepared by mirror polishing the surface of a commercially available 6-inch Si wafer.

第1のSiウェハ1に第2のSiウェハ2の鏡面を張り
合わす。張り合わせは次の第2のSiウェハ2の研削工
程で剥がれることな(、シかも最後に剥がす時剥がれる
強さに調整して張り合わせる。即ち、Siウェハーの張
り合わせ面の面粗さと張り合わせの温度を調節し、張り
合わせ強度を約25 kg/cm”とした。
The mirror surface of the second Si wafer 2 is bonded to the first Si wafer 1. The bonding will not come off in the next grinding process of the second Si wafer 2.The bonding strength is adjusted so that it will peel off when it is finally removed.In other words, the surface roughness of the bonding surface of the Si wafer and the bonding temperature The bonding strength was adjusted to approximately 25 kg/cm.

第1図(b)参照 第1のSiウェハ1の準備に使用した高精度平面研削装
置を用いて、第2のSiウェハ2を張り合わせ面と反対
側の面から研削し、第2のSiウェハ2を厚さ0.7μ
mの薄膜3に加工した。第1のSiウェハ1と薄膜3を
合わせたTTVは。
Refer to FIG. 1(b) Using the high-precision surface grinding device used to prepare the first Si wafer 1, the second Si wafer 2 is ground from the surface opposite to the bonding surface, and the second Si wafer 2 is 2 with a thickness of 0.7μ
It was processed into a thin film 3 of m. The TTV is the combination of the first Si wafer 1 and the thin film 3.

0.3μmであり、薄膜3のTTVは0.1μmであっ
た。
The TTV of the thin film 3 was 0.1 μm.

第1図(c)参照 薄膜3を低温で酸化して2表面に厚さ0.1 μmの酸
化膜4を形成した。
The thin film 3 referred to in FIG. 1(c) was oxidized at low temperature to form an oxide film 4 with a thickness of 0.1 μm on the 2 surface.

第1図(d)参照 市販の6インチSiウェハを第3のSiウェハー5とし
、それと酸化膜4を張り合わせる。張り合わせ時に温度
を1000°Cとし、また、静電圧力を加え、張り合わ
せ強度が約500 kg/cm2となるようにした。
Referring to FIG. 1(d), a commercially available 6-inch Si wafer is used as the third Si wafer 5, and the oxide film 4 is bonded thereto. At the time of lamination, the temperature was set at 1000°C, and electrostatic force was applied so that the lamination strength was approximately 500 kg/cm2.

第1図(e)参照 第1のSiウェハ1を第2のSiウェハ2(薄膜3)の
張り合わせ面からカッターナイフを用いて剥がした。露
出した薄膜3の鏡面を0.1 μm研磨した。薄膜3の
厚みは0.5±0.05μmであった。
Referring to FIG. 1(e), the first Si wafer 1 was peeled off from the bonded surface of the second Si wafer 2 (thin film 3) using a cutter knife. The mirror surface of the exposed thin film 3 was polished by 0.1 μm. The thickness of the thin film 3 was 0.5±0.05 μm.

この後、酸化膜4と第3のSiウェハー5との張り合わ
せを完全にするため、窒素中1100°C530分のア
ニールを行った。
Thereafter, in order to completely bond the oxide film 4 and the third Si wafer 5, annealing was performed in nitrogen at 1100° C. for 530 minutes.

かくして、第3のSiウェハー5を支持基板とし、薄膜
3を素子基板(活性層)とするSol基板を得た。
In this way, a Sol substrate was obtained in which the third Si wafer 5 was used as a supporting substrate and the thin film 3 was used as an element substrate (active layer).

次に、実施例Hについて説明する。Next, Example H will be described.

第2図(a)乃至(e)は実施例■の工程を説明するた
めの断面図である。
FIGS. 2(a) to 2(e) are cross-sectional views for explaining the steps of Example (2).

第2図(a)の工程は第1図(a)と同じである。The process shown in FIG. 2(a) is the same as that shown in FIG. 1(a).

第2図(b)参照 実施例■と同様に、第1のSiウェハ1の準備に使用し
た高精度平面研削装置を用いて、第2のSiウェハ2を
張り合わせ面と反対側の面から研削し、第2のSiウェ
ハ2を厚さ0.5 μmの薄膜3に加工した。
Similar to Example 2 (see FIG. 2(b)), the second Si wafer 2 is ground from the surface opposite to the bonding surface using the high-precision surface grinding device used to prepare the first Si wafer 1. Then, the second Si wafer 2 was processed into a thin film 3 with a thickness of 0.5 μm.

第2図(c)参脇 市販の6インチSiウェハを第3のSiウェハー5とし
、その表面に厚さ0.1 μmの酸化膜4を形成した。
FIG. 2(c) Sanwaki A commercially available 6-inch Si wafer was used as the third Si wafer 5, and an oxide film 4 having a thickness of 0.1 μm was formed on the surface thereof.

第2図(d)参照 その酸化膜4と薄膜3を張り合わせる。張り合わせ強度
は張り合わせ温度と印加する静電圧力を調整し、約50
0 kg/cm”となるようにした。
Refer to FIG. 2(d), the oxide film 4 and the thin film 3 are pasted together. The bonding strength is approximately 50% by adjusting the bonding temperature and the applied electrostatic force.
0 kg/cm".

第2図(e)参照 これ以降の工程は、実施例Iと同様であり、第3のSi
ウェハー5を支持基板とし、厚さ0.5±0.05μm
の薄膜3を素子基板(活性層)とするSol基板を得た
See FIG. 2(e). The subsequent steps are the same as in Example I, and the third Si
The wafer 5 is used as a support substrate, and the thickness is 0.5 ± 0.05 μm.
A Sol substrate was obtained using the thin film 3 as the element substrate (active layer).

なお、薄膜3表面に酸化膜を形成し、第3のSiウェハ
ー5表面にも酸化膜を形成し、それらの酸化膜同志を張
り合わせ、その後第1のSiウェハ1を剥がすようにし
てもよい。
Note that an oxide film may be formed on the surface of the thin film 3, an oxide film may also be formed on the surface of the third Si wafer 5, these oxide films may be pasted together, and then the first Si wafer 1 may be peeled off.

〔発明の効果] 以上説明したように1本発明によれば、厚さが1μm以
下で厚さの均一性のよい薄膜を素子基板(活性層)とす
る張り合わせSol基板を提供することができる。
[Effects of the Invention] As described above, according to the present invention, it is possible to provide a laminated Sol substrate in which the element substrate (active layer) is a thin film having a thickness of 1 μm or less and good thickness uniformity.

本発明は、張り合わせSOI基板を用いたデバイスの性
能向上と歩留り向上に寄与するところが大きい。
The present invention greatly contributes to improving the performance and yield of devices using bonded SOI substrates.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)乃至(e)は実施例Iの工程を説明するた
めの断面図。 第2図(a)乃至(e)は実施例■の工程を説明するた
めの断面図。 第3図(a)乃至(c)は従来の工程を説明するための
断面図。 第4図(a)乃至(c)は従来の問題点を説明するため
の断面図 である。 図において。 1は第1のSiウェハー 1aは酸化IIり 1bはダメージ層。 2は第2のSiウェハー 2aは酸化膜。 3は薄膜。 4は酸化膜。 5は第3のSiウェハー (σ) 1杷例1の工程を説84¥う△約の吋面凹第 図 (e) 実絶倚°] IIの1/FL ’t−S先回するための
断面図第 2 図 (I)ン (C) 抜法のL札乞説朗オろための断面図 第 図
FIGS. 1(a) to 1(e) are cross-sectional views for explaining the steps of Example I. FIGS. 2(a) to 2(e) are cross-sectional views for explaining the steps of Example 2. FIGS. 3(a) to 3(c) are cross-sectional views for explaining conventional processes. FIGS. 4(a) to 4(c) are sectional views for explaining conventional problems. In fig. 1 is a first Si wafer 1a is a II oxide layer and 1b is a damaged layer. 2, the second Si wafer 2a is an oxide film. 3 is a thin film. 4 is an oxide film. 5 is the third Si wafer (σ) 1.Explain the process of Example 1 84¥U △Approximate concavity diagram (e) Real expiration degree] II's 1/FL 't-S To advance Cross-sectional diagram of Figure 2 (I) N (C) Cross-sectional diagram of Nukiho's L-note begging theory Figure 2

Claims (1)

【特許請求の範囲】 〔1〕均一な厚さを有する第1のSiウェハー(1)に
第2のSiウェハー(2)の鏡面研磨された面を張り合
わせた後、第2のSiウェハー(2)を研削して第2の
Siウェハーの薄膜(3)を形成する工程と、 前記薄膜(3)を酸化して、前記薄膜(3)表面に酸化
膜(4)を形成する工程と、 前記酸化膜(4)に第3のSiウェハー(5)を張り合
わせた後、前記第1のSiウェハー(1)を剥がして除
去する工程とを有することを特徴とするSOI基板の製
造方法。 〔2〕均一な厚さを有する第1のSiウェハー(1)に
第2のSiウェハー(2)の鏡面研磨された面を張り合
わせた後、第2のSiウェハー(2)を研削して第2の
Siウェハーの薄膜(3)を形成する工程と、 前記薄膜(3)に、表面に酸化膜(4)の形成された第
3のSiウェハー(5)の表面を張り合わせた後、前記
第1のSiウェハー(1)を剥がして除去する工程とを
有することを特徴とするSOI基板の製造方法。
[Claims] [1] After attaching the mirror-polished surface of the second Si wafer (2) to the first Si wafer (1) having a uniform thickness, the second Si wafer (2) is bonded to the first Si wafer (1) having a uniform thickness. ) to form a thin film (3) of a second Si wafer; oxidizing the thin film (3) to form an oxide film (4) on the surface of the thin film (3); A method for manufacturing an SOI substrate, comprising the steps of laminating a third Si wafer (5) to an oxide film (4) and then peeling off and removing the first Si wafer (1). [2] After bonding the mirror-polished surface of the second Si wafer (2) to the first Si wafer (1) having a uniform thickness, the second Si wafer (2) is ground to form a second Si wafer (2). a step of forming a thin film (3) on the Si wafer of No. 2; and after laminating the surface of a third Si wafer (5) on which an oxide film (4) is formed on the surface of the thin film (3); A method for manufacturing an SOI substrate, comprising a step of peeling off and removing a Si wafer (1).
JP12381490A 1990-05-14 1990-05-14 Manufacture of soi substrate Pending JPH0423324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12381490A JPH0423324A (en) 1990-05-14 1990-05-14 Manufacture of soi substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12381490A JPH0423324A (en) 1990-05-14 1990-05-14 Manufacture of soi substrate

Publications (1)

Publication Number Publication Date
JPH0423324A true JPH0423324A (en) 1992-01-27

Family

ID=14870001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12381490A Pending JPH0423324A (en) 1990-05-14 1990-05-14 Manufacture of soi substrate

Country Status (1)

Country Link
JP (1) JPH0423324A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6865090B2 (en) 1999-12-20 2005-03-08 Murata Manufacturing Co., Ltd. Outer coating substrate for electronic component and piezoelectric resonant component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6865090B2 (en) 1999-12-20 2005-03-08 Murata Manufacturing Co., Ltd. Outer coating substrate for electronic component and piezoelectric resonant component

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