JPH04233314A - Input circuit of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the noise by selecting clocks whose periods are different in accordance with a selecting signal whose period is longer than a clock period and generating a sampling pulse whose period is irregular, and latching in synchronizing with its pulse. CONSTITUTION:To a clock selecting means 5, clocks CL1, CL2 are inputted in advance, and when a selecting signal SL is inputted from a selecting signal generating means 4, the clock is selected in accordance with the signal SL and a sampling pulse SP is outputted. When the pulse SP is an input state and an input signal S is inputted to an FF 2a through an input terminal 7, the output Q1 of the FF 2a is synchronized with the pulse SP and inputted to an FF 2b and an AND circuit 2c. Also, the output Q2 of the FF 2b is synchronized with the pulse SP and inputted to a circuit 2c. When logic of the circuit 2c is formed, an output signal S' is outputted. In such a way, even if noise whose period is shorter than that of the sampling pulse contained in the input signal and the noise repeated in the same period are inputted, they can be eliminated surely.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit for a semiconductor device.

0002

2. Description of the Related Art FIG. 4 is a block diagram of an input circuit of a conventional semiconductor device. The input signal S is input to the input circuit 1 of the semiconductor device.
is input to the input terminal 7 of the flip-flop 2, and its output is input to the input terminal 7 of the flip-flop 2.
It is input to input terminal D of a. The output Q1 of the output terminal Q of the flip-flop 2a is the output terminal of the flip-flop 2b in the subsequent stage.
The signal is input to the input terminal D of the circuit and one side input terminal of the AND circuit 2c. Output Q2 of output terminal Q of flip-flop 2b
is input to the other input terminal of the AND circuit 2c, and an output signal S' is output from its output terminal. The clock CL is input to the frequency dividing circuit 6 of the input circuit 1, and the sampling pulse SP created by frequency division is input to the flip-flop 2a.
, 2b to each clock terminal CK. These flip-flops 2a, 2b and an AND circuit 2c constitute a noise removing means 2.

Next, the operation of the input circuit of this semiconductor device is as follows.
This will be explained with reference to FIG. 5 showing a timing chart of each part signal. As shown in Figure 5(b), the input signal S has different pulse widths; data A has the largest pulse width, and noise NB, NC, and ND have smaller pulse widths.
It includes ND and ND.

Data A of the input signal S shown in FIG. 5(b)
is connected to the input terminal D of the flip-flop 2a via the input terminal 7.
The clock CL is input to the frequency dividing circuit 6, and the sampling pulse SP with the same period as shown in FIG. and flip-flop 2a
The output Q1 is synchronized with the sampling pulse SP as shown in Figure 5.
As shown in (c), the output Q1A becomes the input terminal D of the flip-flop 2b and the AND circuit 2c.
is input to. Also, the output Q2 of flip-flop 2b
becomes Q2A as shown in FIG. 5(d) in synchronization with the sampling pulse SP, and this output Q2A is input to the AND circuit 2c. In this way, the output Q2A is the output Q1A
Therefore, the sampling pulse SP is delayed by one period. These outputs Q1A and Q2A are both connected to the AND circuit 2c.
When the logic of the AND circuit 2c is established,
The AND circuit 2c outputs data A' using the output signal S' shown in FIG. 5(e). This data A' is input to an internal circuit (not shown) of the semiconductor device.

By the way, the noise NB shown in FIG.
, the output Q1 of the flip-flop 2a is not obtained because it is not synchronized with the sampling pulse SP, and the noise NB does not appear in the output signal S'. Furthermore, when the noise NC is input in the same way as data A, the output Q1 of the flip-flop 2a becomes Q1C as shown in FIG. 5(c) in synchronization with the sampling pulse SP, and the output Q2 of the flip-flop 2b similarly becomes The result is Q2C as shown in FIG. 5(d). However, when the output Q1C falls, the output Q2C rises, and the logic of the AND circuit 2c is not established, so that the noise NC does not appear in the output signal S'.

Furthermore, when a plurality of noises ND, ND, ND occurring at the same period as the sampling pulse SP are input in the same manner as described above, the output Q1 of the flip-flop 2a is synchronized with the sampling pulse SP and becomes ) as shown in Q1D, and the output Q2 of flip-flop 2b
Similarly, becomes Q2D as shown in FIG. 5(d). These outputs Q1D and Q2D are input to the AND circuit 2c,
When the logic of AND circuit 2c is established, AND circuit 2
c is the noise ND' included in the output signal S' shown in FIG. 5(e).
Output. In this way, the sampling pulse SP
The input signal S having a pulse width of two cycles or more is converted to data A.
The single noise NB input to the input terminal D of the flip-flop 2a when the sampling pulse SP is not present or the single noise NC having a pulse width of one cycle of the sampling pulse SP is recognized as noise. As a result, the noise NB, NC included in the input signal S becomes the output signal S'
will no longer appear.

[0007]

[Problem to be Solved by the Invention] However, as mentioned above, if the input signal contains noise ND, ND, ND that is synchronized with the sampling pulse SP and occurs repeatedly in the same period, it should be considered as noise. There is a possibility that the data cannot be recognized and is included in the output signal and mistakenly recognized as data A. Also, like the noise ND, the noise N is synchronized with the sampling pulse SP and has the same period.
D, ND, and ND exist in the vicinity of the input circuit due to the operation of the semiconductor device, and as a result, there is a problem that data A is easily misidentified, and the reliability of the input circuit of the semiconductor device is low. In view of such problems, it is an object of the present invention to provide a highly reliable input circuit for a semiconductor device that does not include noise in the output signal even if the input signal contains noise with the same period. .

[0008]

[Means for Solving the Problems] An input circuit for a semiconductor device according to the present invention includes a plurality of clock generation means each generating clocks having different periods, and a clock generation means having a period shorter than the period of the clock of the plurality of clock generation means. a selection signal generation means for outputting a selection signal consisting of a long clock; inputting each clock outputted by a plurality of clock generation means and the selection signal; and selecting the input clock according to the selection signal;
The clock selection means outputs the selected clock.

[0009]

[Operation] One of the clocks with different periods is selected according to the selection signal, and sampling pulses with irregular periods are created. The created sampling pulse is applied to the first and second flip-flops. The first and second flip-flops latch data that is longer than the period of the sampling pulse in synchronization with the sampling pulse. Noise that is shorter than the period of the sampling pulse included in the input signal is the first noise.
The second flip-flop does not latch, and noise that repeats in the same cycle is latched only by the first flip-flop, so that data and noise can be distinguished. Therefore, the output signal does not contain noise.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to drawings showing embodiments thereof. FIG. 1 is a block diagram of an input circuit of a semiconductor device according to the present invention. An input signal S is input to the input terminal 7 of the input circuit 1 of the semiconductor device, and its output is input to the input terminal D of the flip-flop 2a. flip flop 2a
The output Q1 of the output terminal Q of is the flip-flop 2 in the subsequent stage.
It is input to the input terminal D of the circuit 2c and one side input terminal of the AND circuit 2c. The output Q2 of the output terminal Q of the flip-flop 2b is input to the other input terminal of the AND circuit 2c, and an output signal S' is output from its output terminal. Flip-flop 2a, 2
b and the AND circuit 2c constitute a noise removing means 2.

Clock CL1 from a plurality of clock generating means 3a, 3b, . . . which generate clocks with different periods;
CL2... is input to the clock selection means 5. The clock from the clock generating means 8 is input to the selection signal generating means 4. Based on the input clock, the selection signal generation means 4 generates a selection signal SL consisting of a clock whose period is longer than that of the clocks outputted by the clock generation means 3a, 3b, . . ., whose pulse width is larger. The selection signal S
L is input to the clock selection means 5. The clock selection means 5 selects the clock CL1 according to the input selection signal SL.
, CL2 are selected, and a sampling pulse SP based on the selected clock is input to the clock terminals CK of the flip-flops 2a and 2b. The clock generating means 3a, 3b, . . . , the clock generating means 8, the clock selecting means 5, and the selection signal generating means 4 constitute a sampling pulse generating means 9.

Note that clock CL1 and clock CL2
, each period of the selection signal SL is, for example, a clock CL1.
If the period of is 2X, then 2X, 3X, and 5X are selected. The period of the selection signal SL is selected to be equal to or less than the period of the input signal S (see FIG. 3). FIG. 2 is a block diagram of the clock generating means 3a, 3b, . . ., which is composed of a ring oscillator using an odd number of inverters IV1, IV2, IV3. Inverter IV1, IV
2 and IV3 are connected in series, and the output side of inverter IV3 is directly connected to the input side of inverter IV1. Input side of inverter IV2 and inverter IV3
The input sides of are grounded via capacitors C1 and C2 separately. A clock CL is output from the output side of the inverter IV3.

Next, the operation of the input circuit of the semiconductor device configured as described above will be explained with reference to FIG. 3, which shows a timing chart of signals of each part.
I will explain it together. For ease of explanation, it is assumed that means 3a and 3b for generating clocks with different periods are used, and the input signal S has different pulse widths as shown in Fig. 3(e), and data A with the largest pulse width is used. and noises NB, NC, and ND whose pulse widths are smaller than that, and the noises ND, ND, and ND occur repeatedly in the same period.

Here, the sampling pulse generating means 9 includes:
The clock selection means 5 receives the clocks CL1 and CL shown in FIGS. 2(b) and 2(c) from the clock generation means 3a and 3b.
2 from the selection signal generating means 4.
When the selection signal SL shown in (a) is input, clocks CL1 and CL2 are selected according to the selection signal SL, and the clocks shown in FIG.
(d) Output the sampling pulse SP shown in FIG. In other words, when the selection signal SL is at L level, the clock CL1
, and when it is at H level, select clock CL2. Then, as shown in FIG. 3(d), the pulse portion of the clock CL1 during which the selection signal SL is at the L level is selected, and the pulse portion of the clock CL1 during which the selection signal SL is at the H level is selected.
The pulse portion of L2 is selected to obtain a sampling pulse SP having an irregular period as shown in FIG. 3(d). This sampling pulse SP is input to each clock terminal CK of flip-flops 2a and 2b.

Now, with the sampling pulse SP being input to the clock terminal CK in this way, FIG.
) When the data A of the input signal S shown in FIG.
In synchronization with P, it becomes Q1A as shown in Fig. 3(f), and
This output Q1A is input to the input terminal D of the flip-flop 2b and the AND circuit 2c. In addition, the output Q2 of the flip-flop 2b becomes Q2A as shown in Fig. 3(g) in synchronization with the sampling pulse SP, and this output Q2
A is input to the AND circuit 2c. In this way the output Q2
A lags the output Q1A by one cycle of the sampling pulse SP. These outputs Q1A and Q2A are input to the AND circuit 2c, and when the logic of the AND circuit 2c is established, the AND circuit 2c outputs data A' by the output signal S' shown in FIG. 3(h). This data A' is input to an internal circuit (not shown) of the semiconductor device.

By the way, when the noise NB or NC shown in FIG. 3(e) is input to the input terminal D of the flip-flop 2a in the same way as the data A, the output Q1 of the flip-flop 2a is not synchronized with the sampling pulse SP. Therefore, as shown in FIG. 3(h), the output signal S' does not contain noise NB or NC. In addition, Fig. 3(e
) Multiple noises N occurring at the same period as shown in
When D, ND, and ND are input in the same way as data A, the output Q1 of the flip-flop 2a becomes Q1D as shown in Fig. 3(f) due to the second noise ND synchronized with the sampling pulse SP, and its output Q1D is input to AND circuit 2c. However, since the output Q2 of the flip-flop 2b and the sampling pulse SP are not synchronized, there is no output Q2 of the flip-flop 2b, and the logic of the AND circuit 2c is not established. h) Noise ND does not appear as shown in .

In this way, the sampling pulse SP
Since the period of the input signal S is made irregular so that the noise of the input signal S and the sampling pulse SP are not synchronized, the sporadic noise NB, NC with a pulse width of one period or less of the sampling pulse SP is flip-flop 2a
, 2b do not latch, and are less than one period of the sampling pulse SP, and the noise ND occurring in the same period
, ND, and ND are latched only by the first flip-flop 2a, so that the logic of the AND circuit 2c is not established, and the output signal S' does not contain noise corresponding to the noise ND. Therefore, the noise in the output signal S' can be completely eliminated, and the reliability of the input circuit of the semiconductor device can be greatly improved.

In this embodiment, the selection signal generating means 4 is supplied with a clock generated by a clock generating means 4 different from the plurality of clock generating means 3a, 3b. A clock generated by frequency-dividing the clock may be supplied. It goes without saying that by increasing the number of clock generation means that generate clocks with different periods, the period of the sampling pulse can be made even more irregular, and the noise removal function can be further improved.

[0019]

Effects of the Invention As described in detail above, the present invention selects a clock with a different period according to a selection signal whose period is longer than the clock period, generates a sampling pulse with an irregular period, and synchronizes with the sampling pulse. Since the input signal is latched by the flip-flop, even if noise whose cycle is shorter than the sampling pulse included in the input signal and noise which repeats at the same cycle are input, they are reliably removed. Therefore, it is possible to provide an extremely reliable input circuit for a semiconductor device that does not output noise.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an input circuit of a semiconductor device according to the present invention.

FIG. 2 is a block diagram showing the configuration of clock generation means.

FIG. 3 is a timing chart of various signals in FIG. 1;

FIG. 4 is a circuit diagram of an input circuit of a conventional semiconductor device.

FIG. 5 is a timing chart of various signals in FIG. 4;

[Explanation of symbols]

1 Input circuit 2a, 2b flip-flop 2c AND circuit 3a, 3b Clock generation means 4 Selection signal generation means 5 Clock selection means

Claims (1)

[Claims] 1. A first flip-flop that latches an input signal in synchronization with a clock; a second flip-flop that latches an output of the flip-flop in synchronization with a clock; In an input circuit of a semiconductor device that inputs an output of a flip-flop to a logic circuit and inputs the output to an internal circuit, a plurality of clock generation means generate clocks with different periods, and a period of the clock of the plurality of clock generation means. A selection signal generation means for outputting a selection signal with a longer period, each clock outputted by the plurality of clock generation means and the selection signal are inputted, selects a clock according to the selection signal, and outputs the selected clock. 1. An input circuit for a semiconductor device, comprising: clock selection means, and first and second flip-flops are configured to latch an input signal in synchronization with a clock output by the clock selection means.