JPH0423347B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a memory address control circuit that monitors write and read addresses of a jitter absorbing memory of a PCM playback device. Currently, in audio equipment, in addition to the method of recording and playing back analog signals, there is a method generally called the PCM recording/playback method, which converts analog signals into digital signals and records and plays them back. The latter method is highly faithful to recording and playback, and is likely to be widely used in the future. There are disks and tapes as recording media for digital signals, both of which use a rotating system. Therefore, the digital signal contains jitter due to uneven rotation. In order to perform ultra-fidelity playback, a PCM playback device stores the jitter-containing digital signal in memory and reads it out using a crystal oscillator clock to absorb the jitter. This memory is called a jitter absorbing memory, and since the write timing and read timing of the memory are shifted relative to each other by the amount of jitter, there are two types of address counters that specify addresses to the memory: write-only and read-only. pcs are required. The operation of the address control circuit of a conventional jitter absorbing memory will be briefly explained using the circuit configuration diagram in FIG. 1, the timing chart in FIG. 2, and the configuration diagram of the jitter absorbing memory in FIG. 3. Also, to simplify the explanation, data reproduced from a disk, tape, etc. is divided into six blocks in one block between synchronization signals.
It is assumed that there are data w ₀ , w ₁ , w ₂ , w ₃ , and w ₄ , and interleaving is performed at 4-block intervals between each data w ₀ to _{w 5} . As shown in Figure 3, the memory capacity is w ₀
It is handled as a memory with 6 rows A to F corresponding to ~ _w5 and 30 columns that can store 30 blocks of data. In FIG. 1, 1 is a data capture device that captures digital signals reproduced from a disk, tape, etc., and outputs data to a data bus 19;
21 is a D/A converter that takes in the data once written in the memory 3 and converts it into an analog signal when it is read out, and 21 is an address control circuit that gives an address to the memory 3. The internal configuration is for writing only. a write-only address counter 9 giving memory row addresses 0-5; a column address counter 8 giving column addresses 0-29; and a read-only row address counter 6 giving memory row addresses 0-5. a column address counter 7 which gives . a multiplexer 4 that switches according to write and read cases and supplies an address to the address bus 20 of the memory 3; and a read-only column address counter 7 for monitoring how much the write timing and read timing are shifted due to jitter. It consists of an address monitoring circuit that checks the difference between write-only column address counters 8.
The operation of these circuits will be explained using the timing chart in FIG. 2 and the memory configuration diagram in FIG. 3. The input 13 of the write-only column address counter 8 receives a synchronizing signal pulse containing jitter, as shown in FIG. 2e. Further, six pulses from the synchronization signal are applied to the input 14 of the row address counter 9, as shown by f in the figure. Therefore, during a write operation, by selecting the multiplexer 4 to the B side and giving the values of counters 8 and 9 to the address bus 20, the data □1 to □ of w ₀ to w ₅ on the data bus in FIG. 6 are sequentially written as shown in FIG. Next, input 1 of read-only column address counter 7
As shown in FIG. 2b, the second pulse generated from the crystal oscillator is added to the input of the row address counter 6.
The pulse shown in figure c is added. The values of these address counters 6 and 7 are applied to the decoder 5. decoder 5
Then, the value of the column address counter 7 is added to the value of the row address counter 6 by the numerical values shown in the following table.

[Table] If the multiplexer 4 is selected to the A side during reading by the addition of this decoder 5, the address will be △1 to △1 in FIG. The position is △6, and the data bus 19 is in the shape where the interleaving applied to w ₀ to _{w 5} is solved.
Send data to. The data sent out by the crystal oscillator clock in this way is taken into the D/A converter 2 and converted into an analog signal.
This means that a jitter-free signal can be obtained. Also,
When a difference occurs between the values of the write-only column address counter 9 and the read-only column address counter 7 due to jitter, if the value of the counter 8 is larger than the value of the counter 7, the values △1 to △6 in FIG. Although the read position is moved to the left relative to □1 to □6, as can be seen from FIG. 3, correct data can be read within a movement range of 4 blocks. Conversely, if the value of the counter 8 is smaller than the value of the counter 7, the reading positions Δ1 to Δ6 in FIG. 3 will be relatively moved to the right. However, as before, correct data can be read within a movement range of 4 blocks. As described above, the jitter absorption memory 3 can absorb jitter within ±4 blocks shown in the bold line in Figure 3, but if there is an input that contains more jitter. In this case, the erroneous data may be transferred to the D/A converter 2.
This results in continuous transmission. Therefore, the address monitoring circuit 10 detects that the difference between the values of the write-only column address counter 8 and the read-only column address counter 7 exceeds ±4, and uses the detection pulse to reset the counters 8 and 7 and initialize them. It's getting back to normal. In this way, the address monitoring circuit 10
When activated, the counters 8 and 7 are reset, so the data becomes momentarily discontinuous and an abnormal sound is generated. In the address control circuit shown in FIG. 1, considering the moment when the power is turned on, if the difference between the values of the write-only column address counter 8 and the read-only column address counter 7 exceeds ±4, the above Similarly, the address monitoring circuit 10 operates and resets the counters 8 and 7 to the initial state. However, if the difference is within the range of ±4, the address control circuit operates from the original state without returning to the initial state. Therefore, the margin of the memory for absorbing jitter is biased to one side, and the address monitoring circuit 10 is likely to operate even in response to small jitter, which is disadvantageous in that abnormal noise is likely to be generated. In addition, such a state does not only occur when the power is on, but after playing several PCM songs, the previous PCM playback will absorb the jitter before moving on to the next PCM playback, causing the same inconvenience as described above. An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, to set the address monitoring circuit to an initial state when the power is turned on and at the beginning of PCM playback, and to mute the address monitoring circuit so as not to output abnormal sounds when it is activated. The purpose of the present invention is to provide a memory address control circuit for a PCM playback device. For this reason, the present invention provides a PCM playback device that includes:
External input signals such as the mute control signal generated when the power is turned on or when PCM playback is interrupted are added to the address control circuit, and the counter of the address control circuit is reset to the initial state using the above external signal and the detection signal of the address monitoring circuit. Along with this, turn on Miyuto.
However, by detecting that the counter of the address control circuit has exceeded a certain value and turning off the Mute, the abnormal sound is not output when the address monitoring circuit is activated. An embodiment of the present invention will be described below with reference to FIG. 15 is an R circuit for logically ORing the output of the address monitoring circuit 10 and the mute control signal input terminal 19, and 16 is an R circuit that is found to have accumulated data for deinterleaving in the memory after the counter was reset. 17 is an RS flip-flop which is set by the output of the R circuit 15 and reset by the output of the numerical detection power circuit 16. , 18 is
This is the output terminal of the RS flip-flop and is the mute signal of the PCM playback device. Other symbols are the same as in FIG. 1. The operation will be explained below with reference to FIG. Power on
Since it is obvious in conventional PCM devices that mute is added when a PCM playback device plays one piece of music and then plays the next song, we will explain the circuit that generates these mute control signals. is omitted. First, when the power is turned on, when a mute control signal is applied to the input terminal 19, the signal is passed through the OR circuit 15 to the RS flip-flop 17.
and mute the output of the PCM playback device. At the same time, the read-only and write-only column address counters 8 and 7 are reset. This operation sets the address counter to its initial state. After the counter is reset thereafter, the numerical value detection circuit 16 of the read-only column address counter 7 detects that data for deinterleaving has been accumulated, and muting is canceled. This operation mutes abnormal sounds when the power is turned on. Such an operation occurs when a mute control signal is applied to the input terminal 19, and the same operation is performed for mute between songs. Next, when the address monitoring circuit is activated due to jitter during PCM playback, the output of the address monitoring circuit 10 is passed through the OR circuit 15 to the RS flip-flop 1.
7 and resets counters 7 and 8. Therefore, the mute is applied in the same way as when the power is turned on, and the mute is canceled when the data for solving the interleave is accumulated. In FIG. 4, the numerical value of the read-only column address counter 7 is detected by the numerical value detection circuit 16 and the mute is canceled, but even if the numerical value of the write-only column address counter 8 is similarly detected and the mute is canceled, You can do the same work as above. In the embodiment shown in FIG. 4, the structure of the memory 3 is 6 rows 30
It goes without saying that the same address control circuit operation can be performed if the address control circuit is configured in columns and the address counter is divided into rows and columns, but if it is configured in such a way that there is a write address counter and a read address counter. stomach. Further, in the embodiment shown in FIG. 4, a mute control signal is applied to the input terminal 19, but the same operation can also be performed by applying a signal such as the output signal of a switch that causes the PCM playback device to start playback. This has the effect that the address control signal can be set to the initial state at the beginning of playback. Therefore, according to the present invention, since the counter of the address control circuit can be set to the initial state between songs when the power is turned on, there is an effect that the address monitoring circuit is less likely to operate than before, and the address monitoring circuit is Even when the system is in operation, it is determined that data for solving the interleave has been accumulated and cancels the mute, which has the effect that no abnormal sound is output.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the address control circuit of a conventional jitter absorption memory, Fig. 2 is a timing chart used to explain the block diagram in Fig. 1, and Fig. 3 is data written to the memory in Fig. 1. , a block diagram of a memory showing data to be read, and FIG. 4 is a block diagram showing an embodiment of the present invention. 3...Memory, 7...Write-only column address counter, 8...Read-only column address counter, 10...
Address monitoring circuit, 16... Numerical value detection circuit, 18...
Mute signal output terminal, 19...input terminal.

Claims (1)

[Claims] 1. A write-only address counter that provides an address to the memory when writing data to the memory;
In a PCM playback device that is equipped with a read-only address counter that gives an address to the memory when data is read from the memory, it is possible to detect that at least the values of the write-only address counter and the read-only address counter have a certain difference. an address detection circuit to detect; an external input terminal to which a mute control signal indicating the start of playback in the PCM playback device is applied from the outside; and logic for calculating the logical sum of the input signal of the external input terminal and the output signal of the address detection circuit. A PCM reproducing apparatus comprising: a sum means; and a control means for controlling the write-only address counter and the read-only address counter to the same value based on the output signal of the logical sum means at the time of starting reproduction. memory address control circuit. 2. The address detection circuit includes a numerical value detection circuit that detects when the read-only address counter or the write-only address counter reaches a certain value or more, and the control means is configured such that the address detection circuit detects the write-only address. When it is detected that the values of the counter and read-only address counter become a certain value, mute processing is applied to the output signal of the PCM playback device, and the write-only address counter and read-only address counter are reset. , a patent claim characterized in that when the numerical value detection circuit of the address detection circuit detects that the read-only address counter or the write-only address counter has exceeded a certain value, the mute processing is canceled. A memory address control circuit for the PCM playback device according to item 1.