JPH0423468A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve a yield by forming the layout of a plate electrode in such a shape that it does not exist between adjacent bit line contact regions. CONSTITUTION:In a DAC(Diagonal Array Cell), a plate electrode layout 16 is formed in a shape in which a plate electrode does not exist between bit line contacts 15 and 15, i.e., in the layout 16 in which its oblique direction is punched. Accordingly, residual etching of the electrode 16 generated between the contacts 15 and 15 can be eliminated. Thus, the contact of the residue with the contact 15 can be avoided to improve its yield.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a semiconductor memory (semiconductor storage device), and in particular to an M'OS having a stacked memory gear batter.
The type is about memory.

(b) Conventional technology As well as increasing the integration density of LSI memory, securing cell capacity 4
In order to achieve this goal, a stacked memory gear batter that three-dimensionally utilizes the surface level difference formed by the underlying layer of a semiconductor element has been developed and is being put into practical use.

Now, a layout example of a stacked memory capacitor (
A D A C cell) is shown in FIG. 2 (the plate electrodes are not shown in FIG. 2).

In FIG. 2, l, 2, 3.4 and 5 are active regions;
These layers are transfer gates (indicated by diagonal lines), which are word lines, layerers that determine node electrode contacts, note electrodes, and bit line contacts, respectively.

An example of the layout of plate electrodes is shown in FIG.

In FIG. 3, the plate electrode (the plate electrode layout is shown as a shaded area) 6 is normally connected to the bit line contact l.
It has an open shape around -5.

In the production of conventional stacked memory capacitors, after forming the element isolation section and transfer cables 1 and 2, 5iOJX is deposited by the CV l) method, and after the oxide layer is formed to form a Zyte wall, C is further deposited.
VI) Deposit Sif and pattern by method.

Next, a note? 11t Kokuconotact 3 to 11 old,
A polysi film is deposited by the CVD method, made into an electrode by diffusion of PCL, etc., and patterned to form the node electrode 4. After that, a capacitor insulating film is formed, and then C
A polysi film is deposited by the VD method and made into an electrode by diffusion of PCL or the like, and then a plate electrode 6 is patterned [see FIG. 3].

(c) Problems to be solved by the invention However, the conventional cell layout (DA
In the C cell), the bit line contact 5 is patterned as shown in the patterning of the plate electrode 6 in the area shown by the circle in FIG.
Since it has an open shape around it, the base has a high level difference. For example, if the thickness of LOGO3 is 4000 people, half of that is 2000 people, the thickness of transfer gate electrode 2 is 3000 people, and the thickness of transfer gate electrode 2 is 3000 people.
If the thickness of the ift film is 3000 mm, the total step difference from the active region 1 is as high as 2000'' - 3000 + 3000 = 8000. Therefore, as shown in FIG. 4, etching remains on the plate electrode tend to occur at the stepped portion. That is, FIG. 4 shows an active region 1, a transfer gate 2, a pitch line 1-5, and a plate electrode (shown as a shaded area) 6. In FIG.
Step S - The etched residue 6a of the electrode protrudes into the active region I. transfer gate 5ho
In the worst case, due to the Zyte wall 8 (the part indicated by the dotted line in Figure 4), the plate electrode etching remains 6.
a occurs in the active region l.

In reality, due to misalignment, the bit line contact 5 comes into contact with the etched remaining portion of the plate electrode during the human line wiring performed in the later process, causing a short circuit with the plate electrode, resulting in a decrease in yield and reliability. There is a risk of significant damage to the

(d) Means and operation for solving the problem This invention includes:
A DAC (Diagona
This is a semiconductor memory in which a layerer 1 of a plate 1 electrode is formed in a shape that does not exist in a region between adjacent pitch line contacts in a memory cell employing the 1 Array Ce11 method.

That is, in a DAC cell, when removing the area around the bit line contact region of the plate electrode formed on the entire surface, the present invention uses a mask having this shape that is processed into a shape that eliminates the presence of the plate electrode between the bit line contact regions. Therefore, the play I-Flu pole is removed). In view of this, in the present invention, in FIG. 2, where the plate electrode is not shown, the plate electrode, for example, polysilicon, is formed on the entire surface, and then the area around the contact region is removed, unlike the conventional method shown in FIG. This invention has a pattern shape in which the holes are not formed as shown in FIG. 1, but as shown in FIG. This eliminates the etching residue on the plate electrode that conventionally occurs between the bit line contacts, and even if misalignment occurs, it is possible to avoid contact between the etching residue on the plate electrode and the bit line contact, resulting in short circuits. can be prevented.

(e) Examples The present invention will be described in detail below based on embodiments shown in the figures.

Note that this invention is not limited by this.

FIG. 1 shows an embodiment of the present invention, in which the plate electrode layout is shown by diagonal lines.

In FIG. 1, 11 is a layout layer that determines the active region, 12 is a layout layer that determines transfer gates, 14 is a layer that determines node electrodes, 15 is a layout layer that determines bit line contacts, and 16 is a plate. This is a layout layer (shaded area 1:I in FIG. 1) that determines the electrodes.

The plate electrode layout 16 does not have a shape in which the plate electrode layout 6 surrounds the entire circumference of the bit line contact 5 as in the conventional layout 6 shown in FIG. has a non-existent shape.

This is because conventionally, in the area between bit line contacts 1-5, the etched residue of plate electrode 6 protrudes into the active region due to misalignment at the high step portion. In order to avoid the etching remaining part from coming into contact and causing damage,
In this embodiment, the layerer 1-16 of the plate electrode is not provided in the region between the bit line 1 contacts 115 and 15, that is, the layerer 1-16 is punched in an oblique direction.
It is composed of

Therefore, even if a 4V misalignment occurs, contact between the etched residue of the plate electrode and the bit line contact can be avoided, short circuits can be prevented, and high yield and reliability can be obtained, resulting in excellent productivity. A memory cell layout can be realized.

(f) Effects of the Invention According to the present invention, the layer of the DAC cell plate 1-71i pole is formed into a shape punched out in the diagonal direction, thereby forming the area between the bit line contacts. Since the plate electrode is configured in such a shape that no plate electrode exists, it is possible to eliminate the etching residue of the plate electrode that occurs between the bit line contacts, and thereby to avoid contact between the etching residue and the bit line contact 1-. ,
As a result, high yield, high reliability devices can be obtained at high cost.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the configuration of a layerer l- of a plate electrode showing an embodiment of the present invention, and FIG.
3 is a diagram corresponding to FIG. 1 showing a conventional example, and FIG. 4 is an explanatory diagram showing the etching remaining on the plate L-electrode of the conventional example.・・Layout layer of active region, layout layer of transfer gate, ・layout layer of node electrode, ・layout layer of bit line contact, play 1-7[
i-pole layout layer. l 1・・ 12 ・・ l 4・ 15・ I 6・ ・

Claims (1)

[Claims] 1. A DAC (Diagon
1. A semiconductor memory in which a plate electrode is arranged in a shape that does not exist in a region between adjacent bit line contacts in a memory cell employing an ArrayCell method.