JPH04235437A - Buffer memory controller - Google Patents

Abstract

PURPOSE:To reduce data quantity in a single write-in to a buffer memory and the number of times of writ-in and to improve the utilization efficiency of the buffer memory. CONSTITUTION:This controller for a buffer memory suitable for a television telephone device and a video codeck used for a conference system consists of a variable length encoder part 2, switching circuits 3 and 4, a presence judgement circuit 6, a variable length code generation circuit 7, an escape sequence data generation circuit 8 and a stuffing code generation circuit 29. Codes with different effective data length can be incorporated in a single block designated with a prescribed bit length without extending into several data blocks, and the data width of the data block can be reduced to a minimum necessary size.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer memory control device, and more particularly to a buffer memory control device suitable for a video codec used in a television telephone/conference system.

0002

2. Description of the Related Art A video codec 70 as shown in FIG. 5 is used in a terminal device of a television telephone/conference system. There is.

The video encoder 73 performs various signal processing on the video signal supplied via the terminal 71 from a video input/output device (not shown) disposed in the previous stage, and also performs various signal processing according to the CCITT Recommendation H. After performing encoding specified in H.261 [hereinafter simply referred to as recommendation], the encoded data is outputted via a terminal 72 in bit serial form. That is, after processing such as motion compensation and interframe prediction in the video signal encoder 75, DCT, quantization, etc. are performed to form transform coefficients TC, and various flag information, identification information, characteristic information, etc. Added transmission encoder 76
supplied to

In this video encoder 73, video signals are multiplexed into a hierarchical structure consisting of four layers, as described below. The four layers mentioned above are the frame layer, the group of blocks [hereinafter simply referred to as GOB] layer, the macroblock [hereinafter simply referred to as MB] layer, and the block layer, each of which has a unique data format. have.

The frame layer will be explained with reference to FIG. The frame layer, as shown in FIG. 6, is composed of a frame header followed by a GOB. The frame start code [hereinafter simply referred to as PSC] is a code added to the beginning of the data format, and is a 20-bit code ["0000 0000 0000 0001 00
00''].The frame number TR is 5 bits and represents the frame number.The type information PTYPE is 6 bits and represents the information of the entire frame.The extension data insertion information PEI is 1 bit. “1” indicates the presence or absence of the next expansion data area (preliminary information).
”, it is considered to be present.

[0006] The preliminary information PSPARE is expressed in 8-bit units of data of 0/8/16, and currently the encoding device side does not insert this preliminary information PSPARE until its usage is specified by CCITT. It is said that this should not be done. GOB represents data of each frame, and will be explained below.

GOB corresponds to a (1/12) frame in the CIF frame as shown in FIG.
The frame corresponds to (1/3) frame as shown in FIG. GOB is configured in a data format as shown in FIG. This will be explained below based on FIG. The GOB layer is GOB
It consists of a header followed by MB. The GOB start code (hereinafter simply referred to as GBSC) is a code added to the beginning of the data format, and is a fixed length code consisting of 16 bits ["0000 0000 0000 0001"].

[0008] The GOB number GN represents the position of the GOB using 4 bits. The quantization characteristic information GQUANT represents information on the quantization characteristic using 5 bits. The expansion data insertion information GEI has 1 bit and indicates the presence or absence of the next expansion data area (preliminary information), and when it is "1", it is determined that there is. Preliminary information G
SPARE is represented by 8-bit data of 0/8/16, and currently the CC
Until the usage is specified by ITT, this preliminary information
It is said that SPARE should not be inserted. The GOB described above is divided into 33 macroblocks MB as shown in FIG.

The macroblock MB layer has a data format as shown in FIG. This will be explained below based on FIG. 11. Macro block M
The B layer is composed of a header of a macroblock MB and data of the following block. The macroblock address (hereinafter simply referred to as MBA) indicates the position of the macroblock MB in the GOB, and its transmission order is shown in FIG. Each of these MBAs has Figure 12
Variable length codes are defined as shown in . still,
A special code called MBA stuffing code can be inserted to stuff bits immediately after the GOB header or immediately after the encoded macroblock MB, and this code is discarded at the decoding device side.

Type information [hereinafter simply referred to as MTYPE] indicates the type of macroblock MB and which data elements appear, and its details are shown in FIG. For this MTYPE, a variable length code is defined as shown in FIG. 13 corresponding to each MTYPE. Note that in FIG. 13, "X" indicates that the corresponding element is included in the macroblock MB. In addition, when applying a filter to a non-motion compensated macroblock MB, the motion vector is set as a zero vector and “M
C+FIL”. Quantization characteristic information MQUANT
is a 5-bit code that indicates the quantization characteristic used in the macroblock MB and the macroblocks MB subsequent to the macroblock MB in the GOB, and appears only when instructed by MTYPE. This quantization characteristic information MQUANT is the quantization characteristic information G
Same as QUANT.

Motion vector information (hereinafter simply referred to as MVD) is included in every MC macroblock MB. A variable length code is defined for each of these MVDs as shown in FIG. 14. A significant block pattern (hereinafter simply referred to as CBP) represents a block in which at least one transform coefficient TC is transmitted, and appears only when indicated by the above-mentioned MTYPE. This C
A variable length code is defined for each BP as shown in FIG. The block data corresponds spatially to the luminance signal blocks BY1 to BY4, which have 16 pixels x 16 lines and are divided into 4 sections of 8 pixels x 8 lines, as shown in FIG. and a block BCR of color difference signals of 8 pixels x 8 lines shown in FIG.
, BCB.

[0012] The block layer includes the above-mentioned blocks BY and BCR.
, BCB, and blocks BY, BCR,
As shown in FIG. 19, BCB data consists of a conversion coefficient TC transmitted in units of 64 bytes, followed by an end-of-block code [hereinafter simply referred to as EOB] that is transmitted and indicates the end of the block. Ru. The transmission order is luminance signal block BY, color difference signal block BC
The order is R, BCB. The above block BY,
Each of BCR and BCB is composed of 64 transform coefficients TC consisting of 8 pixels x 8 lines as shown in FIG. 20, and the quantized transform coefficients TC are as shown in FIG.
They are transmitted in the numerical order indicated by the arrows inside.

In the transmission encoder 76, the above-mentioned transform coefficient TC
Among various flag information, identification information, characteristic information, etc., predetermined information is encoded. In FIG. 6, a description of the video decoder 74, which includes a transmission decoder, a buffer memory, a video signal multiplexing decoder, an information source decoder, etc., will be omitted.

The transmission encoder 76 performs various types of encoding and processing for various types of encoding as described above, and an example thereof will be described below with reference to FIG. 21. In this transmission encoder 76, first and second characteristic values are formed from the transform coefficients CT. That is, the first characteristic value is the number R of consecutive zeros (hereinafter referred to as a run) when transmitted in the numerical order shown in FIG. This is the subsequent non-zero value (hereinafter referred to as level) LV.

In the configuration of FIG. 21, the characteristic value generation section 81
Then, two characteristic values, run R and level LV, are formed based on the fixed length conversion coefficient TC supplied from the terminal 80. This run R and level LV are supplied to the transmission buffer 77 via terminals 82 and 83.

FIG. 22 shows the run R specified in the recommendation.
Variable length codes corresponding to 62 frequently occurring combinations of LV and level LV are shown. In the variable length code in FIG. 22, "1s" means the code for the first coefficient data, and "11s" means the code for the second coefficient data. It means. Further, the last bit "s" indicates whether the level LV is positive or negative, and the value of the sign bit SB is substituted therein, with "0" being positive and "1" being negative.

Furthermore, if the variable length code corresponding to the combination of the values of run R and level LV is not specified in the recommendation, the escape code shown in FIG.
It consists of a 6-bit identification code called ESC], a 6-bit run R shown in FIG. 23, an 8-bit level LV shown in FIG. 24, and a 5-bit effective data length. A 25-bit fixed length code is constructed. Note that the MSB in the 8-bit fixed length code of level LV shown in FIG. 24 is taken as the sign bit SB.

[0018] The various codes mentioned above, for example, MBA,
MTYPE, MVD, CBP, variable length codes such as conversion coefficient TC specified in the recommendation, GBSC, P
There are techniques shown in FIGS. 25 to 27 for outputting fixed length codes such as SC and conversion coefficients TC not specified in the recommendations to the line via the transmission buffer 77.

FIG. 25 is constructed by focusing on the fact that the above-mentioned data is output to the line as 1-bit serial data. The transmission encoder 76 in this case is composed of a variable length block 86 and a parallel/serial conversion circuit 85. In a variable length conversion block 86, predetermined data is converted into a variable length code, and an effective data length is added to the variable length code to make it serial data,
Alternatively, an effective data length is added to a fixed length code to generate serial data. And this serial data is 1
The data is sequentially outputted to the line via the transmission buffer 77, which is a buffer memory formed by n stages of bit memories connected in cascade.

FIG. 26 is constructed by focusing on the fact that the maximum number of bits of variable-length encoded data is 20. The transmission encoder 76 in this case is composed of a variable length block 86 and a parallel/serial conversion circuit 85. In the variable length block 86, predetermined data is converted into a variable length code or a fixed length code. Then, for example, an effective data length of 5 bits is added to the parallel data of the above-mentioned variable length code or fixed length code, and 25 bits of parallel data is made into one data block. The data block is then supplied to a transmission buffer 77 as a buffer memory.

The transmission buffer 77 has a capacity of 25 bits per stage, and is constructed by providing n stages.
25 bits of parallel data is defined as one data block,
This data can be stored in block units. The variable length code or fixed length code is sequentially moved within the above-mentioned transmission buffer 77 and supplied to the parallel/serial conversion circuit 85.
5, it is converted into serial data. This serial data is sequentially output to the line.

In FIG. 27, instead of writing 25-bit parallel data at once as in FIG. 26, a variable-length code or a fixed-length code with a maximum length of 20 bits is divided into 10-bit units, and each For example, an effective data length represented by 4 bits is added to the data block to form one data block, and the data block can be stored in the memory 88 in units of data blocks. In this case, the transmission encoder 76 is composed of a variable length block 86 and a parallel/serial conversion circuit 85, and the transmission buffer 77 as a buffer memory is composed of a dividing circuit 89, a switch circuit 90, and a memory 88.

The parallel variable length code or fixed length code supplied from the above variable length block 86 is divided into the first half data DA and the second half data DB by the dividing circuit 89, and each of them is divided into 4 bits. An effective data length of 14 bits is added, and 14 bits of parallel data is made into one data block. The data blocks are then alternately supplied to the memory 88 by the switch circuit 90. The memory 88 has a capacity of 14 bits per stage, and is configured by providing n stages of this, so that 14-bit parallel data is made into one data block and can be stored in units of data blocks. be. The variable length code or fixed length code is sequentially moved within the memory 88 described above and supplied to the parallel/serial conversion circuit 85, where it is converted into serial data. This serial data is sequentially output to the line.

[0024]

[Problems to be Solved by the Invention] In the conventional technique shown in FIG. 27, the parallel-to-serial conversion circuit 85 needs to operate at a very high speed, and the access time of the transmission buffer 77 is also required to be short. . Therefore, there is a problem in that an expensive device must be used. Further, in the conventional technique shown in FIG. 28, data is supplied in parallel every 25 bits, so there is a problem that the bus width of the transmission buffer 77 is required to be 25 bits or more. In the conventional technique shown in FIG. 29, the parallel data is divided into two parts and supplied to the memory 88 of the transmission buffer 77, which increases the number of writes, making this configuration unsuitable for speeding up the problem. was there.

[0025] Accordingly, an object of the present invention is to provide a buffer memory control device that can improve the above-mentioned problems.

[0026]

[Means for Solving the Problems] In the present invention, it is determined whether or not conversion data corresponding to coefficient data exists based on a first characteristic value and a second characteristic value that can be extracted from the coefficient data. determining means; means for forming a first data block by adding a code representing a specific sequence to the first characteristic value and the second characteristic value of the coefficient data; A predetermined bit length of the conversion data set corresponding to the characteristic value of No. 2 is set as valid data, and data of the bit length of the conversion data and a predetermined code are added to the valid data to form a second data block. means for converting coefficient data not expressed by the first characteristic value and the second characteristic value into corresponding predetermined conversion data, and converting a predetermined bit length of the conversion data into valid data; At the same time, the configuration includes means for adding data of the bit length of the converted data and a predetermined code to valid data to form a third data block, and switch means for selecting each data block.

[0027]

[Operation] When it is determined that conversion data corresponding to the first characteristic value and second characteristic value of coefficient data exists, a second data block is formed, and conversion data corresponding to the coefficient data exists. If it is determined not to, a first data block is formed. Then, a third data block is formed for coefficient data that is not expressed by the above-mentioned first characteristic value and second characteristic value.

The above-mentioned second or third data block consists of valid data representing only the 8 bits on the LSB side, valid data length representing the total bit length of the data block, and a flag representing a predetermined sequence. configured. The above-mentioned data block is then written to the memory of the transmission buffer in one go. The first data block is composed of a first characteristic value and a second characteristic value of coefficient data, and a flag representing a predetermined sequence. The above-mentioned data block is then written to the memory of the transmission buffer in one go.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 3. What is described in this one embodiment corresponds to prior art transmit buffers. Before explaining the details of one embodiment, the basic idea of the present invention will be explained. The capacity of each stage of the buffer memory is set to 16 bits, and this 16 bits is the bit length of one data block, which is the unit of one write. This data block composed of 16 bits consists of an 8-bit area AR1 and a 6-bit area AR2.
, an area AR3 of a 1-bit flag FESC representing a sequence of escape codes ESC, and a 1-bit flag FSTF representing a sequence of stuffing codes.
It is divided into an area AR4. Each area AR1 mentioned above
Corresponding data or flags are written in ~AR4, respectively. As a result, the bus width of the buffer memory can be reduced, variable-length codes or fixed-length codes (hereinafter simply referred to as codes) with different bit lengths can be contained in one data block, and writing to the buffer memory can be performed only once per data block. It is possible to complete it.

In the present invention, the format of writing to the buffer memory is determined by the following classifications. (1) For codes other than conversion coefficient TC, conversion coefficient TC
Other codes include MBA, MTYPE, MVD, CBP, etc., which can be converted into the variable length codes mentioned above, and PS.
This is a fixed length code such as C or GBSC. In this case,
Escape code ESC flag FESC [="0"
], stuffing code flag FSTF [="0
”]. (1-1) When the code is 8 bits or less, the above area AR
1, write the valid data DE of the code to the area AR mentioned above.
2, write the effective data length LDE of the code.

(1-2) When the code exceeds 8 bits, write the valid data DE of the code in the above area AR1, and write the valid data length LDE of the code in the above area AR2.
Write. In this case, as will be explained below, the value [="0"] is omitted by the number of bits that is the difference between the number of bits of the effective data length LDE and 8 bits. In this specification, valid data DE is defined as follows. Generally speaking, as the word length of a variable length code increases, the MSB
Multiple “0”s are placed consecutively from the side, followed by “0”
", "1" combination continues. This "0", "1" combination has a maximum of 6 bits, so 8 bits from the LSB are written to the valid data DE and the blank area AR1. Then, from the LSB to 9 bits. “0” for bits or more up to MSB
The consecutive parts of the variable length code are omitted, and the data length of the variable length code [LSB
to MSB] is written to area AR2. For example, if the variable length code is [0000 0000 1011 10]
, the 8 bits on the LSB side [="00 10
11 10 ”] is the valid data DE in the area AR1.
The effective data length LDE is set to "14" and is written to the area AR2. When restoring this variable length code, it is known that the continuous part of omitted "0" is 6 bits (14-8=6), so after outputting 6 bits of "0" continuously, , the above-mentioned valid data DE [=[00
1011 10]] is output. In addition, fixed length codes such as PSC [="0000 0000 0000
0001 0000"], similarly, 8 on the LSB side
Bit [="0001 0000"] is valid data D
E is written in the area AR1, and the effective data length LDE is written as "20" in the area AR2. When restoring this fixed length code, the consecutive parts of omitted “0” are 1
It turns out that it is 2 bits (20-8=12), so 1
After continuously outputting two bits of "0", the above-mentioned valid data DE [="0001 0000"] is output.

(2) In the case of a variable length code of conversion coefficient TC (2-1) A variable length code corresponding to a combination of run R and level LV is defined, and the variable length code is 8 bits or less. At this time, the effective data DE of the variable length code is placed in the above-mentioned area AR1, and the effective data length LDE of the variable-length code is placed in the above-mentioned area AR2. In this case, the flag FESC of the escape code ESC [=”0
” ], stuffing code flag FSTF [=”
(2-2) When a variable length code corresponding to the combination of run R and level LV is defined, and the variable length code exceeds 8 bits, the above area A
The effective data DE of the variable length code is entered into R1, and the effective data length LDE of the variable length code is entered into the above-mentioned area AR2. This is processed in the same manner as "(1-2) When the code exceeds 8 bits" described above. In this case,
Escape code ESC flag FESC [="0"
], stuffing code flag FSTF [="0
” ].

(2-3) When the variable length code corresponding to the combination of run R and level LV is not defined, run R (6 bits) and level LV (8 bits) are set in escape code ESC (6 bits). Although it is added, the word length will be 20 bits as it is, so compression is required. In other words, a flag FESC [="1"] indicating that the escape code ESC is added to the area AR3 is set, and a run R (6 bits) and a level LV (8 bits) are added to this flag FESC and then written. . Also, at this time, a flag FSTF representing the sequence of stuffing codes is used.
is set to "0".

In the configuration of FIG. 1, MBA, MTYPE, MVD, C
BP, etc., or fixed length code PSC, GBS
Data such as C is supplied to the variable length encoder 2 via the terminal 1.

[0035] In the variable length encoding unit 2, MBA, MTYP
Variable length codes corresponding to E, MVD, CBP, etc. are formed. Effective data DE and effective data length LDE are formed based on the variable length code and fixed length code described above. For this effective data DE and effective data length LDE, flag FESC [="0"] and flag FSTF [="
0''] is added to form the third data block DT3 shown in FIG. 2. This third data block DT3 is then supplied to the terminal 3a of the switch circuit 3.

In addition, the run R obtained from the conversion coefficient TC
and a level LV are transmitted through a terminal 5 to a presence determination circuit 6 and a variable length code generation circuit (hereinafter referred to as a VLC generation circuit) 7.
, escape sequence data generation circuit [hereinafter simply referred to as E
SC data generation circuit] 8 is supplied thereto.

In the presence determination circuit 6, the run R and the level LV
It is determined whether a variable length code corresponding to the combination of is specified in the recommendation. A high level signal Sc for outputting the variable length code stored in the VLC generation circuit 7 only when specified is the VLC generation circuit 7.
and is supplied to the ESC data generation circuit 8. The VLC generation circuit 7 receives a high level signal Sc from the presence determination circuit 6.
When supplied, an integrated value n, which will be described later, is determined based on the run R and level LV supplied via the presence determination circuit 6, and an address AD is generated. The variable length code is read based on this address AD.

Address AD is calculated as follows. In the VLC generation circuit 7, 62 variable length codes defined in the recommendation and shown in FIG. 4 are stored consecutively from the first address together with the effective data length LDE. Therefore,
In order to accurately output each variable length code, a key is required to search the address AD of each variable length code. In this embodiment, the run R is used as the key to search for the address AD.
The sum of the integrated value n and the level LV is used, and this integrated value n is written in the rightmost column in FIG.

FIG. 4 shows the presence or absence of a variable length code defined in the recommendation. If a variable length code is defined, it is indicated by a "1", and if a variable length code is not defined, it is indicated by a blank. The integrated value n in FIG. 4 is the total value of "1" added in the row of each run R, that is,
This is the number of level LVs where variable length codes exist. This integrated value n is taken as the starting point of the address AD, and is also the starting point of the level LV.
is the offset from the starting point. Therefore, the integrated value n corresponding to run R0 in the first row is set to "0", and this first
The integrated value n (=15) in the run R0 in the second row is set as the integrated value n1 (=15) in the run R1 in the second row.

Address AD can be determined, for example, by adding the value of level LV as an offset to the cumulative value n of run R as the starting point of address AD. For example, in FIG. 5, if the value of run R is "7" and the value of level LV is "2", the integrated value n(
= 39), so the address AD is (39+2=4
1). Run R integrated value n and level LV
The values of are added to determine the address AD, and the variable length code is read based on this address AD.

Based on this variable length code, effective data DE and effective data length LDE are formed as described above. For this valid data DE and valid data length LDE, flag FESC [="0"] and flag FSTF [="0"
] is added to form the second data block DT2 shown in FIG. This second data block DT2 is then supplied to the terminal 4a of the switch circuit 4.

In the presence determination circuit 6, the run R and the level LV
It is determined whether a variable length code corresponding to the combination of is specified in the recommendation. If not specified, the low level signal Sc is transmitted to the VLC generation circuit 7 and the ESC.
The data is supplied to the data generation circuit 8. When the ESC data generation circuit 8 receives the low level signal Sc from the existence determination circuit 6, it applies an escape code ESC to the 6-bit run R and 8-bit level LV supplied via the existence determination circuit 6. A flag FESC [=“1”] and a flag FSTF [=“0”] are added to form the first data block DT1 shown in FIG. 2. This first data block DT1 is then supplied to the terminal 4b of the switch circuit 4.

In the presence determination circuit 6, the run R and the level LV
It is determined whether or not a variable length code corresponding to the combination is specified in the recommendation, and the switch circuit 4 is controlled based on the result. That is, when a variable length code is specified in the recommendation, the switch control signal SSW connects the terminals 4a and 4c of the switch circuit 4, and the second data block DT2 is selected and connected to the terminal 3b of the switch circuit 3. Supplied. If the variable length code is not specified in the recommendation, the switch control signal SSW connects the terminals 4b and 4c of the switch circuit 4, selects the first data block DT1, and selects the terminal 3b of the switch circuit 3. supplied to

The stuffing code generating circuit 29 generates a stuffing code, for example, an MBA stuffing code, based on a control signal supplied from a control circuit (not shown) via a terminal 28. Additionally, a flag FSTF [="1"] indicating that the data is a stuffing code is added to this MBA staff code.
A fourth data block DT4 shown in FIG. 2 is formed. This fourth data block DT4 is then supplied to the terminal 3c of the switch circuit 3. Note that the flag FESC in this case may be either "0" or "1". In addition, a flag FS indicating that the content of data written to areas AR1 and AR2 without writing the above-mentioned MBA stuff code is a stuffing code.
The fourth data block DT4 may be configured only by TF [="1"].

The connection state of the switch circuit 3 is switched by a control circuit (not shown). That is, the variable length encoder 2
When the third data block DT3 is supplied to the switch circuit 3, the terminals 3a and 3d of the switch circuit 3 are connected. Further, when the second data block DT2 is supplied from the VLC generation circuit 7 to the switch circuit 3, the terminals 3b and 3d of the switch circuit 3 are connected. and,
The first data block DT from the ESC data generation circuit 8
1 is supplied to the switch circuit 3, the switch circuit 3
Terminals 3b and 3d of are connected. Further, when the fourth data block DT4 is supplied from the stuffing code generation circuit 29 to the switch circuit 3, the terminals 3c and 3d of the switch circuit 3 are connected.

In this way, the output of any one of the first to fourth data blocks DT1 to DT4 is selected and supplied to the buffer memory 20 via the switch circuit 3 and the terminal 37. A data block composed of areas AR1 to AR4 is supplied to the buffer memory 20, and a write process is performed at one time.

Flags and codes are sequentially read out from the buffer memory 20 by a control circuit (not shown) and supplied to the line data generation section 40. The line data generating section 40 reproduces the original code based on the flag and code read from the buffer memory 20 and outputs it to the line.

From the buffer memory 20, areas AR1 to
The data of AR4 is read out in data blocks and supplied to the code selection circuit 41. In the code selection circuit 41, the data in the area AR4 is read out as a flag FSTF, and the data in the area AR3 is read out as a flag FESC. Further, the data read from the areas AR1 and AR2 are processed according to their respective characteristics based on the above-mentioned flags FESC and FSTF.

As shown in FIG. 2, the flag FESC
[="1"], and in the case of the first data block DT1 represented by the flag FSTF [="0"], the area A
The data in R1 is set to an 8-bit level LV, and the data in area AR2 is set to a 6-bit run R. and,
The above-mentioned level LV and run R are supplied to the register 42. The escape code ESC is stored in this register 42 in advance.
are stored, and are read out from the register 42 in the order of escape code ESC, run R, level LV,
The data is supplied to the terminal 43b of the switch circuit 43 as serial data. Further, since the flag FESC [=“1”] is from the code selection circuit 41, a switch control signal SSW2 is supplied to the switch circuit 43, and the connection state of the switch circuit 43 is controlled. That is, in this case, since the flag FESC [="1"],
Serial data supplied from the register 42 is selected and supplied to the terminal 50a of the switch circuit 50.

As shown in FIG. 2, the flag FESC
[="0"], in the case of the second data block DT2 or the third data block DT3 represented by the flag FSTF [="0"], the valid data D of the area AR1
E is supplied to the parallel/serial conversion circuit 44 and converted into serial data, and at the same time, the effective data length LDE of the area AR2 is supplied to the subtraction counter 45.

From the subtraction counter 45, the effective data length L
The value of DE is supplied to one terminal of comparator 46, and
A threshold Th1 [="8"] representing the bit length of the area AR1 is supplied from the terminal 47. Comparator 4
6, the effective data length LDE and the threshold T
A comparison is made with h1. If the effective data length LDE is larger than the threshold Th1 [LDE>Th1], for example, a high-level switch control signal SSW1 is output, terminals 48a and 48c of the switch circuit 48 are connected, and the signal is output via the terminal 49. The value supplied by [=”0”
] is supplied to the terminal 43a of the switch circuit 43 via the switch circuit 48.

The value [=
"0"] is selected once, the subtraction counter 45 decrements the value of the effective data length LDE. This decremented effective data length LD
E is again compared with the threshold Th1 in the comparator 46. The comparison of the effective data length LDE and the threshold Th1 in the comparator 46, the output of the value [="0"], and the decrement of the effective data length LDE are repeated until the value of the effective data length LDE becomes equal to or less than the threshold Th1. be done. Therefore, from the value of the effective data length LDE to the predetermined value [
="8"] is subtracted from the value from terminal 49 [=
"0"] is connected to the switch circuit 4 via the switch circuit 48.
The signal is supplied to the terminal 43a of No. 3.

In comparing the effective data length LDE in the comparator 46 with the above-mentioned threshold Th1, if the effective data length LDE is smaller than the threshold Th1 [LDE<Th1], for example, the low level The switch control signal SSW1 is output, terminals 48b and 48c of the switch circuit 48 are connected, and the serial valid data DE supplied from the parallel-serial conversion circuit 44 is sent to the terminal 43 of the switch circuit 43 via the switch circuit 48.
supplied to a.

Further, from the code selection circuit 41, a flag FESC [="0"], a flag FSTF [="0"]
" ], the switch control signal SSW2 is supplied to the switch circuit 43, and the connection state of the switch circuit 43 is controlled. That is, in this case, the switch control signal SSW2 is supplied to the switch circuit 43, and the connection state of the switch circuit 43 is controlled.
The data supplied as serial data via 8 is selected and supplied to the terminal 50a of the switch circuit 50.

As shown in FIG. 2, the flag FSTF
Fourth data block DT4 represented by [="1"]
In this case, the high level signal S41 is the AND gate 5
2. Then, the signal S41 is the AND gate 5
If a stuffing code insertion request signal (hereinafter simply referred to as the insertion request signal) SIN is supplied at a high level through the terminal 53 while the stuffing code insertion request signal SIN is supplied at a high level to A high level signal is supplied to the switch circuit 50 via the gate 52, and the connection state of the switch circuit 50 is controlled. That is, in this case, since the flag FSTF [="1"],
Terminals 50b and 50c of switch circuit 50 are connected. As a result, the stuffing code from the stuffing code generation circuit 54 is selected by the switch circuit 50 and output as serial data to a line (not shown) via the terminal 56.

On the other hand, as shown in FIG.
In the case of the first to third data blocks DT1 to DT3 represented by TF [="0"], the low level signal S4
1 is supplied to the AND gate 52, the insertion request signal SIN is supplied from the AND gate 52 to the switch circuit 50 at a low level, and the connection state of the switch circuit 50 is controlled. That is, in this case, the flag FSTF [=
“0”], the terminal 5 of the switch circuit 50
0a and 50c are connected, and data from one of the first to third data blocks DT1 to DT3 from the switch circuit 43 is selected by the switch circuit 50 and sent as serial data to a line (not shown) via the terminal 56. Output.

[0057] In this way, in the case of variable length codes and some fixed length codes, as in the second or third data blocks DT2 and DT3, the effective data DE of only 8 bits on the LSB side and the code The effective data length LDE representing the total bit length is stored separately, and when restoring the code, the effective data DE and the effective data length LDE are read out from the buffer memory 20, and "0" that was omitted during storage is added to the effective data DE. Since codes with different effective data lengths LDE can be stored in one data block defined by a predetermined bit length without spanning multiple data blocks, codes with different effective data lengths LDE can be stored in one data block defined by a predetermined bit length. Data width can be reduced to the minimum necessary. As a result, both the amount of data and the number of times of writing in one write to the buffer memory 20 can be reduced. As a result, buffer memory 2
0 can be used more efficiently. Also, the conversion coefficient T
For combinations of C run R and level LV for which variable length codes are not specified in the recommendation, an escape code ESC is added as a flag FESC as in the first data block DT1. When inserting a stuffing code, the same effect as described above can be obtained by adding a stuffing code insertion request as a flag FSTF as in the fourth data block DT4.

[0058]

According to the buffer memory control device according to the present invention, codes with different effective data lengths can be stored in one data block defined by a predetermined bit length without spanning over a plurality of data blocks.
This has the effect that the data width of the data block can be reduced to the necessary minimum. This has the effect of reducing both the amount of data and the number of times of writing in one write to the buffer memory. As a result, there is an effect that the usage efficiency of the buffer memory 20 can be improved.

Further, there is an effect that high speed is not required for accessing the buffer memory, there is no need to use an expensive device, and there is no need for a buffer memory having a large bus width. This has the effect of being suitable for speeding up without increasing the number of writes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a buffer memory control device.

FIG. 2 is an explanatory diagram showing the contents of a data block.

FIG. 3 is a block diagram of a line data generation section.

FIG. 4 is a schematic diagram showing locations where runs and levels exist.

FIG. 5 is a block diagram of a video codec.

FIG. 6 is an explanatory diagram showing a data format of a frame layer.

FIG. 7 is a schematic diagram showing the arrangement of GOBs in a frame.

FIG. 8 is a schematic diagram showing the arrangement of GOBs in a frame.

FIG. 9 is an explanatory diagram showing the data format of the GOB layer.

FIG. 10 is a schematic diagram showing the arrangement of macroblocks in a GOB.

FIG. 11 is an explanatory diagram showing the data format of the MB layer.

FIG. 12 is a schematic diagram showing a variable length code of MBA.

FIG. 13 is a schematic diagram showing a variable length code of MTYPE.

FIG. 14 is a schematic diagram showing a variable length code of MVD.

FIG. 15 is a schematic diagram showing a CBP variable length code.

FIG. 16 is a schematic diagram showing the arrangement of blocks in a macroblock.

FIG. 17 is a schematic diagram showing the arrangement of blocks in a macroblock.

FIG. 18 is a schematic diagram showing the arrangement of blocks in a macroblock.

FIG. 19 is a schematic diagram showing the transmission order of block transform coefficients TC and EOB.

FIG. 20 is a schematic diagram showing the transmission order of transform coefficients in a block.

FIG. 21 is a block diagram of a transmission encoder showing generation of first and second characteristic values from transform coefficients.

FIG. 22 is a schematic diagram showing variable length codes in transform coefficients.

FIG. 23 is a schematic diagram showing a 6-bit fixed length code of a run.

FIG. 24 is a schematic diagram showing an 8-bit fixed length code of levels.

FIG. 25 is a block diagram illustrating a state in which a code and effective data length are written to a conventional transmission buffer.

FIG. 26 is a block diagram illustrating a state in which a code and effective data length are written to a conventional transmission buffer.

FIG. 27 is a block diagram illustrating a state in which a code and effective data length are written to a conventional transmission buffer.

[Explanation of symbols]

2 Variable length encoder 3, 4 Switch circuit 6 Existence determination circuit 7 Variable length code generation circuit 8 Escape sequence data generation circuit TC Transform coefficient R Run LV Level DT1, DT2, DT3, DT4 Data block D
E Valid data LDE Valid data length MBA Macroblock address MTYPE Type information MVD Motion vector information CBP Significant block pattern PSC Frame start code GBSC GOB start code FESC, FSTF Flag

Claims (1)

[Claims] 1. Discrimination means for determining whether or not conversion data corresponding to the coefficient data exists based on a first characteristic value and a second characteristic value that can be extracted from the coefficient data; means for forming a first data block by adding a code representing a specific sequence to the first characteristic value and the second characteristic value of the coefficient data; A predetermined bit length of the correspondingly set converted data is set as valid data, and data of the bit length of the converted data and a predetermined code are added to the valid data to form a second data block. means, converting the coefficient data not expressed by the first characteristic value and the second characteristic value into corresponding predetermined conversion data, and making a predetermined bit length of the conversion data valid data; Further, the method is characterized by comprising means for adding data of the bit length of the converted data and a predetermined code to the valid data to form a third data block, and switch means for selecting each of the data blocks. Buffer memory control device.