JPH0423637A - Data receiver - Google Patents

Abstract

PURPOSE:To eliminate the need for troublesome phase adjustment between data clocks by using a clock resulting from delaying a regular clock for a prescribed time as a data read clock when a data and a data and clock are in contention. CONSTITUTION:Suppose that a shift register 4 reads a data in a rising timing of a clock CL, when a clock CL rises for a 1st pulse period, the both are in contention and the possibility of occurrence of a read error exists. Then a clock resulting from delaying a regular clock for a prescribed time is used as a data read clock. Moreover, when the clock CL rises for a 2nd pulse period, since no contention takes place, the clock CL is used as the read clock as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data receiving device, and particularly to a serial data receiving device.

[Prior Art] FIGS. 3 to 5 are block diagrams showing conventional examples of this type of data receiving apparatus.

FIG. 3 shows the case of a two-wire system, in which data D and clock CL transmitted via cable 31 are input to shift register 33. For example, at the rising timing of clock CL, data D is input to shift register 33. be read. In this case, it is necessary to insert a phase adjuster 32 into the clock line and adjust the phase of the clock while observing it with an oscilloscope or the like so that the optimal phase relationship between the data and the clock is maintained.

FIG. 4 shows an example of a one-wire system in which the cable 31a transmits only data. In this example, PLL (Phase 1ocked 1oop
) type clock generator 34 generates a read clock. In this case, the steady phase error adjuster 3
5 to adjust the steady phase error of the clock generator 34,
It is necessary to optimally set the data and clock phases.

Further, in this device, phase fluctuation occurs depending on the frequency of data switching, so a PLL circuit with good transient response is required.

FIG. 5 shows an example in which the read clock is generated by the PLL clock generator 34 in a one-wire system similar to that in FIG. A correction circuit 36 is also used.

[Problems to be Solved by the Invention] With the conventional technology shown in Figure 3, it was necessary to make adjustments to optimize the phase relationship between the data and the read clock while observing the oscilloscope, which required a lot of man-hours. . In addition, in the case of a one-wire system, manual adjustment is required, and
Since a PLL type clock generator with good responsiveness is required, the device becomes expensive, and a highly accurate error correction circuit is also required, resulting in high costs.

[Means for Solving the Problems] A data receiving device according to the present invention automatically detects whether or not there is a competitive relationship between a data change point and a reading edge of a clock for reading data, and detects whether or not there is a competitive relationship between a data change point and a reading edge of a clock for reading data. In some cases, the regular clock delayed by a certain period of time is used as the data reading clock, and in other cases, the regular clock is used as it is as the data reading clock.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a timing chart showing its operating state.

As shown in FIG. 1, the receiving device of this embodiment includes delay elements 5.6.7, EXOR gates 8.10, EXNOR gates 9, AND gates 11.14.15, and OR gates 12.
, a conflict detection circuit 1 composed of an inverter 13, a NOR gate 16, and a D-type flip-flop 17;
A clock delay circuit 2 composed of delay elements 18, 19, and an inverter 20. A clock switching circuit 3 consists of an AND gate 21, 22 and an OR gate 23, and switches between a clock CL and a delayed clock DCL based on a clock switching signal S5 of the conflict detection circuit 1, and a clock switching circuit 3 reads the output clock OCL from the clock switching circuit 3. a shift register 4 that reads data D as a clock;
Equipped with:

Note that this embodiment can be applied to either a one-wire system or a two-wire system. Therefore, in the case of a one-wire system, the clock is provided by a clock generator.

Next, the operation of this embodiment will be explained with reference to the timing chart of FIG.

In the conflict detection circuit 1, data D is transmitted through delay elements 5, 6, .
7, it is delayed by three stages. Each delay signal and data D are connected to EXOR gate 8, EXNOR gate 9 and EXO
By passing through the R gate 10, signals S1, S2, and S3 are obtained from each gate. These signals are AND
The gate 11 and the OR gate 12 synthesize the signal S4. Signal S4 becomes two consecutive pulses from the change point of data D, the first pulse represents an interval where there is a possibility of conflict between the clock and data, and the second pulse represents a safe interval where there is no risk of conflict. is occupying.

If the shift register 4 reads data at the rising timing of the clock CL, when the clock CL rises during the first pulse period, there is a conflict between the two, and a read error may occur. Therefore,
In this embodiment, a clock obtained by delaying the clock CL by a certain period of time is used as the reading clock. Further, when the clock CL rises during the second pulse period, there is no fear of conflict, so the clock CL is used as it is as the reading clock. In sections other than the two pulse periods, there is no possibility of conflict, but in order to prevent clock CL and delayed clock DCL from frequently switching due to jitter between data D and clock CL, switching of clock CL is prohibited. shall be.

A circuit consisting of an inverter 13, an AND gate 14, 15, a NOR gate 16, and a D-type flip-flop 17 generates a lock switching signal S5 from the signal S1.4 and the clock CL, which is necessary for performing the above operations. be.

When the clock CL rises in an interval other than the pulse of the signal S4 (low level interval), the inverted signal of the summer output of the D-type flip-flop 17 is input to the D terminal, so the output of the D-type flip-flop 17 is A certain clock switching signal S5 does not change. When the clock CL rises during the first pulse period of the signal S4, the signal Sl
Since the inverted signal (high level at this time) is input to the D terminal of the D-type flip-flop 17, the clock switching signal S5 becomes low level. Furthermore, signal S4
When the clock CL rises during the second pulse period of becomes.

In the clock switching circuit 3, the clock switching signal S5
When the clock switching signal S5 is at a low level, the delayed clock DCL is set at a low level, and when the clock switching signal S5 is at a high level, the clock C is set at a low level.
L is output as the output clock OCL.

Shift register 4 receives output clock OCL and reads data D. That is, when the clock switching signal S5 is at a low level (when the reading timing of the clock CL coincides with the data change time), the shift register 4 reads data using the delayed clock DCL, and when the clock switching signal is When the level is high (when the reading timing of the clock CL is within the safe interval with respect to the data change point), it is the normal clock CL.
The reading is performed by

In the case of the two-wire system, when the clock switching signal is at a low level, there is a possibility that the rise of the clock CL is before the contention period and the rise of the delayed clock falls within the contention period. If there is such a possibility, it is necessary to set the contention interval to a certain extent and to delay the data D at point A in FIG. 1 using a delay circuit. Further, the clock switching circuit 3 switches the signal S after the clock CL is input.
5 switches, a "whisker" will appear in the output. To avoid this, it is necessary to insert a short-time delay circuit at point B in FIG.

As explained above, according to the present invention, reading errors can be corrected by simply adding a relatively simple circuit, without going through complicated adjustment steps, and without using an expensive lock generator or error correction circuit. Therefore, it is possible to obtain a data receiving device that does not cause this problem.

[Effects of the Invention] As explained above, the present invention detects whether or not data and a data read clock are in a competitive relationship in a data receiving device, and when they are in a competitive relationship, delays the regular clock by a certain period of time. According to the present invention, contention between the data and the read clock can be reliably avoided by simply adding a small-scale circuit. Therefore, according to the present invention, there is no need for complicated phase adjustment between data clocks, and furthermore, it is possible to use a simple PLL type clock generator and an error correction circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
Timing charts for explaining the operation and FIGS. 3 to 5 are block diagrams of conventional examples, respectively. 1...Conflict detection circuit, 2...Clock delay circuit, 3...Clock switching circuit, 4...Shift register, 5.6
．． 7.18.19...Delay element, 8.10
...EXOR gate (exclusive OR gate), 9...EXNOR gate (exclusive NOR gate), 11.14.15
．． 21.22...AND gate, 12.2
3...OR gate, 13.20...Inverter, 16...NOR gate,
17...D type flip-flop, D...
...Data, CL...Clock,
DCL...delay clock, OCL...
...output clock, S1 to S4...signal,
S5...Clock switching signal.

Claims (3)

[Claims] (1) In a data receiving device that reads serially transferred data in synchronization with a clock, when there is a conflict between the data read edge of the clock and the data change time, a clock delayed by a certain period of time is used. The data receiving device is characterized in that the data is read using the clock when this is not the case. (2) A conflict detection circuit that detects whether there is a conflict between the data read edge time of the clock and the data change time; a clock delay circuit that delays the clock by a predetermined time; a clock switching circuit which outputs the delayed clock when the conflict detection circuit detects a conflict and outputs the regular clock when the conflict detecting circuit detects a conflict; A data receiving device that includes a shift register that reads data that is serially transferred at a timing. (3) The conflict detection circuit generates a first level signal when the edge of the clock exists within a conflict interval that includes a data change point, and generates a signal at a first level in a safe interval delayed by a certain period of time from the conflict interval. when it exists within the second
3. The data receiving apparatus according to claim 2, wherein the data receiving apparatus generates a signal having a level of .