JPH04236514A - Pulse signal generating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal generating circuit, and is particularly suitable for use in improving the withstand voltage of each transistor constituting the circuit.

0002

[Background Art] In circuits that handle digital signals, a pulse signal generation circuit is used to generate a pulse signal delayed from an input pulse signal, or to generate a pulse signal whose waveform is shaped by an input signal. are used in various ways. FIG. 3 shows a conventional example of a pulse signal generation circuit that sequentially transfers an input pulse signal VST according to a clock signal VCK and an inverted clock signal VCKX, and generates a pulse signal delayed by a predetermined timing from the input signal.

The circuit of FIG. 3 shows a shift register composed of a data transfer section 20, a NAND gate 21, an inverter 22, etc., and is used as a vertical shift register for, for example, an LCD. The data transfer section 20
is composed of a D-type flip-flop made of MOS transistors, and each output VA1, VA2 is output in synchronization with the rising edge of the clock signal VCK and the inverted clock signal VCKX.

Further, as shown in the time chart of FIG. 4, a NAND gate 21 is provided to form signals VB1 and VB2 by extracting a common portion of high level "H" from the pair of outputs VA1 and VA2. There is. On the other hand, the inverter 22 inverts the NAND output signals VB1 and VB2 given from the NAND gate 21 and converts them into shift register output signals VC1 and VC2.
It is provided for outputting to the outside as a.

[0005]

Generally, in LCDs, particularly active matrix type LCDs, NMOS transistors are often used as pixel transistors. Therefore, in the case of this active matrix type LCD, the gate signal is required to have a voltage greater than the pp value of the input video signal. For this reason, a relatively high voltage such as 14 to 18 [V] is used as the power supply voltage VDD of the vertical shift register shown in FIG. 3, for example.

[0006] Since such a high voltage is applied, sufficient consideration must be given to the withstand voltage of each circuit element constituting the shift register. In particular, TFT (Thin
In the case of film transistors, the withstand voltage between terminals such as gate and drain, gate and source, and drain and source is lower than that of bulk transistors configured on a substrate, so when TFTs are used as circuit elements. However, there is a problem in that when a high power supply voltage VDD as described above is applied, the element may be destroyed, resulting in a decrease in reliability.

[0007] In order to solve such problems, ■TF
Countermeasures such as increasing the gate film thickness of T or (2) reducing the amplitude of the input signal may be taken. However, if the above-mentioned measure (2) is taken, the threshold voltage Vth becomes large, so there is an inconvenience that a high power supply voltage VDD is required. Moreover, if the measure (■) is taken, the amplitude of the output signal will also become small, and as mentioned above, the LCD
When used as a vertical shift register for commercial purposes, there was a problem in that the contrast deteriorated.

In view of the above-mentioned problems, the present invention substantially improves the withstand voltage by reducing the voltage applied to each element constituting the pulse signal generation circuit, and also reduces the amplitude of the voltage applied to each element. The purpose of the present invention is to output a pulse signal having the following characteristics.

[0009]

[Means for Solving the Problems] The pulse signal generation circuit of the present invention is a first signal processing circuit to which one voltage obtained by dividing a predetermined voltage into two is applied as a driving voltage when processing an input pulse signal. and the input pulse signal is the first pulse signal.
a second signal processing circuit which is provided in common with the signal processing circuit and which is provided with the other voltage obtained by dividing the predetermined voltage into two as a drive voltage when processing the input pulse signal; A PMOS transistor whose gate is given one voltage that is divided into two, and an NMOS transistor whose gate is given the other voltage that is obtained by dividing the predetermined voltage into two.
A CMOS transistor comprising a transistor, the output signal of the first signal processing circuit being applied to the source of the PMOS transistor, and the output signal of the second signal processing circuit being applied to the source of the NMOS transistor. A transistor is provided, and an output signal subjected to predetermined processing by the first and second signal processing circuits is obtained from the output terminal of the CMOS transistor.

0010

[Operation] Two pulse signal processing circuits are provided in parallel that perform predetermined processing on the input signal and generate a signal delayed by a predetermined timing from the input signal, and these signal processing circuits perform the predetermined processing. The applied pulse signals are synthesized to generate a desired output pulse signal. As a result, by operating the above two signal processing circuits at a low operating voltage, it is possible to solve the problem of withstand voltage of the circuit elements that make up these signal processing circuits, and to generate output signals with large amplitudes. It becomes possible.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a pulse signal generation circuit showing an embodiment of the present invention. As is clear from FIG. 1, the pulse signal generation circuit 1 of this embodiment has an input pulse signal S
in as clock signal VCK and inverted clock signal VC
It is configured as a shift register that transfers according to KX, generates a pulse signal delayed by a predetermined timing from the input pulse signal Sin, holds it for a predetermined period, etc., and transfers the input pulse signal Sin. The circuit for this purpose is comprised of two systems, a first signal processing circuit A and a second signal processing circuit B.

Both of the first signal processing circuit A and the second signal processing circuit B are constructed as a circuit block having a data transfer section 2 and a signal output circuit 3 as one unit, and the circuit configurations themselves are as follows. Both are the same. However, the operating voltages of the first signal processing circuit A and the second signal processing circuit B are different, and the operating voltage of the first signal processing circuit A is [from ground level Gnd to power supply voltage VDD/2]. and the second signal processing circuit B
is driven by an operating voltage of [power supply voltage VDD/2 to power supply voltage VDD].

In this way, by reducing the operating voltage for driving each signal processing circuit A, B to half of the power supply voltage VDD, the MOS forming these signal processing circuits A, B
The magnitude of the maximum voltage applied between any nodes of the transistor can be reduced to half the power supply voltage VDD. Therefore, in the case of the pulse signal generation circuit of this embodiment, the problem of breakdown voltage of circuit elements can be completely solved.

However, the operating voltage is set to the power supply voltage VDD.
If it is halved, a problem arises in that the amplitude of the signal output therefrom is also half of the power supply voltage VDD. That is, the amplitude of the first output signal S1 output from the signal output circuit 3 of the first signal processing circuit A is [ground level Gnd to power supply voltage VDD/2]. Similarly, the second
The second output signal S2 output from the signal processing circuit B becomes [power supply voltage VDD/2 to power supply voltage VDD].

Therefore, in this embodiment, a signal synthesis circuit 4 is provided to synthesize S1 and S2 output from these signal processing circuits A and B, respectively, and
An output pulse signal Sout having a large amplitude of nd to power supply voltage VDD is formed.

As shown in FIG. 1, this signal synthesis circuit 4 includes a PMOS transistor mp and an NMOS transistor m.
The power supply voltage V is applied to the gate of the PMOS transistor mp.
DD/2 is applied, and a ground level voltage 0 is applied to the gate of the NMOS transistor mn. Further, the second output signal S2 is applied to the source of the PMOS transistor mp, and the NMOS transistor m
A first output signal S1 is given to n.

Therefore, this signal synthesis circuit 4 operates as shown in Table 1 below. Table 1 As shown in FIG. 2, during the period t0 to t1, the voltage applied to the source of the PMOS transistor mp is the power supply voltage VDD/
2, the voltage applied to the source of the NMOS transistor mn is the ground level Gnd. Therefore, Table 1
In this case, the PMOS transistor mp
turns off, and NMOS transistor mn turns on, so the output pulse signal Sout at this time is “L”
level.

During the period t1 to t2, the voltage applied to the source of the PMOS transistor mp is equal to the power supply voltage VD.
D, and the voltage applied to the source of the NMOS transistor mn becomes the power supply voltage VDD/2. Therefore, in this case, the PMOS transistor mp is turned on and the NMOS transistor mn is turned off, so that the output pulse signal Sout has an amplitude of "H" level of VDD. In addition, during the period t2~, the PMOS transistor m
The voltage applied to the source of p is the power supply voltage VDD/2,
The voltage applied to the source of the NMOS transistor mn is the ground level Gnd. Therefore, in this case, the PMOS transistor mp is turned off and the NMO transistor mp is turned off.
Since the S transistor mn is turned on, the output pulse signal S
out becomes the "L" level again.

Since the pulse signal generation circuit of this embodiment operates in this manner, the PMOS transistors mp and NM
In the OS transistor mn, the voltage applied between arbitrary nodes can be reduced to a maximum of VDD/2, and even in transistors with low breakdown voltages, problems with breakdown voltage can be eliminated. Note that normally |VGS|=VDD, but in this embodiment, |VGS|=VDD/2, so a large drive current cannot be obtained. However, since the gate line load is light and only needs to be charged and discharged at a low speed (~1 μs), it is not necessary to use the full capacity, and the small sizes of the PMOS transistor mp and the NMOS transistor mn are sufficient.

[0020]

[Effects of the Invention] As described above, the present invention provides two parallel pulse signal processing circuits that delay an input signal by a predetermined timing and output the signal, and performs the predetermined operation of these signal processing circuits. A signal synthesis circuit is provided which processes each of the input signals by driving at an operating voltage lower than the above voltage and synthesizes the outputs of the signal processing circuit, and predetermined processing is performed by the two signal processing circuits. Since the output pulse signals having the desired amplitude are synthesized by the signal synthesis circuit, the problem of withstand voltage of the circuit elements constituting the two signal processing circuits can be solved. At the same time, an output signal with a large amplitude can be generated. Therefore, the withstand voltage of the circuit element can be substantially improved without changing the process, and the reliability of the pulse signal generation circuit configured using circuit elements with low withstand voltage can be improved.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a pulse signal generation circuit showing one embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of each part.

FIG. 3 is a circuit diagram showing an example of a conventional pulse signal generation circuit.

FIG. 4 is a waveform diagram for explaining the operation of each part of a conventional pulse signal generation circuit.

[Explanation of symbols]

1 Pulse signal generation circuit 2 Data transfer section 3 Signal output circuit 4 Signal synthesis circuit A First signal processing circuit B Second signal processing circuit Sin Input pulse signal S1 First output signal S2 Second output signal Sout Output pulse signal

Claims (1)

[Claims] 1. A first signal processing circuit to which one voltage obtained by dividing a predetermined voltage into two is applied as a driving voltage when processing an input pulse signal; As well as being given in common with the circuit,
a second signal processing circuit to which the other voltage obtained by dividing the predetermined voltage into two is applied as a drive voltage when processing the input pulse signal; and a PMOS transistor whose gate is provided with one voltage obtained by dividing the predetermined voltage into two. , and an NMOS transistor whose gate is supplied with the other voltage obtained by dividing the predetermined voltage into two, the output signal of the first signal processing circuit is supplied to the source of the PMOS transistor, and the source of the NMOS transistor is supplied with the output signal of the first signal processing circuit. a CMOS transistor configured to receive an output signal of the second signal processing circuit;
and a pulse signal generation circuit, wherein an output signal subjected to predetermined processing by a second signal processing circuit is obtained from an output terminal of the CMOS transistor.