JPH04238559A - Competition processing control system - Google Patents

Abstract

PURPOSE:To offer a competition processing system for allocating efficiently utilization requests from plural circuits with regard to a competition processing control system for managing the same resources by a request and a condition from plural circuits in the system for utilizing the same resources with plural circuits. CONSTITUTION:In the system for sharing the same resources of a memory, etc., this system is constituted so that a request discriminating means 2 discriminates a utilization condition with respect to an access request and discriminates whether its request is received or not, and when it is discriminated that it is unnecessary to receive it, a switching instruction is issued to a switching means 3, and by this switching instruction, a request from a second circuit is received.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system in which a plurality of circuits use the same resource, and more particularly to a contention processing control method for managing the same resource according to requests and conditions from a plurality of circuits.

0002

2. Description of the Related Art In a system in which a plurality of circuits use the same resource, the access method to the resource may differ depending on the circuit. For example, there is a case where an SRAM is shared by a CPU and a circuit formed by another LSI or the like. In such a system, the LSI periodically accesses its SRAM, but the CPU accesses it randomly (only when requested by a program). In such a system, it is generally necessary to adjust access to the resources as effectively as possible (without wasting time). For example, if the above-mentioned LSI is an LSI for transmitting and receiving data to a line or for controlling the transmission and reception of data to a line, in order to transmit data in specific time units, an access time for transmission is always provided in one transmission/reception operation period, and then A plurality of access periods are set for the CPU and further for reception, and an access period is set for each of the CPUs. That is, transmission, CPU, reception, etc. are repeated within one operation unit of a circuit such as an LSI.

Conventionally, the time (S) required for periodic access is allocated based on the minimum unit of access to a resource, s, and the remaining time is allocated to random access.

0004

SUMMARY OF THE INVENTION In a system using the above-mentioned SRAM or the like, a waiting time is provided for random access from a CPU or the like in addition to the time necessarily required by an LSI or the like. For this reason, a waiting time is provided for random access from the CPU, which reduces the number of program executions and causes a reduction in processing performance.

An object of the present invention is to provide a contention processing control method for efficiently allocating usage requests from a plurality of circuits in a system that shares the same resource.

[0006]

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. The present invention is directed to a system that shares the same resource (1) that operates in response to access from a plurality of circuits. For example, the same resource (1) is memory.

[0007] In response to an access request from the first circuit, the element determining means 2 determines whether the requested element satisfies usage conditions. For example, the first circuit is a transmission/reception data processing circuit that processes data from a line.

When the element discriminating means 2 determines that the usage conditions are not satisfied, the switching means 3 accepts the request from the second circuit even if the time is allocated to the first circuit. The same resource is switched to the second circuit.

[0009]

[Operation] In response to an access request from the first circuit, the element determining means 2 determines the usage conditions of the previous accesses, and determines whether or not to accept the requested access. When it is determined that there is no need to accept it, a switching instruction is given to the switching means 3. In response to this switching instruction, a request from the second circuit is accepted, and the same resource 1 operates in response to the access request from the second circuit.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to the drawings. FIG. 2 is a block diagram of the first embodiment of the present invention. In the first embodiment, competition between the CPU and the transmission/reception data processing section in the line control device is controlled. The CPU (for example, Intel 80186) 10 provides a program area and a data area in the SRAM, and accesses the SRAM 1 via the access control unit 11.
Access 2. Note that the CPU 10 randomly accesses and executes programs in the SRAM 12.

[0011] Here, when the SRAM 12 is assumed to be a shared asset,
There are cases where requests from the transmission/reception data processing unit 13 must be accepted preferentially. For example, when a request to send data occurs, if the request is not responded to immediately, the data may be lost and the system may go down.

For this reason, as shown in the allocation timing diagram of FIG. 3, time obtained by dividing one transmission/reception operation time T is allocated to each circuit. First, the transmission is performed at time T1, the CPU is transmitted at time T2, and the times T3, T4, T5,
Reception is assigned to times T6 and T7, and CPU is assigned to times T8 and T9.

In a normal state, that is, when received data has already been added, the timing represented by this assigned timing is used. On the other hand, as shown in FIG. 4, when the access control unit 11 determines that the received data (2), that is, the received data at the time T3 which is the reception slot, does not satisfy the usage conditions and the time slots T6 and T7 are not in the reception state, the access control unit 11 controls the CPU 10. S.R.A.
Assign M12. In addition, 1 time slot S is SRA
This is the minimum unit time for accessing M. As a result, in the past, devices used in time slots were fixedly allocated in specific units of time, but as in the present invention, by changing the time allocated depending on factors such as receiving conditions, the efficiency of use of the devices can be increased. be able to.

FIG. 5 is a block diagram of a second embodiment of the present invention. The access control unit 11 in FIG. 2 described above is a CPU.
The CPU access processing unit 21 for access from
It consists of an I access processing section 22. These two access processing units 21 and 22 are never active at the same time.

When a request from a line or the like is applied to the transmission/reception data processing section 23 and an access request is generated, an element corresponding to the request is outputted to the fetch clock generation section 24 . The fetch clock generation unit 24 determines the element A added from the transmission/reception data processing unit 23, and determines whether or not to allocate a time corresponding to the element. If it is an element that does not need to be assigned, C
Switch to PU.

Conventionally, element A was not used and access control was not switched. However, according to the present invention, element A is clarified and switched with the access control unit, so that the same resources can be used effectively. Moreover, this speeds up the CPU's response to random access, making it possible to speed up the processing time.

[0017]

[Effects of the Invention] As described above, according to the present invention, the same resources can be used effectively and the waiting time for requests from the CPU can be limited, without reducing the processing capacity of the CPU. , control processing can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention.

FIG. 3 is an allocation timing diagram.

FIG. 4 is an allocation timing diagram in condition setting.

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

[Explanation of symbols]

1... Same resource 2... Element discrimination means 3...Switching means

Claims (2)

[Claims] Claim 1: In a system that shares the same resource (1) that operates in response to access from a plurality of circuits, a first
element determination means (2) for determining whether the element of the request satisfies the usage conditions in response to an access request from the circuit of
), and when the element determining means (2) determines that the usage conditions are not satisfied, the request from the second circuit is accepted even if the time allocated to the first circuit is Switching means (3) for switching the same resource (1) to the circuit of
A contention processing control method characterized by: 2. The same resource (1) is a memory, the first circuit is a transmitting/receiving data processing circuit that processes data from or to the line, and the element determining means (2) is a memory. 2. The contention processing control system according to claim 1, wherein when the data from the transmission/reception data processing circuit does not satisfy the usage conditions, the pre-allocated time is switched to the second circuit.