JPH0423860B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a carrier phase control device, in particular, for receiving and demodulating a quadrature amplitude modulated or phase modulated line signal, and in initial training, the carrier wave phase control device receives and demodulates a line signal that is quadrature amplitude modulated or phase modulated. The present invention relates to a carrier phase control system in a demodulator using alternating sequences of two symbols in position.

In general, a modem/demodulator (MODEM) in a transmitting/receiving device that transmits and receives data signals such as facsimile signals executes a predetermined training sequence prior to receiving the data signal, performs carrier detection and initial timing setting, and performs automatic gain control circuit. (AGC) and automatic equalizer are adapted to the signal level and line characteristics to achieve convergence. For example, in the International Telegraph and Telephone Consultative Committee (CCITT) Recommendations V.27bis/ter and V.29, the training sequence is activated by an alternating repeated sequence of binary symbols, i.e., alternation, in the first stage of initial training. . The transmitting/receiving device initializes the timing as early as possible in this training sequence, and thereafter quickly and stably converges the system including the phase-locked loop (PLL) for timing extraction and carrier detection, and the automatic equalizer.

In the 9600 bit/s mode specified in CCITT Recommendation V.29, segment 2 of the training sequence uses the complex plane XY as shown in Figure 1.
Alternating sequences of the two symbols A and B of the above arrangement are used, and in segment 3 a pseudo-random sequence of symbols C and D is used.

An example of a carrier phase control method in the prior art will be explained with reference to FIG. Multiplier (MLT) 10
The output r' of the equalizer input to is the equalized signal. recommendation
V.29 uses quadrature amplitude modulation, so
The signal r' in the baseband is a complex number. Therefore, the signals r and t in the baseband at the input and output of the quantizer 12 and the divider (DIV) 1
4, the output signal r/t is also a complex signal.

In particular, the signal r will be referred to as a baseband signal.

If the pre-equalizer phase control method performs carrier phase control at the demodulator stage, the signal r' is not subjected to phase control and therefore has a certain phase error θ. Therefore, if the signal r' is multiplied by the sine wave e ^-j , the phase error becomes 0 and carrier wave phase control is possible. This calculation is performed by a sine wave generator 16 and a multiplier 10.

Quantizer 12 determines the signal t (or symbols) originally transmitted by signal r and quantizes it into a discrete signal t'. If there is no error in this judgment, t'=t (1).

The divider (DIV) 14 is a divider for complex numbers and outputs r/t. By the way, if we express r=|r|e ^j 〓 (2) t=|t|e ^j 〓 (3), it becomes r/t=|r/t|e ^j( 〓 ^- 〓 ⁾ (4). By the way, the phase error Δθ is Δθ=γ−τ (5), so if |Δθ|≪1 (6) and |r/t|≒1 (7), then Δθ=Imag(r/t) (8 ) is obtained. The imaginary part selection unit 18 selects the imaginary part Imag(r/t) from the output r/t of the divider 14 and outputs it as a signal Δθ.

The condition of equation (7) is that even in cases where the amplitude value of t |t| can take various values, such as in Recommendation V.29,
This is satisfied by the action of AGC (not shown).

Equation (8) performs division, but when expressed in the form of multiplication, Δθ=Imag(r/t)=Imag(
r・t ^* /t・t ^* )=I _nag (rt ^* / | t | ² ) (9) Therefore, Δθ= (1/ | t | ² )・Imag (r・t ^* ) (10) can get. Here t ^* is the complex conjugate of t.
Although the right side of equation (10) seems to include division, the signal t
takes the quantized signals t ₁ , t ₂ ,..., so the signal
It can be replaced by a constant _{d i =} 1/|t _i | ² (11) corresponding to t i (i=1, 2, . . . ). Therefore, quantizer 1
2 so that it outputs t and d for input r, we get Δθ=d・Imag(r・t ^* ) (12), which eliminates the division. Note that if the output of the divider 14 is only imaginary numbers, this imaginary number selection circuit 18 is unnecessary.

In the process up to now, the phase error θ was corrected to obtain r=r'·e ^-j 〓 (13), but as a result, there was still an error of Δθ. Therefore, θ can be successively corrected by setting θ _o+1 = θ _o + α・Δθ _o (14). here,
n represents the n-th symbol, α is a phase tracking coefficient, and generally 0<α<1 (14a). It seems that the tracking ability for phase jitter will be better if α is set as large as possible, but
When there is noise, etc., it often happens that the residual jitter (residual RMS (or MS) phase jitter) cannot be reduced unless α is reduced to a certain extent.

Equation (14) is realized by the phase control section 20 in FIG. This corresponds to a first-order integrating circuit, but it may also be a second-order integrating circuit in order to follow the frequency offset of the carrier wave. Furthermore, it is also possible to use a higher order one to track jitter at a specific frequency.

By the way, when the carrier wave has a frequency offset, the average value of Δθ in the primary system integration circuit (formula (14)) 20 takes a small positive or negative value. Therefore, the output θ continues to increase or decrease, and eventually exceeds the range that can be expressed by the hardware.
This will cause overflow or underflow. However, this is not a problem if you do the following. Regarding the angle θ, θ=θ±2 _i π(i=0, 1, 2,...) (15), so the apparent range of θ can be expressed as, for example, 0≦θ<2π (16) or −π≦θ< If π (17), then when this range (Equation (16) or (17)) is exceeded, it is only necessary to adjust it to the previous range using Equation (15).

This can be done even more easily as follows.
Let be an m-bit register and let it correspond to = (θ/2π)・2 ^m (18). Adding the condition of equation (16), 0≦<2 ^m −1 (19) Add equation (14) to _o+1 = ( _o + (α・Δθ _o /2π・2 ^m )) MOD2 ^m (20) All you have to do is to do it with a modulus of 2 ^m (MOD2 ^m ).
Of course, θ _o+1 = 2π/2 ^m・(21).

The sine wave generator 16 generates a sine wave e ^−j 〓 according to the output θ of the phase control section 20 and inputs it to the multiplier 10 .

By the way, when such a conventional carrier wave phase control device (FIG. 2) is applied to CCITT Recommendation V.29, the following problem occurs. In segment 2 of the V.29, 9600 bits/second mode, an alternating sequence of symbols A and B of FIG. 1 is used. Therefore, when the quantizer inputs the signal r, if it lies on the left half plane with the straight line l in FIG.
If it is on the right half plane, it is determined to be symbol B, and t=A or t=B is output, respectively.

Now, the signal r where symbols A and B are rotated by Δθ
Suppose we get If now |Δθ|≪1, the phase error Δθ becomes smaller successively. This is the normal carrier phase control operation.

By the way, if Δθ=π (radians), symbol A becomes C, symbol B becomes D, and a signal r is obtained. Therefore, when r≒C' is received, r is changed to B by the carrier phase control device (Fig. 2).
When r≈D is received, θ is decreased so that r approaches A. Therefore, θ repeats alternating increases and decreases, and does not approach the original value of θ+π. This is a kind of pseudo-lock in phase control.

Once such a pseudo-lock occurs, it becomes impossible to escape from that state. In reality, it does not last forever because it is affected by line distortion, noise, etc., but it is possible that it will not be possible to escape from the pseudo-lock within a short MODEM training sequence.

When moving to segment 3 with this pseudo-lock state, in the pseudo-random sequence of symbols C and D, symbols C and D each have r≈
It will be received as A, r≈B.

That is, in FIGS. 1 and 2, when the baseband signal r demodulated and phase-controlled as point C is determined as symbol B, the phase error θ (absolute value) is reduced (in this case, (clockwise rotation) phase controlled. At the next symbol time,
r becomes point D (more precisely, since it has been rotated to the right by the previous phase control, it becomes point D', which is slightly rotated to the right from point D). At this time, the phase is controlled so that the absolute value of the phase error -θ' decreases (in this case, it rotates to the left). Next, when r reaches point C (more precisely, point C', which is a slightly rotated position near point C), phase control of clockwise rotation occurs again, and thereafter, in the same way, left, right, left, right, etc. and stable under vibration conditions. This is the true nature of pseudo-lock. Similar pseudo-locks can occur here as well.

In segment 3, the automatic adaptive equalizer performs an adaptive operation to the line characteristics. In the case of the well-known transversal equalizer, the error signal (r-
t) to successively modify the tap coefficients. This modification requires the condition that the output t of the quantizer 12 is not erroneous. However, in the pseudo-lock state, the quantizer 12 makes a completely opposite decision, so the tap coefficients of the equalizer are corrected in the wrong direction, eventually leading to a state in which equalization is impossible. Although such a worst-case scenario is actually rare, erroneously modifying the tap coefficients of the equalizer, even temporarily, can make the convergence of the equalizer extremely poor.

The same is true for CCITT Recommendation V.29 7200
It also occurs in bit/second and 4800 bit/second modes.

Therefore, the present invention provides a carrier waveform that allows correct phase control to be performed without causing such pseudo-lock conditions, and that allows the system including the automatic equalizer and carrier detection PLL to quickly and stably converge in the initial training sequence. An object of the present invention is to provide a phase control device.

More specifically, the present invention provides a carrier phase control device that can reliably follow the absolute phase in segment 2 of CCITT Recommendation V.29 without causing false locks, and can shift to segment 3 in the correct phase control state. is planned.

This object is achieved by a carrier phase control device according to the invention as follows. In other words, this device includes a sine wave generating circuit that generates a sine wave e -j 〓 in response to a first signal representing the phase error θ of the carrier wave in the base band, and a sine wave generating circuit that generates a sine wave e ^-j a multiplier circuit that outputs a second signal whose carrier phase is controlled;
a calculation circuit for calculating an average phase error Δθ between two received symbols and outputting a third signal representing the average phase error Δθ; This circuit includes a phase control circuit that outputs a phase error θ of the carrier wave in the base band.

Next, an embodiment of the carrier phase control device according to the present invention will be described in detail with reference to FIG. In this figure, similar components to the prior art device shown in FIG. 2 are designated with the same reference numerals.

In FIG. 3, a switching circuit (SW) 50 is provided between the imaginary part selection section 18 and the phase control section 20. The switching circuit 50 is to which this device is applied.
It includes a switch that receives a control signal S from a sequence control circuit (not shown) that centrally controls the entire operation of the MODEM and switches to the 0 side or the 1 side. The 0 side contact is connected to the imaginary part selection section 118 of the arithmetic circuit 100 by a signal line 52, and the 1 side contact is connected to the imaginary part selection section 18 by a signal line 54. A stator side 56 of the switching circuit 50 is connected to the phase control section 20 .

The arithmetic circuit 100 includes an imaginary part selection section 118 and a divider 1
02 and a synthesis circuit 150. Synthesis circuit 1
50 consists of a delay circuit (DLY) 152 which receives the baseband signal r _i at the output 64 of the multiplier 10, and an adder (ADD) 154. However, i
is a natural number and indicates the symbol number in the line signal. One input 58 of the multiplier 10 receives a signal r _i ' from an equalizer (not shown). Further, from the output 60 of the quantizer 12, the quantizer 12
The signal t _i determined based on the quantization level is output.

Now, suppose that at the beginning of MODEM training, an alternating series of two symbols A and B in FIG. 1 is sent from the transmitting side. The switching circuit 50 is controlled by the control signal S from the sequence control circuit.
In the alternating series of binary symbols in the MODEM training sequence, the contact point is switched to the 0 side. In other cases, it is switched to the contact 1 side. To simplify the explanation, let us assume that the line distortion is small, the symbol sample timing is almost optimal, and the phase error is small. Then, the signal r _i is approximately A or B. Also, since the signals r _i and r _-1 are different from each other, if r _i ≒ A, then r _i-1 ≒ B. If r _i ≒ B, then r _i-1 ≒ A, and in the end, r _i + r _i-1 ≒ A + B. ≡E (101) is obtained.

The computation of equation (101) is performed by the synthesis circuit 150. Delay circuit 152 has a delay time equal to one symbol period in this embodiment. Therefore, its output 156 contains the signal from one symbol period ago.
r _{i -1} appears, this and signal r _i are added in adder 154 , and the addition result is output to adder output 158 .

Here, if r _i and r _i-1 both have a phase error of Δθ, r _i + r _i-1 = A・e ^j 〓〓+B・e ^j 〓〓=
(A+B)e ^j 〓〓=E・e ^j 〓〓 (102). This is the output 1 of adder (ADD) 154
Obtained at 58.

This combined output (formula (102)) is the average value of binary symbols A and B. That is, it extracts the DC component. In this sense, many other expressions can be considered, for example, r _i + r _i-1 + r _i-2 + r _i-3 = 2E・e ^j 〓〓 (103) 1/2・r _i + r _r-1 + 1/ 2r _i-2 =E・e ^j 〓〓(104
) etc. are listed as representative examples. Both use the property that the symbols A and B occur alternately.

Next, to find the phase error Δθ from equation (102),
A reference signal with a reference phase (formula (8)) as in the past
Either divide by r _ref or multiply by the complex conjugate r ^* _ref of r _ref (Equation (10)). Here, r _ref = E (105) and r _i + r _i-1 / r _ref = E・e ^j 〓〓/E=e ^j 〓〓 (106
), so if |Δθ|≪1, then Δθ≒Imag(e ^j 〓〓)=Imag(r _i +r _i-1 /E) (107). This operation is performed by the divider 10 of the arithmetic circuit 100.
2 and the imaginary part selection unit 118.
The phase error signal Δθ is output to the output 52 of the imaginary part selection unit 118.
Output.

Equation (106) is as in equations (9) and (10) (r _i +r _i-1 )・r ^* _ref =E・e ^j 〓〓
・E ^* = | E | ² e ⁱ 〓〓 (108) If you calculate, Δθ≒1/ | E | ² Imag {(r _i + r _i-1 )・E ^* } (109), and |E | If normalized to 1, Δθ≒Imag((r ₁ +r _i-1 )·E ^* ) (110) is obtained. However, E ^* is the conjugate complex number of E.
Therefore, the divider 102 of the arithmetic circuit 100 may be replaced with a multiplier that multiplies the output r _i +r _i-1 of the adder 154 by E ^* (=r ^* _ref ).

The phase control operation is similar to the conventional case shown in FIG.

In the above explanation, |Δθ| was assumed to be sufficiently small, but |
As Δθ| becomes larger, this approximation becomes worse. Of course Δθ＝arctanImag(e ^j 〓〓)／Real(e ^j 〓〓)(
111), but this calculation is complicated. Furthermore, as θ is successively corrected by phase control, |Δθ| gradually becomes smaller, and finally it can be sufficiently approximated by equation (107) or (110), so generally the arctangent No function calculations are required.

By the way, in equations (101) to (106), Δθ
Let us consider the case where is approximately π (radian).
In this case, the received signals r _i and r _i-1 are approximately C and D in Fig. 1.
Take point (or point D, C). Therefore, r _i +r _i-1 ≒C+D≡F=-E (112). Performing the same calculations as in equations (107) and (110) yields Δθ=Imag(r _i +r _i-1 /E)≒
Imag (-E/E) = 0 (113) Δθ = Imag {(r _i + r _i-1 )・E ^*
}≒Imag(−E ² )=0(114). Therefore, if the original phase error is approximately π (radians), the calculated phase error Δθ
Since θ is small, the convergence of θ by phase control becomes slow. However, once the original phase error deviates from π to some extent, θ begins to converge rapidly thereafter.

In order to prevent such a phenomenon, the following can be done. From equations (106) and (108), r _i +r _i-1 / r _ref ≡x+jy (115) or (r _i +r _i-1 )・r ^* _ref ≡x+jy (116) (x, y are real numbers), If x>0, set Δθ=y (117), and if x<0, set Δθ=π−y (118). Here, when x=0, it may be included in either equation (117) or (118).

This calculation is performed by configuring the imaginary part selection section 118 as follows. In the output signal of the divider 102 or a multiplier replacing it, if the real part x is positive (or 0), the value of the imaginary part y is output as the phase error Δθ to the output 52, and the real part x is negative. (or 0), the value obtained by subtracting the value of the imaginary part y from π is output as Δθ. Note that in equation (118), π does not need to be exactly π, and it is sufficient if the phase control circuit 20 can quickly escape from the phase error Δθ≈π.

After detecting the absolute phase of the carrier wave with the switching circuit 50 connected to the 0 side, the automation is completed and the switching signal S from the sequence control circuit is
When the switching circuit 50 is switched to the contact 1 side, training of the equalizer etc. starts using a pseudo-random sequence of binary symbols, and the quantizer 12, divider 14 and imaginary part selector 18 select the carrier wave. Phase control is performed.

Note that the phase control operation (for example, equation (14)) does not need to be performed for each symbol. In the case of FIG. 3, a new calculation of θ (updating of θ) may be performed every two symbols, that is, every other symbol.

Incidentally, the divider 102 of the arithmetic circuit 100 can be omitted. In Figure 1, if we consider the signal arrangement rotated by 90 degrees, points A, B, and E are respectively
These are points A′, B′, and E′. If normalized to |E|=|E′|=1, E′=1.

Therefore, r _i +r _i-1 /E′=r _i +r _i-1 /1=r _i +r _i-1 (119) or (r _i +r _i-1 )E′ ^* = (r _i +r _i-1 )・1=r _i +r _i-1 (120), so neither multiplication nor division is necessary. In other words, the output 158 of the adder 154 is directly sent to the imaginary part selection unit 118.
It can be used as an input.

Even if it is not rotated 90 degrees, if E=-j, then r _i +r _i-1 /E=r _i +r _i-1 /-j=(r _i +r _i-1 )
j = −Imag (r _i + r _i-1 ) + j・Real (r _i + r _i-1 ) (121
) Similarly, (r _i +r _i-1 )E ^* = (r _i +r _i-1 )j=-Imag(r _i
+r _i-1 ) + j・Real(r _i +r _i-1 ) (122) Therefore, the imaginary part selection unit 118 inputs r _i +
All you have to do is swap the real and imaginary parts of r _i-1 and adjust the sign appropriately.

By configuring the carrier wave phase control device according to the present invention in this way, it is possible to
The oscillating condition to the right cannot occur, and therefore the previously occurring false locks are essentially impossible with the present invention.
That is, as is clear from the above description, the present invention uses the property of alternating symbols in the training sequence of the modem, removes high frequency components due to this alternating occurrence, extracts a DC component, and converts this DC component into a phase The main feature is that the phase is controlled using E in equation (101), which indicates the DC component of alternating symbols, as the error and the reference for phase comparison. The above equations (102), (103),
Alternatively, equation (104) is an equation for extracting the DC component of the phase error of symbols that occur alternately.

Also, although equations (107) and (110) are approximate equations,
Equation (111) is not an approximate equation. If we calculate the phase error Δθ using equation (111), even if the original phase error (denoted as ΔΘ) is π, Δθ will not become 0 but will become π, so the phase error will quickly become 0. It is clear that it will be converged. According to equation (111), Δθ
=ΔΘ. At this time, since the alternating current component is removed in advance in calculating the phase error, the oscillating state in the prior art cannot occur in the present invention, and therefore, false locks cannot essentially occur. Therefore, it is possible to transition from segment 2 of the initial training according to CCITT Recommendation V.29 to segment 3 in a phase-controlled state, resulting in better convergence of the system including the equalizer and carrier detection PLL. can be done. Also, regarding timing extraction, if a decision-directed method is used, good convergence can be achieved.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the arrangement of signals used in the initial training sequence of MODEM on a complex plane, Fig. 2 is a block diagram showing a carrier wave phase control method according to the prior art, and Fig. 3 is a diagram showing carrier wave phase control according to the present invention. FIG. 2 is a block diagram showing an embodiment of the device. Explanation of symbols of main parts, 10... Multiplier, 12
...Quantizer, 14,102...Divider, 16...
... Sine wave generator, 18,118 ... Imaginary part selection unit,
20... Phase control section, 50... Switching circuit, 100
... Arithmetic circuit, 150 ... Synthesis circuit, 152 ...
Delay circuit, 154... Adder, 64... Baseband signal.

Claims (1)

[Claims] 1. Receiving and demodulating a quadrature amplitude modulated or phase modulated line signal, and during initial training, an alternating sequence of two symbols located asymmetrically with respect to the origin in the complex plane representation of the line signal. A carrier wave phase control device for controlling the ^phase of a baseband signal output from a demodulator using a sine wave generating circuit that generates a sine wave; a multiplier circuit that multiplies the baseband signal by the sine wave and outputs a second signal whose carrier phase is controlled; a calculation circuit that calculates an average phase error Δθ and outputs a third signal representing the average phase error Δθ; and a phase control circuit that calculates a more accurate phase error θ from the third signal and outputs it as a first signal. What is claimed is: 1. A carrier wave phase control device comprising: a carrier wave phase control device, which cancels a phase error θ of a carrier wave in a base band; 2. In the device according to claim 1,
The calculation circuit includes a combining circuit that combines signals of at least two consecutive symbols at a time interval of one symbol in the second signal; 1. A carrier wave phase control device, comprising: a phase difference detection circuit that outputs a signal as a signal. 3. In the device according to claim 1,
A carrier phase control device, wherein the phase control circuit outputs a first signal for each successive one or more symbols in the baseband signal. 4. In the device according to claim 2,
Carrier phase control characterized in that the synthesis circuit includes a delay circuit that delays the second signal by a time equal to one symbol period, and an addition circuit that adds the delayed signal and the second signal. Device. 5. In the device according to claim 4,
A carrier phase control device, wherein the phase control circuit outputs a first signal for every two consecutive symbols in the baseband signal. 6. In the device according to claim 2, the phase difference detection circuit includes a division circuit that divides the signal synthesized by the synthesis circuit by a reference signal having a reference phase; and an imaginary part selection circuit that outputs the value of the imaginary part of the division result as a third signal. 7. In the device according to claim 2,
The phase difference detection circuit includes a multiplication circuit that multiplies the signal synthesized by the synthesis circuit by a conjugate complex number of a reference signal having a reference phase, and outputs the value of the imaginary part of the multiplication result in the multiplication circuit as a third signal. 1. A carrier phase control device comprising: an imaginary part selection circuit. 8. In the device according to claim 6,
The imaginary part selection circuit is characterized in that when the real part of the division result is negative, the circuit outputs a value obtained by subtracting the value of the imaginary part from a value approximately equal to π (radians) as a third signal. Carrier phase control device. 9. In the device according to claim 7,
The imaginary part selection circuit outputs, as a third signal, a value obtained by subtracting the value of the imaginary part from a value approximately equal to π (radians) when the real part of the multiplication result is negative. Phase control device.