JPH0423963B2 - - Google Patents

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Publication number
JPH0423963B2
JPH0423963B2 JP60085816A JP8581685A JPH0423963B2 JP H0423963 B2 JPH0423963 B2 JP H0423963B2 JP 60085816 A JP60085816 A JP 60085816A JP 8581685 A JP8581685 A JP 8581685A JP H0423963 B2 JPH0423963 B2 JP H0423963B2
Authority
JP
Japan
Prior art keywords
circuit
voltage
current
capacitor
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60085816A
Other languages
Japanese (ja)
Other versions
JPS61244115A (en
Inventor
Hisao Tateishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP60085816A priority Critical patent/JPS61244115A/en
Publication of JPS61244115A publication Critical patent/JPS61244115A/en
Publication of JPH0423963B2 publication Critical patent/JPH0423963B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は電流制御型発振器の回路構造に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit structure of a current controlled oscillator.

(従来の技術) 電圧制御型発振器(VCO)などに利用される
電流制御型発振器は、通常、入力信号電圧で動作
制御される2つの定電流回路と、この2つの定電
流回路と一つの容量との間を周期的に交互に切替
え接続する電流切替回路とを基本として回路構成
される。すなわち、一つの容量に定電流回路の一
方の電流を通じて充電し、ついで他方の定電流回
路に切替えて充電電荷を引張らせ放電せしめる周
期動作によつて発振出力を得るものである。通
常、電流切替回路は2つの定電流回路の間に挿入
されるCMOSインバータで構成され、一つの容
量はそのインバータ出力端子と電源端子の一つ
(例えば地気端子)との間に接続される。また、
このインバータのゲート電極には、充放電により
変化する容量の端子間電圧を2値化した信号が帰
還され、所謂自走発振回路として構成されるのが
常である。通常、この信号変換にはシユミツト・
トリガ回路が使用される。この場合の発信周波数
pscを一般式で記述すればつぎの通りである。
(Prior Art) A current-controlled oscillator used in a voltage-controlled oscillator (VCO), etc. usually has two constant-current circuits whose operation is controlled by an input signal voltage, and two constant-current circuits and one capacitor. The circuit is basically configured with a current switching circuit that alternately switches and connects between the two. That is, an oscillation output is obtained through a periodic operation in which one capacitor is charged through one current of a constant current circuit, and then the other constant current circuit is switched to draw and discharge the charged charge. Usually, a current switching circuit consists of a CMOS inverter inserted between two constant current circuits, and one capacitor is connected between the inverter output terminal and one of the power supply terminals (e.g. earth terminal). . Also,
A signal obtained by converting the voltage between the terminals of the capacitor, which changes due to charging and discharging, into a binary value is fed back to the gate electrode of this inverter, and the inverter is usually constructed as a so-called free-running oscillation circuit. Typically, this signal conversion involves a Schmitt
A trigger circuit is used. Transmission frequency in this case
If psc is written using a general formula, it is as follows.

1/psc=2C/I0・(VSH−VSL)+4td ただし、 I0…定電流回路の定電流値 C…容量の大きさ VSH,VSL…シユミツト・トリガ回路のヒステリ
シス電圧値 td…シユミツト回路およびインバータの動作遅延
時間 (発明が解決しようとする問題点) 既に述べたようにこの発振器は自走発振器なの
で、CMOSインバータの電流切替回路とこれを
動作制御するシユミツト・トリガ回路とは回路動
作上相互に関連し合う。従つて、このループ回路
が正常に動作しなくなると発振モードが乱れ、発
振周波数pscが変化する。通常の回路ではCMOS
インバータのしきい値は電源電圧の1/2に設計さ
れ、これに伴ないシユミツト・トリガ回路の基準
電圧もこれと等しい電圧に設定される。しかしな
がら、一般にMOS電界効果トランジスタのチヤ
ネル長(ゲート長)は製造工程においてバラツキ
を生じ易く、それによるゲートしきい値のバラツ
キはロツト間で±20%にも及びことがある。また
一方、シユミツト・トリガ回路の出力電圧特性
は、回路全体の発振限界近傍では一般に鈍い立上
がりおよび立下がり波形を示すので、このように
トランジスタのゲートしきい値にバラツキがあ
と、基準電圧をロツト毎に調整するか或いは出力
電圧特性そのものを方形波形に改善しない限りイ
ンバータの電流切替動作タイミングに変動を与え
る。すなわち、規定された発振周波数を出力し得
なくなる。このように従来回路構成の電流制御型
発振器は、電流切替回路を構成するCMOSイン
バータのゲートしきい値のバラツキに対して繁雑
な対応しかできず、きわめて量産性に乏しい欠点
を有する。
1/ psc = 2C/I 0 (V SH −V SL ) + 4t d However, I 0 ... Constant current value of constant current circuit C ... Capacitance size V SH , V SL ... Hysteresis voltage value of Schmitt trigger circuit t d ...Operation delay time of the Schmitt circuit and inverter (problem to be solved by the invention) As already mentioned, this oscillator is a free-running oscillator, so the current switching circuit of the CMOS inverter and the Schmitt trigger circuit that controls its operation are required. and are interrelated in terms of circuit operation. Therefore, if this loop circuit ceases to operate normally, the oscillation mode will be disturbed and the oscillation frequency psc will change. In a normal circuit, CMOS
The threshold value of the inverter is designed to be 1/2 of the power supply voltage, and the reference voltage of the Schmitt trigger circuit is also set to the same voltage. However, in general, the channel length (gate length) of a MOS field effect transistor tends to vary during the manufacturing process, and the resulting variation in gate threshold value can reach as much as ±20% from lot to lot. On the other hand, the output voltage characteristics of a Schmitt trigger circuit generally exhibit slow rising and falling waveforms near the oscillation limit of the entire circuit. Unless the output voltage characteristic itself is adjusted to a square waveform or the output voltage characteristics themselves are improved to a square waveform, the current switching operation timing of the inverter will vary. In other words, it becomes impossible to output the specified oscillation frequency. As described above, the current controlled oscillator with the conventional circuit configuration has the disadvantage that it can only deal with variations in the gate threshold value of the CMOS inverter that constitutes the current switching circuit in a complicated manner, and is extremely difficult to mass-produce.

本発明の目的は、上記の情況に鑑み、電界効果
トランジスタにおけるゲートしきい値のバラツキ
によつて電流切替タイミングが影響されない電流
切替回路を備えた電流制御型発振器を提供するこ
とである。
In view of the above circumstances, an object of the present invention is to provide a current controlled oscillator including a current switching circuit in which current switching timing is not affected by variations in gate threshold values in field effect transistors.

(問題点を解決するための手段) 本発明の電流制御型発振器は、電源端子の一つ
に入力側または出力側の何れか一方をそれぞれ接
続し入力信号電圧でそれぞれ動作制御される2つ
の定電流回路と、前記2つの定電流回路の間に接
続される互いに異なる極性の2つの電界効果トラ
ンジスタ差動増幅器の並列接続からなり入力する
2値信号の何れか一方にそれぞれ応答して前記定
電流回路のそれぞれと共通差動出力端子との間を
交互に切替え接続する電流切替回路と、前記共通
差動出力端子と電源端子の一つとの間に接続され
前記電流切替回路の切替動作毎に交互に充放電を
繰り返す容量と、前記容量の両端電圧と前記2つ
の電界効果トランジスタ差動増幅器のリフアレン
ス電圧に等しく設定される基準電圧とのレベル差
を2値化し前記2つの電界効果トランジスタ差動
増幅器の入力信号として電流切替回路に帰還する
信号変換回路とを備えることを含む。
(Means for Solving the Problems) The current controlled oscillator of the present invention has two constants each having either the input side or the output side connected to one of the power supply terminals and whose operation is controlled by the input signal voltage. The constant current circuit is composed of a current circuit and two field effect transistor differential amplifiers of different polarities connected in parallel between the two constant current circuits, each in response to either one of the input binary signals. a current switching circuit that alternately switches and connects between each of the circuits and a common differential output terminal; and a current switching circuit that is connected between the common differential output terminal and one of the power supply terminals and alternates each time the current switching circuit switches. A capacitor that is repeatedly charged and discharged, and a level difference between the voltage across the capacitor and a reference voltage set equal to the reference voltage of the two field effect transistor differential amplifiers are binarized and the two field effect transistor differential amplifiers are connected to each other. and a signal conversion circuit which is fed back to the current switching circuit as an input signal of the current switching circuit.

すなわち、本発明によれば、信号変換回路から
の2値信号によつて切替動作を行なう電流切替回
路は、従来のCMOSインバータの各トランジス
タにそれぞれと同一極性の電界効果トランジスタ
がそれぞれ配設され、ソース同志を共通接続して
構成される2つの電界効果トランジスタ差動増幅
器の並列接続によつて構成される。この際、2つ
の差動増幅器のリフアレンス電圧と信号変換回路
の基準電圧とは、互いに等しい電圧(例えば、電
源電圧の1/2)に設定される。ここで、信号変換
回路にはシユミツト・トリガ回路の如く入力に対
しヒステリシス特性を示すものが望ましい。しか
し、これに代わるものであれば置換して用いるこ
ともできる。
That is, according to the present invention, a current switching circuit that performs a switching operation based on a binary signal from a signal conversion circuit includes field effect transistors having the same polarity as each transistor of a conventional CMOS inverter, and It is constructed by connecting in parallel two field effect transistor differential amplifiers whose sources are commonly connected. At this time, the reference voltages of the two differential amplifiers and the reference voltage of the signal conversion circuit are set to be equal to each other (for example, 1/2 of the power supply voltage). Here, it is desirable that the signal conversion circuit exhibit hysteresis characteristics with respect to input, such as a Schmitt trigger circuit. However, any substitute can be used instead.

(作用) 本発明によれば、2つの電界効果トランジスタ
差動増幅器の並列接続回路は、設定されたリフア
レンス電圧をしきい値として信号変換回路の2値
信号によるスイツチ動作を行なう。従つて、電界
効果トランジスタのゲートしきい値電圧に製造上
のバラツキがある場合でも、常に2値入力信号に
同期して容量に対する2つの定電流回路の切替動
作を行なうことができる。
(Function) According to the present invention, a parallel connection circuit of two field effect transistor differential amplifiers performs a switching operation using a binary signal of a signal conversion circuit using a set reference voltage as a threshold. Therefore, even if there is manufacturing variation in the gate threshold voltage of the field effect transistor, the switching operation between the two constant current circuits for the capacitance can always be performed in synchronization with the binary input signal.

(実施例) 以下図面を参照して本発明を詳細に説明する。(Example) The present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例を示す接続回路図で
ある。本実施例では、2つの定電流回路を構成す
るトランジスタQ1,Q2,Q3およびQ4と、電流切
替回路の2つの電界効果トランジスタ差動増幅器
を構成するトランジスタQ5,Q6およびQ7,Q8
と、共通差動出力端子Pと地気端子GNDとの間
に接続された容量C1と、容量C1の両端電圧を正
相入力端子に、また、電源電位VDDの1/2電圧を
負相入力端子にそれぞれ接続し、その出力をトラ
ンジスタQ5およびQ7のゲート端子に帰還するシ
ユミツト・トリガ回路Sとを含む。ここで2つの
差動増幅器のリフアレンス電圧は、シユミツト・
トリガ回路Sの基準電圧VDD/2と等しく設定さ
れ、トランジスタQ6およびQ8の共通ゲート接続
端子に与えられる。また、VINは入力信号であ
る。
FIG. 1 is a connection circuit diagram showing one embodiment of the present invention. In this example, transistors Q 1 , Q 2 , Q 3 and Q 4 constitute two constant current circuits, and transistors Q 5 , Q 6 and Q constitute two field effect transistor differential amplifiers of a current switching circuit. 7 , Q8
, a capacitor C 1 connected between the common differential output terminal P and the earth terminal GND, the voltage across the capacitor C 1 to the positive phase input terminal, and 1/2 voltage of the power supply potential V DD to the positive phase input terminal. A Schmitt trigger circuit S is connected to each of the negative phase input terminals and feeds back its output to the gate terminals of transistors Q5 and Q7 . Here, the reference voltages of the two differential amplifiers are Schmitts
It is set equal to the reference voltage V DD /2 of the trigger circuit S and is applied to the common gate connection terminal of transistors Q 6 and Q 8 . Further, V IN is an input signal.

この回路接続では、電流の切替操作そのものは
従来の同じくトランジスタQ5およびQ7によつて
それぞれ行なわれる。すなわち、容量C1の両端
電圧と基準電圧VDD/2とのレベル差はシユミツ
ト・トリガ回路Sで“H”または“L”の2値信
号に変換され、トランジスタQ5およびQ7をそれ
ぞれゲート制御する。ここで、シユミツト・トリ
ガ回路Sが“L”を出力するとトランジスタQ5
が導通してトランジスタQ5からの定電流I0を容量
C1に流し、また、“H”を出力するとトランジス
タQ7が導通して容量C1からトランジスタQ2に定
電流I0を流す。しかしながら、トランジスタQ5お
よびQ7はトランジスタQ6およびQ8との間に、リ
フアレンス電圧をVDD/2とする差動増幅器を構
成しているので、トランジスタQ5およびQ7の動
作はそれぞれこのリフアレンス電圧で規制され
る。従つて、トランジスタQ5およびQ7はゲート
しきい値電圧をそれぞれ等価的にVDD/2として
動作し容量C1を充放電せしめるので、ゲートし
きい値電圧のバラツキの影響を除去した自走発振
器を構成し得る。
In this circuit connection, the current switching operation itself is performed by the conventional transistors Q5 and Q7 , respectively. That is, the level difference between the voltage across the capacitor C 1 and the reference voltage V DD /2 is converted into a binary signal of "H" or "L" by the Schmitt trigger circuit S, which gates the transistors Q 5 and Q 7 , respectively. Control. Here, when the Schmitt trigger circuit S outputs "L", the transistor Q5
conducts the constant current I 0 from the transistor Q 5
C 1 and outputs "H", transistor Q 7 becomes conductive and a constant current I 0 flows from capacitor C 1 to transistor Q 2 . However, since transistors Q 5 and Q 7 constitute a differential amplifier with a reference voltage of V DD /2 between transistors Q 6 and Q 8 , the operation of transistors Q 5 and Q 7 , respectively, is similar to this. Regulated by reference voltage. Therefore, transistors Q 5 and Q 7 operate with their gate threshold voltages equivalently V DD /2, charging and discharging capacitor C 1 , so that the transistors Q 5 and Q 7 operate as free-running transistors that eliminate the influence of variations in gate threshold voltage. An oscillator may be configured.

第2図は本発明発振回路における各部出力波形
図で、トランジスタQ5およびQ7のゲートしきい
値のバラツキが影響しないことを示す。ここで、
a,bおよびcは、シユミツト・トリガ回路出力
波形図、トランジスタQ7の動作波形図および容
量C1の充放電電圧波形図をそれぞれ示す。
FIG. 2 is a diagram of output waveforms of various parts in the oscillation circuit of the present invention, and shows that variations in the gate threshold values of transistors Q5 and Q7 have no effect. here,
a, b, and c respectively show a Schmitt trigger circuit output waveform diagram, an operation waveform diagram of transistor Q7 , and a charging/discharging voltage waveform diagram of capacitor C1 .

第3図および第4図は、従来回路構成の接続回
路図およびその各部出力波形図をそれぞれ示すも
ので、本発明との対比を容易とする目的で掲げた
ものである。従つて、第1図および第2図と共通
するものには同一の符号が用いられている。第4
図において、トランジスタQ7のしきい値が設定
値設定値であるVDD/2より高くなつた場合を示
す。トランジスタQ7は、シユミツトトリガ回路
の出力が波形aに示すしきい値に達したとき、始
めて波形bのようにオンとなり、波形cに示すよ
うにコンデンサC1の電圧が低下するが、この結
果、波形a,bの周期が短縮される、すなわち、
回路全体の発振周波数が増加する様子が示されて
いる。この回路接続では、CMOSインバータを
構成するトランジスタQ5およびQ7それぞれの単
独動作が直接電流切替回路の切替タイミング特性
を支配する。従つて、これらトランジスタのゲー
トしきい値電圧のバラツキが直接発振周波数に影
響しバラツキを与えることとなる。
3 and 4 respectively show a connection circuit diagram of a conventional circuit configuration and an output waveform diagram of each part thereof, and are shown for the purpose of facilitating comparison with the present invention. Therefore, the same reference numerals are used for parts common to FIGS. 1 and 2. Fourth
The figure shows a case where the threshold value of transistor Q 7 becomes higher than the set value V DD /2. When the output of the Schmitt trigger circuit reaches the threshold shown in waveform a, transistor Q7 turns on for the first time as shown in waveform b, and the voltage across capacitor C1 decreases as shown in waveform c. As a result, The periods of waveforms a and b are shortened, that is,
It is shown that the oscillation frequency of the entire circuit increases. In this circuit connection, the independent operation of each of transistors Q 5 and Q 7 forming the CMOS inverter governs the switching timing characteristics of the direct current switching circuit. Therefore, variations in the gate threshold voltages of these transistors directly affect and cause variations in the oscillation frequency.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、
簡単な回路を付加するのみで従来問題とされてい
たゲートしきい値のバラツキによる発振周波数の
規定値よりのズレを完全に除去し得、また、各部
出力電圧がバイアス点(例えばVDD/2)を中心
とし動作するので、発振回路がもつ特性限界まで
容易に動作せしめ得る。更に、信号変換回路は電
流切替回路と独立に出力特性を設定することがで
き設計に大きな自由度をもたせることができる。
例えば出力特性の立上がりおよび立下がりに大き
な遅延がある場合でも、従来回路構成で問題とさ
れた発振出力のデユーテイ比変動なる現象を生じ
ることはない。また更に、電界効果トランジスタ
差動増幅器をスイツチ動作するに必要な電圧は最
小0.1Vであるので、例えばシユミツト・トリガ
回路の出力電圧はVDD/2±0.1Vに設定すれば充
分であり、きわめて量産向きの回路設計を行なう
ことができる。
As explained in detail above, according to the present invention,
By simply adding a simple circuit, it is possible to completely eliminate the deviation of the oscillation frequency from the specified value due to variations in the gate threshold value, which has been a problem in the past, and the output voltage of each part can be adjusted to the bias point (for example, V DD /2 ), it is possible to easily operate the oscillation circuit to its characteristic limits. Furthermore, the output characteristics of the signal conversion circuit can be set independently of the current switching circuit, allowing a large degree of freedom in design.
For example, even if there is a large delay in the rise and fall of the output characteristic, the phenomenon of duty ratio fluctuation of the oscillation output, which has been a problem with conventional circuit configurations, does not occur. Furthermore, since the minimum voltage required to switch a field effect transistor differential amplifier is 0.1V, it is sufficient to set the output voltage of a Schmitt trigger circuit to V DD /2±0.1V, which is extremely It is possible to design circuits suitable for mass production.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す接続回路図、
第2図は本発明発振回路における各部出力波形
図、第3図および第4図は従来回路構成の接続回
路図および各部出力波形図である。 Q1,Q2,Q3,Q4……定電流回路のトランジス
タ、Q5,Q6,Q7,Q8……電流切替回路トランジ
スタ、I0……定電流、C1……容量、S……シユミ
ツト・トリガ回路、P……共通差動出力端子、
VIN……入力信号電圧、VDD……電源電圧、GND
……地気、a……シユミツト・トリガ回路出力電
圧波形、b……トランジスタQ7の動作波形、C
……容量C1の充放電電圧波形、VSH,VSL……シ
ユミツト・トリガ回路のヒステリシス電圧。
FIG. 1 is a connection circuit diagram showing an embodiment of the present invention;
FIG. 2 is an output waveform diagram of each part in the oscillation circuit of the present invention, and FIGS. 3 and 4 are connection circuit diagrams and output waveform diagrams of each part of the conventional circuit configuration. Q 1 , Q 2 , Q 3 , Q 4 ... Constant current circuit transistor, Q 5 , Q 6 , Q 7 , Q 8 ... Current switching circuit transistor, I 0 ... Constant current, C 1 ... Capacity, S...Schmitt trigger circuit, P...common differential output terminal,
V IN ...Input signal voltage, V DD ...Power supply voltage, GND
...Earth, a... Schmitt trigger circuit output voltage waveform, b... Operation waveform of transistor Q7 , C
...Charging and discharging voltage waveform of capacitor C1 , V SH , V SL ... Hysteresis voltage of Schmitt trigger circuit.

Claims (1)

【特許請求の範囲】 1 電源端子の一つに入力側または出力側の何れ
か一方をそれぞれ接続し入力信号電圧でそれぞれ
動作制御される2つの定電流回路と、前記2つの
定電流回路の間に接続される互いに異なる極性の
2つの電界効果トランジスタ差動増幅器の並列接
続からなり入力する2値信号の何れか一方にそれ
ぞれ応答して前記定電流回路のそれぞれと共通差
動出力端子との間を交互に切替え接続する電流切
替回路と、前記共通差動出力端子と電源端子の一
つとの間に接続され前記電流切替回路の切替動作
毎に交互に充放電を繰り返す容量と、前記容量の
両端電圧と前記2つの電界効果トランジスタ差動
増幅器のリフアレンス電圧に等しく設定される基
準電圧とのレベル差を2値化し前記2つの電界効
果トランジスタ差動増幅器の入力信号として電流
切替回路に帰還する信号変換回路とを備えること
を特徴とする電流制御型発振器。 2 前記基準電圧が電源電圧の1/2に設定される
ことを特徴とする特許請求の範囲第1項記載の電
流制御型発振器。 3 前記信号変換回路が、シユミツト・トリガ回
路で構成されることを特徴とする特許請求の範囲
第1項記載の電流制御型発振器。
[Claims] 1. Between two constant current circuits whose input or output sides are each connected to one of the power supply terminals and whose operation is controlled by the input signal voltage, and the two constant current circuits. between each of the constant current circuits and a common differential output terminal in response to either one of the input binary signals. a current switching circuit which is alternately switched and connected; a capacitor which is connected between the common differential output terminal and one of the power supply terminals and which is alternately charged and discharged every switching operation of the current switching circuit; and both ends of the capacitor. Signal conversion that binarizes the level difference between the voltage and a reference voltage set equal to the reference voltage of the two field effect transistor differential amplifiers and returns it to the current switching circuit as an input signal of the two field effect transistor differential amplifiers. A current controlled oscillator comprising a circuit. 2. The current controlled oscillator according to claim 1, wherein the reference voltage is set to 1/2 of the power supply voltage. 3. The current controlled oscillator according to claim 1, wherein the signal conversion circuit is comprised of a Schmitt trigger circuit.
JP60085816A 1985-04-22 1985-04-22 Current-controlled oscillator Granted JPS61244115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60085816A JPS61244115A (en) 1985-04-22 1985-04-22 Current-controlled oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60085816A JPS61244115A (en) 1985-04-22 1985-04-22 Current-controlled oscillator

Publications (2)

Publication Number Publication Date
JPS61244115A JPS61244115A (en) 1986-10-30
JPH0423963B2 true JPH0423963B2 (en) 1992-04-23

Family

ID=13869378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60085816A Granted JPS61244115A (en) 1985-04-22 1985-04-22 Current-controlled oscillator

Country Status (1)

Country Link
JP (1) JPS61244115A (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5767331A (en) * 1980-10-14 1982-04-23 Toshiba Corp Bias varying circuit
JPS5829217A (en) * 1981-08-17 1983-02-21 Fujitsu Ltd Voltage-controlled oscillating circuit
JPS59132242U (en) * 1983-02-21 1984-09-05 日産自動車株式会社 oscillation circuit

Also Published As

Publication number Publication date
JPS61244115A (en) 1986-10-30

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