JPH04239954A - Input/output control device - Google Patents

Abstract

PURPOSE:To reduce the hardware amount in the processor circuit and to constitute the channel with abundant extendability by moving the address counter, length counter and local memory from the processor circuit to the channel circuit. CONSTITUTION:In the input/output control device connecting the peripheral control device with the subordinates and having plural channel circuits 4-1 to 4-n controlling the data transfer between a main storage device 1, the address counter 4a-1 to 4a-n showing the address on the main storage in data transfer, the length counter 4b-1 to 4b-n showing remaining value for the data and the local memory 4c-1 to 4c-n storing the control information for each channel are provided within the channel circuits 4-1 to 4-n, as a special feature.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input/output control device for controlling data transfer between a main storage device and peripheral devices according to instructions from a central processing unit.

0002

[Prior Art] An input/output control device controls the interface between a processor circuit, which controls input/output operations using a microprogram, and peripheral control devices according to instructions from a central processing unit. It consists of channel circuits that transfer data according to instructions.

[0003] This type of conventional input/output control device collectively stores information for each channel in a processor circuit.

For example, address/length information necessary for data transfer is stored between register files that can be accessed for each channel, and is read from the register file each time there is a data transfer request from a channel, and updated for the amount of data to be transferred. and restorage.

[0005] Also, intermediate information for each channel (for example, a channel program pointer, etc.) necessary for executing a channel program is stored in a local memory with an address allocated to each channel, and is accessed by the processor as necessary. .

[0006]

[Problems to be Solved by the Invention] In the conventional input/output control device described above, information for each channel is collectively held in the processor circuit, so as the maximum number of connected channels increases, the hardware of the processor circuit becomes The disadvantage is that the amount increases.

[0007]Also, normally, the hardware is designed to support the maximum configuration, but in the case of a small-scale configuration, there is a disadvantage that the hardware corresponding to the number of channels that are not connected is wasted.

[0008]

Means for Solving the Problems The device of the present invention is an input/output control device that connects a peripheral control device thereunder and has a plurality of channel circuits that control data transfer between main storage devices. It is characterized by having an address counter that indicates an address on the main memory for data transfer, a length counter that indicates a residual value of data, and a local memory that stores control information for each channel.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the first invention.

In FIG. 1, a main memory device 1, an arithmetic processor 2 that executes software instructions, and a processor circuit 3 of an input/output control device are connected to a system bus 100.

The processor circuit 3 includes a processor 3a that executes a microprogram, a control memory (hereinafter referred to as CS) 36 that stores the microprogram, and a bus control circuit 3c that controls access to the system bus 100.
It consists of a request control circuit 3d that selects data transfer requests from a plurality of channel circuits according to predetermined priorities and grants permission for data transfer.

In this embodiment, there are n units under the processor circuit 3.
It has a configuration in which (n is an integer) channel circuits are connected. Channel circuits 4-1...4-n store addresses on the main memory of data to be transferred and are updated every time data is transferred, and address counters 4a-1...4a-n, which indicate the remaining amount of data to be transferred, and Length counters 4b-1...4b-n that are updated every time a transfer is made, and a local memory (hereinafter referred to as LM) 4c- that stores control information for each channel.
1...4c-n and an interface control circuit 4d that has a built-in buffer for data transfer of multiple bytes and performs interface control between the peripheral control device (not shown) connected under it and executes data transfer and command transfer. -1...
Consists of 4d-n.

Processor circuit 3 and channel circuit 4-1...
4-n, an address bus 201 that sends out an address during data transfer, a data bus 201 that sends and receives data, an internal bus 203 that is used to exchange control information with the processor 3a, and a selected processor 3a. Channel number signal line 2 that supplies the number of the channel circuit being
04 is connected.

Next, the operation of the input/output control device of the present invention will be explained.

When receiving an I/O command instruction from the arithmetic processor 2, the processor 3a in the processor circuit 3 executes the CS
The channel program on the main memory 1 is transferred to the system bus 100 by the microprogram stored in the microprogram 3b.
to determine the number of the channel on which the operation should be performed.

The channel number is supplied from the processor 3a to all channel circuits via the channel number signal line 204,
The channel circuit determines whether the access is for itself based on the number given in advance, and if the numbers match, it accepts the access operation from the processor 3a. The explanation will now proceed assuming that the channel of the channel circuit 4-1 is selected, but the same applies when other channels are selected.

The processor 3a accesses the control information (for example, status information, etc.) stored in the LM4c-1 in the channel circuit 4-1 via the internal bus 203 and transmits it to the I/O.
O operation is prepared, and the interface control circuit 4a-
The command information in the channel program is sent to the peripheral control device connected under 1, and the I/O operation is started.

If the command indicates data transfer, the processor 3a sends the data transfer start address specified in the channel program to the address counter 4a-1 via the internal bus 203, and sends the transfer length to the length counter 4b.
-1 to instruct the interface control circuit 4d-1 to start data transfer.

In the case of input direction transfer in which data from the peripheral control device is written to the main memory 1, the interface control circuit 4d-1 requests data transfer request control when a certain amount of input data is accumulated in the buffer. It is sent to circuit 3d and waits for the data transfer permission signal to be returned. When the permission signal is returned, the channel circuit 4-1 registers the address counter 4.
The value of a-1 is sent to the address bus 201, and the transfer data from the peripheral control device is sent to the data bus 202. The bus control circuit 3c starts a system bus sequence for writing a value on the data bus 202 using an address on the address bus 201.

In the case of transfer in the output direction (writing to the peripheral control device), if there is a certain number of empty data in the buffer in the interface control circuit 4d-1, a data transfer request is sent in the same way as the output transfer, and a permission signal is sent. When the address counter 4a-1 is received, the value of the address counter 4a-1 is sent to the address bus 201. The bus control circuit 3c uses the value of the address bus 201 to
and sends the transfer data to the data bus 202. The interface control circuit 4d-1 is connected to the data bus 2
It receives the data on 02 and sends it to the peripheral control device.

Address counter 4a-1 and length counter 4b-1 are updated for each transfer in synchronization with data transfer, and data transfer continues until length counter 4b-1 reaches 0 or the peripheral control device issues an end request. It will be done.

FIG. 2 is a block diagram of another embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same components.

The parts not explained in FIG. 1 will be explained below.

Similarly to the bus control circuit 3c, the bus control circuits 4e-1...4e-n in the channel circuits 4-1...4-n perform access control of the system bus 100 based on requests from the interface circuits 4d-1...4d-n. Follow the instructions below.

Next, the operation of the input/output control device of the present invention will be explained.

In this embodiment, as in the first embodiment described above, upon receiving an I/O instruction, the processor 3a in the processor circuit 3 executes the main program using the microprogram stored in the CS 3b. A channel number for reading out the channel program stored in the memory 1 via the system bus 100 is determined.

The channel number is supplied from the processor 3a to all channel circuits via the channel number signal line 204,
The channel circuit determines whether there is an access to itself based on a pre-given number, and if the numbers match, it accepts the access operation from the processor 3a. In this example as well, the explanation will proceed assuming that the channel circuit 4-1 is selected.

The processor 3a transfers the control information stored in the LM4c-1 in the channel circuit 4-1 to the internal bus 20.
3 to prepare for the I/O operation, and also use the interface control circuit 4d-1 to send command information in the channel program to peripheral control devices connected under the I/O control circuit 4d-1. Start operation.

If the command instructs data transfer, the processor 3a sets the data transfer start address in the address counter 4a-1 and the transfer length in the length counter 4b-1 via the internal bus 203. The interface control circuit 4d-1 is instructed to start.

In the case of input transfer, the interface control circuit 4d-1 raises a data transfer request when input data from the peripheral control device accumulates to a certain value, and inputs the value of the address counter 4a-1 as the transfer address. data to the bus control circuit 4e-1. Bus control circuit 4e
When -1 has the right to use the system bus 100, it starts a bus operation to write input data into the area with the value of address count 4a-1.

In the case of output transfer, the bus control circuit 4e-
1, when receiving a data transfer request, the address counter 4a
The main memory is accessed with a value of -1, output data is obtained, and the output data is supplied to the interface control circuit 4d-1.

Address counter 4a-1 and length counter 4b are used for each data transfer in either direction.
-1 is updated and the value of length counter 4b-1 becomes “0”
Data transfer continues until the end or the peripheral controller issues a termination request.

In this embodiment, the same effects as in the first embodiment can be obtained, and in addition, the channel circuits 4-1 to 4-1
By having an access circuit for the system bus 100 every 4-n, the hardware amount of the processor circuit 3 can be further reduced, and the data transfer speed can be increased by not depending on the operation sequence of the bus control circuit 3c of the processor circuit 3. This has the advantage that peripheral control devices with various functions can be connected.

[0035]

As explained above, the present invention improves the hardware of the processor circuit by providing each channel with an address counter, a length counter, and a local memory corresponding to the channel, which were conventionally managed collectively in the processor circuit. This has the effect of reducing the amount of data and realizing a highly expandable channel configuration with efficient hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment of the invention.

[Explanation of symbols]

1 Main storage device 2 Arithmetic processor 3 Processor circuit 3a Processor 3b Control memory 3c Bus control circuit 3d Request control circuit 4-1 to 4-n Channel circuit 4a-1 to 4a-n Address counter 4b-1
~4b-n Length counter 4c-1 ~ 4c-
n Local memory 4d-1 to 4d-n
Interface control circuit 100 System bus 201 Address bus 202 Data bus 203 Internal bus 204 Channel number signal line

Claims (2)

[Claims] 1. An input/output control device having a plurality of channel circuits that connect peripheral control devices thereunder and control data transfer between main storage devices, in which the channel circuits include:
An input/output control device comprising an address counter that indicates an address on a main memory for data transfer, a length counter that indicates a residual value of data, and a local memory that stores control information for each channel. 2. A data transfer path for accessing a main memory is connected to each of the channel circuits, and an access control circuit for the main memory is provided in the channel circuit. I/O controller.