JPH0424134U - - Google Patents
Info
- Publication number
- JPH0424134U JPH0424134U JP6560490U JP6560490U JPH0424134U JP H0424134 U JPH0424134 U JP H0424134U JP 6560490 U JP6560490 U JP 6560490U JP 6560490 U JP6560490 U JP 6560490U JP H0424134 U JPH0424134 U JP H0424134U
- Authority
- JP
- Japan
- Prior art keywords
- register
- output
- multiplier
- stores
- encoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例を示す除算演算装
置の構成図、第２図は従来の除算演算装置の構成
図である。
図において、１ａ〜１ｅはレジスタ、２は乗算
器、３はエンコーダ、４ａ，４ｂはシフタ、５は
補数器、６は減算器、７はセレクタ、８はデコー
ダ、９は比較器である。なお、図中、同一符号は
同一又は相当部分を示す。
FIG. 1 is a block diagram of a division arithmetic device showing an embodiment of this invention, and FIG. 2 is a block diagram of a conventional division arithmetic device. In the figure, 1a to 1e are registers, 2 is a multiplier, 3 is an encoder, 4a and 4b are shifters, 5 is a complementer, 6 is a subtracter, 7 is a selector, 8 is a decoder, and 9 is a comparator. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
エンコーダと、上記エンコーダの出力を格納する
第１のレジスタと、上記第１のレジスタの出力を
シフト数として入力をシフトするシフタと、乗数
被乗数を格納する第２、第３のレジスタと、上記
第２、第３のレジスタの出力の積を算出する乗算
器と、上記乗算器の出力を格納する第４のレジス
タと、上記第４のレジスタの出力の補数を算出す
る補数器と、上記第４のレジスタの値が１に収束
したかを判定する比較器を備えたことを特徴とす
る除算演算装置。 In a division operation, an encoder that calculates a normalized number of input, a first register that stores the output of the encoder, a shifter that shifts the input using the output of the first register as a shift number, and stores a multiplier multiplicand. a multiplier that calculates the product of the outputs of the second and third registers, a fourth register that stores the output of the multiplier, and an output of the fourth register. 1. A division arithmetic device comprising: a complementer for calculating the complement of , and a comparator for determining whether the value of the fourth register has converged to 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6560490U JPH0424134U (en) | 1990-06-21 | 1990-06-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6560490U JPH0424134U (en) | 1990-06-21 | 1990-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0424134U true JPH0424134U (en) | 1992-02-27 |
Family
ID=31597579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6560490U Pending JPH0424134U (en) | 1990-06-21 | 1990-06-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0424134U (en) |
-
1990
- 1990-06-21 JP JP6560490U patent/JPH0424134U/ja active Pending
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