JPH04242871A - Write module for data flow calculator - Google Patents

Abstract

PURPOSE:To offer the write module for data flow calculator easily performing the dump for debugging. CONSTITUTION:A bus interface 12 fetches data 101 for write module from a data bus 11 and extracts ID 102 and data 103. A TRS table 13 converts the extracted ID 102 into an internal ID 104. An address generation circuit 14 generates the prescribed address 105 when the internal ID 104 has a specified value, otherwise it passes the internal ID 104 as it is. An address data output circuit 15 writes the data 103 extracted from the bus interface 12 in a memory with the use of the address 105 generated in the address generation circuit 14. When the internal ID 104 is directly supplied, a pair of address and data are written in the memory.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light module for a data flow computer.

0002

2. Description of the Related Art In general, debugging is essential when developing software for electronic computers, and for this purpose it is necessary to dump the results of calculations during processing into memory.

[0003] By the way, in a normal computer, by temporarily stopping processing, it is possible to dump the results of operations in the middle of processing from the contents of memory and registers at that time, but the processing in a data flow computer Because it is driven according to the flow of data, processing cannot be stopped midway through by commands from outside.

[0004] Therefore, when dumping computation results during processing in a data flow computer, conventionally the program has been modified so that the processing is interrupted at a desired point and the computation results are output to memory. was.

[0005]

[Problems to be Solved by the Invention] As mentioned above, in conventional data flow computers, when dumping the calculation results etc. during processing, the program is rewritten, so when there are multiple parts to be debugged, , it is necessary to create a test program for that number,
The drawback was that debugging efficiency was very poor.

The present invention has been proposed in view of the above points, and its object is to provide a write module for a data flow computer that can easily perform dumping for debugging.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a bus interface that takes in data addressed to a light module from a data bus, extracts an ID and data, and converts the extracted ID into an internal ID. TRS to convert
A table, an address generation circuit that generates a predetermined address when the internal ID is a specific value and passes the internal ID as is in other cases, and an address generation circuit that generates data extracted by the bus interface. The present invention includes an address/data output circuit that writes data into the memory at a given address, and also waits for a paired address and data to be written into the memory when an internal ID is directly given.

[0008]

[Operation] In the write module of the data flow calculator of the present invention, the bus interface takes in data addressed to the write module from the data bus, extracts the ID and data, and the TRS table uses the extracted ID as an internal ID.
The address generation circuit generates a predetermined address when the internal ID is a specific value, and in the case of other internal IDs, the internal ID is passed through as is, and the address/data output circuit extracts it at the bus interface. The generated data is written into the memory using the address generated by the address generation circuit, and when the internal ID is directly given, the paired address and data are waited for and written into the memory.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a write module of a data flow computer according to the present invention.

In FIG. 1, the write module of this embodiment includes a bus interface (BIF) 12 connected to a data bus 11, a TRS table (transfer table) 13, an address generation circuit 14, and an address/data output circuit. 15 and a CNT table (control table) 16, and differs from conventional write modules in that an address generation circuit 14 is added. In addition, regarding the functions of each part, to avoid duplication,
This will be explained through the following operations.

[0012] The operation of the above embodiment will now be explained in different cases.

(1) Normal memory write operation Data 101 arriving on the data bus 11 has two tags called MSF and ID. Here, the MSF (module select flag) is a tag indicating the arithmetic module to which the data is destined, and the ID is a data identification tag that defines the processing content within the arithmetic module. Note that when writing data to the memory using the write module, the write address and write data are given as separate data.

Now, when data 101 arrives on the data bus 11, the bus interface 12 checks the MSF, and if it is addressed to its own write module, the data 101 is sent to the data bus 11.
1 is fetched, ID 102 and original data 103 are extracted, ID 102 is given to TRS table 13, and data 103 is given to address/data output circuit 15.

[0015] The TRS table 13 converts the ID 102 into an internal ID (STN) 104 according to a predetermined correspondence relationship,
It is applied to the address generation circuit 14 and the CNT table 16. Note that the TRS table outputs the same internal ID 104 for each ID added to a pair of write data and a write address. However, in that case, whether the data 103 is write data or a write address is identified by the even odd flag added to the internal ID 104.

[0016] The address generation circuit 14 generates a specific ID 102.
If a specific internal ID 104 other than that corresponding to the internal ID 104 is received, the internal ID 104 is directly provided to the address/data output circuit 15 as an internal ID 105.

The address/data output circuit 15 is an internal ID
If 105 is received, the corresponding data 103 is held until the same internal ID 105 that becomes a pair arrives, and when the pair is formed, the held data 103 and the arrived data 103 are added to the internal ID 105. The write address and write data are identified by the even-odd flag, and are given to the memory as address 106 and data 107 for writing. Upon completion of writing, a write end signal 108 is given to the CNT table 16.

CNT table 16 receives write end signal 1
At the timing when 08 is received, the internal ID 104 is converted into an MSF ID 109 and data 110 according to a predetermined correspondence relationship, and the data 110 is provided to the bus interface 12. Note that in normal writing, data 110 becomes a dummy, and M
The SF ID 109 is an end token indicating completion of writing.

The bus interface 12 receives the MS
F・ID109 and data 110 are combined, data 11
1 to other arithmetic modules (
(not shown).

(2) Dump operation during debugging Data flow If you want to dump the results of calculations in the middle of processing at any point in the computer into memory, you can use the CNT table of the calculation module (not shown) that outputs the data you want to dump. Operated externally using a debugger or the like, rewrite the MSF of the data to be dumped to information that specifies the write module as the destination, and rewrite the ID to a specific ID.

Now, when data 101 to be dumped arrives on the data bus 11, the bus interface 12
As a result of investigating, it is addressed to the own light module, so
Import that data 101, ID102 and data 10
3 is extracted, the ID 102 is given to the TRS table 13, and the data 103 is given to the address/data output circuit 15. Note that the ID 102 of the data 101 to be dumped is specific.

The TRS table 13 converts a specific ID 102 into a specific internal ID 104 according to a predetermined correspondence relationship, and provides the converted ID 104 to the address generation circuit 14 and the CNT table 16.

[0023] The address generation circuit 14 generates a specific ID 102.
When receiving a specific internal ID 104 corresponding to , it generates an address of a specific area of the memory and supplies it to the address/data output circuit 15 as a generated address 105 . Note that a predetermined number of words is secured in a specific area of the memory, and each time the address generation circuit 14 receives a specific internal ID 104,
The addresses are counted up to generate successive different addresses, and when a predetermined number of words is reached, the process returns to the first address.

When the address/data output circuit 15 receives the generated address 105, it uses the data 103 given at that time as the data 107, the generated address 105 as the address 106, and supplies these to the memory for writing. Then, upon completion of writing, a write end signal 108 is given to the CNT table 16.

CNT table 16 receives write end signal 1
MSF ID1 means an end token that interrupts processing for a specific internal ID 104 at the timing when 08 is received.
09 and data 110, and bus interface 1
Give to 2.

[0026] The bus interface 12 receives the MS
F・ID109 and data 110 are combined, data 11
1 to other arithmetic modules via the data bus 11.

Since the sent data 111 is an end token that interrupts the processing, the processing is interrupted and debugging becomes possible from the contents written in a predetermined area of the memory.

[0028]

[Effects of the Invention] As explained above, in the light module of the data flow computer of the present invention, the CNT table of the calculation module that outputs the data to be dumped can be manipulated externally using a debugger etc. without rewriting the program. Dumping can be done in a specified area of memory by simply rewriting the MSF and ID of the data you want to dump, making debugging much more efficient than the traditional method of creating test programs for as many parts as you want to debug. This has the effect of allowing you to do this.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a write module of a data flow computer of the present invention.

[Explanation of symbols]

11...Data bus 12...Bus interface 13...TRS table 14...Address generation circuit 15...Address/data output circuit 16...CNT table 101...Data 102...ID 103...Data 104...Internal ID 105...Internal ID/generated address 106...Address 107...Data 108...Writing end signal 109...MSF・ID 110...Data 111...Data

Claims (1)

[Claims] Claim 1: A bus interface that takes in data addressed to a light module from a data bus and extracts an ID and data, and a T that converts the extracted ID into an internal ID.
RS table, an address generation circuit that generates a predetermined address when the internal ID is a specific value, and otherwise passes the internal ID as is, and an address generation circuit that generates the data extracted by the bus interface. A data flow calculator characterized by comprising an address/data output circuit that writes into the memory at an address given by the ID, and waits for a paired address and data to write into the memory when an internal ID is directly given. light module.