JPH04243093A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To simplify circuits and to allow the easy execution of tests without impairing the arbitrariness to a word depth by providing a circuit for detecting and outputting that the number of the addresses assigned by an address input exceeds the number of the addresses of a memory circuit. CONSTITUTION:The semiconductor memory circuit has a memory element group 1 having a prescribed word depth direction 10 and longitudinal direction 11, a stored data input/output circuit 2, an address buffer 3, an address decoder 4, an excess address detecting circuit 5, and the terminal of an excess address signal 9. The layout of this memory circuit is disposed with the memory element corresponding to the deepest word in the uppermost position of the element 1. The circuit 5 is disposed on a decoder 4 for selecting this uppermost memory element and the excess address detection signal is outputted in correspondence to the address input exceeding the max. word depth. The number of the element is decreased in this way and the higher integration is allowed. The ease of automation is improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory circuits, and more particularly to means for detecting an address input exceeding a maximum word depth in a semiconductor memory circuit in which an arbitrary word depth can be set.

0002

2. Description of the Related Art A conventional memory circuit in which an arbitrary word depth can be set is shown in FIG.

In FIG. 5, a memory circuit with a word depth of 2 to the Nth power or less normally uses N address signals. First, a memory circuit with a word depth of 8 will be explained as an example.

Since the word depth of 8 is the cube of 2, three address signals are used. By assigning each word depth to address inputs 000[2] to 111[2], eight types of data can be stored separately. 1
A storage element corresponding to one word depth is composed of sets of several word lengths.

Even if the word depth is 7 or 5, three address signals are used to address 000[2] to 110, respectively.
By assigning to [2],000[2] to 100[2], they can be stored separately. In this case, there are 7 or 5 sets of memory elements.

That is, for any word depth W, W
W types of memory elements are made to correspond using N address signals satisfying ≦2 to the Nth power.

In conventional memory circuits, especially word depth W
is 2 to the (N-1) power<W<2 to the N power, and if the address input exceeds the word depth W, normal operation cannot be performed because there is no corresponding memory element. Therefore, a circuit for storing an arbitrary word depth W has been prepared in an external circuit that controls the memory circuit, and a logic circuit that prevents address input from exceeding the word depth W has been used.

In FIG. 5, this memory circuit includes a storage element group 1 having a predetermined word depth direction 10, word length direction 11, etc., a storage data input/output circuit 2, an address buffer 3, and an address decoder. 4, an address signal 8 and write data 6 are input, and read data 7 is output. Here, if the input of the address signal 8 exceeds the word depth, there is no corresponding memory element group 1.

[0009]

[Problems to be Solved by the Invention] In the conventional semiconductor memory circuit described above, in order to detect an address input exceeding an arbitrary word depth W, it is necessary to have a word depth W in the external circuit.
Since it is necessary to memorize the input of the memory circuit, the disadvantage is that the circuit that controls the memory circuit becomes complicated.

This drawback is especially true when a self-test circuit is inserted into a memory circuit having an arbitrary word depth. This is an obstacle to automation compatible with memory circuits.

Furthermore, it becomes extremely difficult to construct a system in which a plurality of memory circuits are tested using the same test circuit.

An object of the present invention is to provide a semiconductor memory circuit which solves the above-mentioned problems, has a simple circuit, does not impair arbitrary word depth, and can be easily tested. There is a particular thing.

[0013]

[Means for Solving the Problems] The structure of the semiconductor memory circuit of the present invention is such that, in a memory circuit having a plurality of data lines and a plurality of address lines perpendicular to the data lines, a plurality of addresses can be input in response to an address input. an address decoder circuit that selects only a predetermined address line from the data line; a memory element that has means for selectively exchanging signals from the data line according to the address line selected in response to address input; A circuit that detects the memory contents of the memory element that have been read out, a circuit that writes write data to the memory element via a data line during the write period, and a memory that has a smaller number of addresses than the number of addresses that can be selected by the address decoder. The present invention is characterized in that the circuit configuration includes a circuit that detects and outputs when the number of addresses designated by the address input exceeds the number of addresses of the memory circuit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a semiconductor memory circuit according to an embodiment of the present invention.

In FIG. 1, a semiconductor memory circuit according to an embodiment of the present invention includes a storage element group 1 having a predetermined word depth direction 10 and length direction 11, a storage data input/output circuit 2, and an address buffer. 3, address decoder 4,
It includes an excess address detection circuit 5 and a terminal for an excess address signal 9.

The difference from FIG. 5 is that an excessive address detection circuit 5 and a terminal for an excessive address signal 9 are provided at the innermost portion.

In this embodiment, the word depth direction 10 is seven, so there are three address signal lines. The layout of this memory circuit uses a method in which the logical word depth direction 10 corresponds to the physical position direction of the storage element, and the address decoder 4 also has a logical design that can realize this layout. That is, the memory element corresponding to the deepest word is arranged at the top of the memory elements in FIG.

In this embodiment, an excessive address detection circuit 5 is provided above the address decoder 4 that selects the highest storage element.
and outputs an excessive address detection signal in response to an address input exceeding the maximum word depth (111[2] in this embodiment).

FIG. 2 is a logic circuit showing an example of the excessive address detection circuit 5 of FIG. 1.

In FIG. 2, this detection circuit 5 has an AND gate and an inverter that receive address decode lines R (address signals A, B, C, and their inverted signals), Outputting to the terminal.

The logic of the excess address detection circuit 5 merely extends the logic of the address decoder 4 in the word depth direction 10.

The embodiment shown in FIGS. 1 and 2 is particularly suitable for automatic generation of memory circuits having arbitrary words, and can be applied to conventional automatic tools with only slight program changes.

FIG. 3 is a block diagram showing a semiconductor memory circuit according to another embodiment of the present invention.

In FIG. 3, this embodiment has a configuration in which excess addresses are detected from the address input itself. Other parts are the same as in FIG.

FIG. 4 shows an example of a logic circuit of the excessive address detection circuit 5 shown in FIG.

In FIG. 4, address signals 8 (A, B,
C) has an AND gate and a buffer, and outputs the excess address signal 9.

[0027]

As explained above, in the present invention, in a memory circuit having a plurality of data lines and a plurality of address lines orthogonal to the data lines, a predetermined signal can be selected from the plurality of address lines in response to an address input. An address decoder circuit that selects only an address line, a memory element that has a means for selectively exchanging signals from a data line by an address line selected in response to an address input, A circuit that detects the memory contents of a memory element that has been selected, a circuit that writes write data to the memory element via a data line during a write period, and a circuit that detects the memory contents of a memory element that has been selected by an address decoder. By comprising a circuit that detects and outputs when the number of addresses specified by the input exceeds the number of addresses of the memory circuit, the circuit that stores the input of the maximum word depth in the external circuit that controls the memory circuit is provided. In particular, in a system where multiple different memory circuits are controlled by the same algorithm because the maximum word input memory circuit itself outputs, it is possible to share the control circuit and reduce the number of elements (system 1/the number of memory circuits used in
), which is effective for high integration, especially when inserting an embedded self-test circuit into a memory circuit of arbitrary word depth, without considering the arbitrariness of word depth, which was difficult in conventional design. This has the effect of improving ease of automation because test circuits can be designed quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor memory circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an excessive address detection circuit portion of the embodiment of FIG. 1;

FIG. 3 is a block diagram showing a semiconductor memory circuit according to another embodiment of the present invention.

FIG. 4 is a circuit diagram showing an excessive address detection circuit portion of the embodiment of FIG. 3;

FIG. 5 is a block diagram showing a conventional memory circuit.

[Explanation of symbols]

1 Memory element group 2. Memory data input/output circuit 3 Address buffer 4 Address decoder 5 Excessive address detection circuit 6 Write data 7 Read data 8 Address signal 9 Excess address signal 10 Word depth direction 11 Word length direction 12 Address decode line

Claims (1)

[Claims] 1. In a semiconductor memory circuit having a plurality of data lines and a plurality of address lines intersecting the data lines, an address for selecting only a predetermined address line from the plurality of address lines in response to an address input. a decoder, a storage element having means for selectively exchanging signals from the data line by the address line selected in accordance with the address input, and the storage element read onto the data line in a read period. and a circuit for writing write data into the storage element via the data line during a write period,
A semiconductor having a smaller number of addresses than the number of addresses selectable by the address decoder, and having a circuit that detects and outputs when the number of addresses specified by the address input exceeds the number of addresses. memory circuit.