JPH04243436A - Execution history storage device - Google Patents

Abstract

PURPOSE:To make effective use of a tracer memory and to recognize execution suppression time by suppressing the writing to the tracer memory when the execution of a microcommand is suppressed. CONSTITUTION:Storing of a next execution address signal 200, a specific logic signal 400 and a counter value 600 to a tracer memory 4 is performed to the address indicated by a pointer 5, and simultaneously with the execution of storing, the value for the pointer is increased by one. In particular, when the pointer 5 indicates the last address in the tracer memory 4, the first address in the tracer memory 4 is set simultaneously with the storing, and thus the circulative use of the tracer memory 4 can be realized. When the execution of the microcommand is suppressed, the execution suppression time for the microcommand is recognized from the count value 600 stored in the tracer memory 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an execution history storage device for a data processing device employing a microprogram control system.

0002

2. Description of the Related Art In a data processing device using a microprogram control system, an execution history storage device is provided to record the execution address of the microprogram and the history of specific logic signals as a clue to clarify the cause of abnormalities or exceptions in the device. Sometimes.

In such a data processing device, microinstructions read from the control memory are stored in a microinstruction register, a part of which is decoded by a decoder.
It becomes a control signal that executes a microinstruction. At the same time, specific logic signals are stored in the tracer memory.

These operations are sequentially repeated to form a microprogram sequence, but if an abnormality or exception is detected, updating of the tracer memory is also stopped, and the microprogram stored in this tracer memory is By analyzing the execution history of , it becomes easy to find the cause of device abnormalities and exceptions.

[0005] However, since the capacity of the tracer memory is limited, it is not possible to store all the data necessary for investigating the cause of an abnormality or exception. Therefore, when data is stored in the entire storage area of the tracer memory, a method is used in which the process returns to the beginning and sequentially overwrites older data.

[0006]

[Problems to be Solved by the Invention] In the conventional execution history storage device described above, even if the execution of a microinstruction is inhibited due to various factors during the execution of a microprogram, the execution address of the microprogram or a specific logic signal cannot be stored. is recorded in the tracer memory every clock, so if microinstruction execution is inhibited for a long time, it becomes difficult to find the cause of device abnormalities or exceptions.

[0007]

[Means for Solving the Problems] The device of the present invention provides an execution history storage device for a data processing device employing a microprogram control system, which includes a microinstruction register for storing microinstructions read from a control memory, and a microinstruction register for storing microinstructions read from a control memory. Count the suppression time if execution is suppressed,
A counter that is reset when execution inhibition of a microinstruction is released, a tracer memory that stores a next execution address signal, a count value, and a specific logic signal of the microinstructions stored in the microinstruction register, and a microinstruction. means for inhibiting writing to the tracer memory when execution of the tracer memory is inhibited.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of one embodiment of the invention.

Referring to FIG. 1, this embodiment comprises a control memory 1, a microinstruction register 2, a decoder 3, a tracer memory 4, a pointer 5, a counter 6, and a microinstruction execution inhibit signal 500.

When the microinstructions constituting the microprogram stored in the control memory 1 are read out, they are stored in the microinstruction register 2. Microinstruction register 2
A part of the microinstruction stored in is decoded by the decoder 3, and a control signal 1 for executing the microinstruction is generated.
It becomes 00. On the other hand, some of the microinstructions stored in the microinstruction register 2 receive the next execution address signal 200.
Then, the address on the control memory 1 is specified and the next microinstruction is stored in the microinstruction register 2.

This series of operations forms a microinstruction execution sequence. The next execution address signal 200, specific logic signal 400, and count value 600 are stored in the tracer memory 4 at the address indicated by the pointer 5, and the value of the pointer 5 is increased by 1 at the same time as the storage. In particular, when the pointer 5 points to the last address of the tracer memory 4, the first address of the tracer memory 4 is set to the pointer 5 at the same time as storage, thereby realizing circular use of the tracer memory 4.

If the execution of a microinstruction is inhibited due to various factors during the execution of a microprogram, the microinstruction execution inhibition signal 500 becomes "ON". When the microinstruction inhibit signal 500 is turned "ON", all information necessary for executing the microinstruction including the microinstruction register 2 is held in a HOLD state until the microinstruction inhibition signal 500 is turned "OFF" again. At this time, pointer 5 is also in the HOLD state. Therefore, the next execution address signal 200, the specific logic signal 400, and the count value 600 are stored in the tracer memory 4 at the same location.

The counter 6 receives a microinstruction inhibit signal 500
The number of clocks is counted while the microinstruction inhibit signal 500 is "ON", and is reset when the microinstruction inhibit signal 500 becomes "OFF". The number of clocks is not counted while the microinstruction inhibit signal 500 is "OFF". The count value 600, which is the output of this counter, is stored in the tracer memory 4 together with the next execution address signal 200 and the specific logic signal 400.

By reading out the history of the series of next execution address signals 200 and specific logic signals 400 stored in the tracer memory 4, it is possible to know the execution history of the microprogram up to the stop. When execution of an instruction is inhibited, the execution inhibition time of the microinstruction can be determined from the count value 600 stored in the tracer memory 4.

[0016]

[Effects of the Invention] According to the present invention, when the execution of a microinstruction is inhibited due to various factors during the execution of a microprogram, the tracer memory can be effectively utilized by inhibiting writing to the tracer memory. In addition, since the execution inhibition time can also be known, even if the execution of a microinstruction is inhibited for a long time, it is possible to obtain important information for investigating the cause of a problem when it occurs.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention.

[Explanation of symbols]

1 Control memory 2 Microinstruction register 3 Decoder 4 Tracer memory 5 Pointer 6 Counter

Claims (1)

[Claims] Claim 1: An execution history storage device in a data processing device employing a microprogram control method, comprising:
a microinstruction register that stores microinstructions read from control memory; a counter that counts the inhibition time when the execution of the microinstruction is inhibited; and a counter that is reset when the inhibition of the execution of the microinstruction is released; a tracer memory that stores a next execution address signal, the count value, and a specific logic signal of the microinstructions stored in the instruction register; and a tracer memory that inhibits writing to the tracer memory when execution of the microinstruction is inhibited. An execution history storage device comprising: means.