JPH0424573A - Testing method of ic - Google Patents

Abstract

PURPOSE:To prepare a test pattern in a short time even when the number of terminals is large, by comparing an output logic value as an expected value of an IC terminal with an output logic value obtained by supplying thereto a signal voltage based on impressed data and by measuring an output DC voltage or current when these values coincide with each other. CONSTITUTION:A selection circuit 22 changes over a pattern memory 11 to an expected value data register 21 and supplies expected value data to a logic comparison circuit 15, while a measuring terminal selection register 23 switches over the selection circuit 22. A control element 18 starts a sequence control, a test signal from a signal forming circuit 12 generated on the basis of impressed data from the pattern memory 11 is converted into a signal voltage in a driver 13 and the voltage is supplied to a terminal of IC 1. Meanwhile, a voltage obtained at the terminal of the IC 1 is compared with a reference voltage by a comparator 14 and a comparison output is compared with the expected value data in the logic comparison circuit 15. When an actual output logic value of the logic comparison circuit 15 differs from an expected value, a stop signal is not supplied to the control element 18 from an AND gate 24 and an OR gate 25. When it coincides with the expected value, in contrast, the stop signal is supplied thereto to stop the sequence control, and an output DC voltage or current is measured in a DC measuring circuit 16.

Description

Detailed Description of the Invention "Industrial Application Field" This invention relates to a method for testing an IC (semiconductor integrated circuit), and in particular to a method for testing an output DC voltage or output DC current when the output logic value of an IC terminal is a predetermined value. Concerning how to measure.

"Conventional Technology J In testing ICs such as logic integrated circuits, a logic level test signal is formed from applied data, which is a type of test pattern, and the test signal is converted to a signal voltage such as ECL level or TTL level. At the same time, the voltage obtained at the IC terminal is compared with a reference voltage, and the comparison output is compared with expected value data, which is a type of test pattern, to determine whether the IC is good or not. Not, but
The output DC voltage or output DC current is sometimes measured when the output logic value of the IC terminal is a predetermined value, but conventionally, this output DC voltage or output DC current has been measured based on the expected value in the preliminary test pattern. This is done by detecting a test cycle in which the output logic value first becomes a predetermined value for each terminal for which the output DC voltage or output DC current of the IC is to be measured from the data, and instructing that test cycle.

FIG. 3 shows an example of an IC test system that implements the conventional IC test method, including a pattern memory 11, a signal forming circuit 12,
, driver 13, comparator 14, logic comparison circuit 15
A DC measurement circuit 16 is provided individually for each necessary terminal of the ICI, and test patterns for the necessary terminals of the ICI are formed in advance in a main control section 17 having a computer and stored in the pattern memory 11 through a sequence control section 18. However, in this case, the main control unit determines the test cycle in which the output logic value of each terminal for which the output DC voltage or output DC current of the ICI is to be measured first becomes a predetermined value based on the expected value data in the test pattern. 1
7 and held in the main control section 17. That is, terminals Pa and Pb at which the output DC voltage or output DC current of the ICI is to be measured.

The expected value data in the test pattern for Pc... is as shown in Figure 2, and the terminals Pa, P
When measuring the output DC voltage or output DC current when the output logic value of b, Pc... is logic 1, the terminal Pa
For the terminal Pb, a value indicating the test cycle ■ is held, for the terminal Pb, a value indicating the test cycle ■, and for the terminal Pc, a value indicating the test cycle ■ is held in the main control unit 17.

First, the main control section 17 sets the cycle number counting circuit 19 to a value "4°" indicating the test cycle ■ for the terminal Pa, and then the main control section 17 sets the sequence control section 18 to the sequence control section 18. When control is started, applied data is read out from the pattern memory 11 in order from test cycle 1, a logic level test signal is obtained from the signal forming circuit 12 based on the applied data, and the test signal is changed to an ECL level in the driver 13. At the same time, the voltage obtained at the ICI terminal is compared with a reference voltage in the comparator 14, and the comparison output is converted into a signal voltage such as TTL level or the like and supplied to the ICI terminal. It is compared with the expected value data read out from the memory 11. In this case, for each test cycle, the sequence control unit 18 increases the count value in the cycle number counting circuit 19 by 1, and the cycle number counting circuit 19 , it is detected whether the counted value matches the above-mentioned set value.

In the above example, in the test cycle ■, when the count value matches the set value, a stop signal is supplied from the cycle number counting circuit I9 to the sequence control unit 18, and the sequence control unit I8 stops the sequence control, Output DC voltage or output DC current when the output logic value of terminal Pa is logic 1 in the DC measurement circuit 16 connected to terminal Pa is measured.

In the above example, the main controller 17 then sets the cycle number counting circuit 19 to the value "2" indicating the test cycle ■ for the terminal Pb, and then the main controller 17 causes the sequence controller 18 to perform sequence control. The logic test as described above is performed in order from test cycle T, and when test cycle H is reached, the count value in cycle number counting circuit 19 matches the set value, so that the cycle number counting circuit 19 performs the logic test in sequence control section. A stop signal is supplied to the sequence controller 18, the sequence control unit 1 stops sequence control, and the output DC voltage when the output logic value of the terminal pb of the DC measurement circuit 16 connected to the terminal Pb is logic 1. Or the output DC current is measured. The same applies hereafter.

[Problem to be Solved by the Invention] However, in the conventional IC testing method described above, the main point is to measure the output DC voltage or output DC current when the output logic value of the ICI terminal is a predetermined value. When forming a test pattern for the necessary terminals of the ICI in the control unit 17, the output logic value is first determined for each terminal for which the output DC voltage or output DC current of the ICI is to be measured based on the expected value data in the test pattern. Since the test cycle in which the predetermined value ζ is to be reached is detected and the test cycle is instructed to the cycle number counting circuit 19, there is an inconvenience that it takes a lot of time to create a test pattern, especially when the number of ICI terminals is large. be.

Accordingly, the present invention provides a method for measuring output DC voltage or output DC current when the output logic value of an IC terminal is a predetermined value, in which a test pattern can be created in a short time even when the number of IC terminals is large. It was made so that it could be done.

"Means for Solving the Problem" In the present invention, when measuring the output DC voltage or output DC current of the terminal of the IC, the output logic value of the terminal of the IC is set as an expected value, and the data applied to the IC is Compare it with the output logic value of the terminal of the IC obtained by supplying the original signal voltage, and when the two match, measure the output DC voltage or output DC current of the terminal of the IC, and use this as the output logic value of the terminal of the IC. The output DC voltage or output DC current of the IC is sequentially measured for each terminal to be measured.

"Function" In the IC testing method of the present invention that takes the above method, the output DC voltage or output DC current of the IC is measured for each terminal for which the output DC voltage or output DC current is to be measured. The output logic value as an expected value is successively compared with the output logic value obtained by supplying a signal voltage based on the applied data to the IC, and when the two match, the output DC voltage or output DC current is measured. , when creating a test pattern, detect the test cycle in which the output logical value should first reach a predetermined value for each terminal for which the output surface fL voltage or output DC current of the IC is to be measured from the expected value data in the test pattern. This is not necessary, and test patterns can be created in a short time even if the IC has a large number of terminals.

[Embodiment J] FIG. 1 shows an example of an IC test system that implements the IC test method of the present invention, and includes a pattern memory 11, a signal forming circuit 12, a driver 13, a comparator 14, a logic comparison circuit 15, and a DC measurement circuit 16. The expected value data register 2 is provided individually for each necessary terminal of the ICI.
1. A selection circuit 22, a measurement terminal selection register 23, and an AND gate 24 are provided individually for each necessary terminal of the ICI, and an OR gate 25 is also provided. The expected value data register 21 is set with expected value data by the main control unit 17 as described later, and the selection circuit 22 is configured to set expected value data from the pattern memory 11 and the expected value from the expected value data register 21. The data is switched and supplied to the logic comparison circuit 15, and the measurement terminal selection register 23 is set to one of them by the main control unit 17, as described later, and set to "0" to all others. °
" is set, and the selection circuit 22 is switched according to its output, the AND gate 24 obtains the AND of the output of the measurement terminal selection register 23 and the output of the logic comparison circuit 15, and the OR gate 25 and gate 24
The logical sum of the respective outputs is obtained and the output is supplied to the sequence control section 18 as a stop signal.

In advance, a test pattern for the necessary terminals of the ICI is formed in the main control section 17 and stored in the pattern memory 11 through the sequence control section 18. However, as mentioned above, the test cycle in which the output logic value should first reach the predetermined value for each terminal for which the output DC voltage or output DC current of IC1 is to be measured is detected from the expected value data in the test pattern. It never happens.

The expected value data in the test pattern for the terminals Pa, Pb, Pc, etc. for which the output DC voltage or output DC current of the ICI is to be measured is as shown in Fig. 2, and the terminals PaPb, Pc... When measuring the output DC voltage or output DC current when the output logic value of . “1°” is set as the value data, and “1” is set in the measurement terminal selection register 23 corresponding to the terminal Pa.
is set, and all others are set to "0".

Next, the main control unit 17 causes the sequence control unit 18 to start sequence control, and sequentially from test cycle I,
Application data is read from the pattern memory 11, a logic level test signal is obtained from the signal forming circuit 12 based on the application data, and the test signal is converted into a signal voltage such as an ECL level or TTL level in the driver 13, and is then converted to an ICI signal. The voltage obtained at the terminal of the ICI is compared with the reference voltage in the comparator 14, and the comparison output is sent to the logic comparison circuit 1.
5, it is compared with expected value data.

In this case, since the measurement terminal selection register 23 is set to 0'' for the terminals other than the ICI terminal Pa as described above, the selection circuit 22 receives the expected value data read from the pattern memory 11. It is taken out and supplied to the logic comparison circuit 15, but since the output of the measurement terminal selection register 23 is "0'", the output of the AND gate 24 is 0 regardless of the output of the logic comparison circuit 15.
On the other hand, for the terminal Pa of the ICI, since "1°' is set in the measurement terminal selection register 23 as described above, the selection circuit 22 receives the expected value from the expected value data register 21. Value data is extracted and supplied to logic comparison circuit 15.

Therefore, test cycle 1. n, [1, the expected value data from the expected value data register 21 corresponding to the terminal Pa is 1'', but the output logical value actually obtained at the terminal Pa is logical 0. , the output of the logic comparison circuit 15 corresponding to the terminal Pa is 0'' indicating that the actual output logic value is different from the expected value.
Then, the output of the AND gate 24 corresponding to the terminal Pa also becomes "0°", and the output of the OR gate 25 becomes "0°".
In other words, the stop signal is not supplied from the OR gate 25 to the sequence control unit 18, but the test cycle
Then, while the expected value data from the expected value data register 21 corresponding to the terminal Pa is "l", the output logical value actually obtained at the terminal Pa is also logical 1, so that the logical comparison is performed. The output of the circuit 15 corresponding to the terminal Pa becomes ``1'', indicating that the actual output logic value matches the expected value, and the output of the measurement terminal selection register 23 corresponding to the terminal Pa becomes ``I''. Therefore, the output of the AND gate 24 corresponding to the terminal Pa becomes "1", and the output of the OR gate 25 becomes "1".

That is, in the test cycle ■, the terminal Pa of the ICI
When the actual output logic value becomes logic 1, a stop signal is supplied from the OR gate 25 to the sequence control unit 1, and the sequence control unit I8 stops the sequence control,
Output DC voltage or output DC current when the output logic value of terminal Pa is logic 1 in the DC measurement circuit 6 connected to terminal Pa is measured.

In the above example, next, the main control unit 17 sets "pi" as the expected value data to the one corresponding to the terminal pb of the expected value data register 21, and sets "pi" to the one corresponding to the terminal Pb of the measurement terminal selection register 23. “°1”” is set, and all others are set to “0°°,” and then the main control unit 17 causes the sequence control unit 1B to start sequence control and perform the logic test as described above sequentially from test cycle I. Therefore, as is clear from the above, when the actual output logic value of the terminal Pb of the ICI becomes logic 1 in the test cycle H, a stop signal is supplied from the OR gate 25 to the sequence control section 1B. The sequence control unit 18 stops the sequence control, and the output DC voltage or output DC current when the output logic value of the terminal pb is logic 1 in the DC measurement circuit 16 connected to the terminal Pb is measured. From now on,
The same is true.

When measuring the output DC voltage or output DC current when the output logic values of the terminals Pa, Pb, Pc, etc. are logic O, the terminals Pa, Pb, Pc of the expected value data register 21
. . . "0" may be sequentially set as the expected value data.

Note that the actual logic test is performed on a different occasion from the above-mentioned measurement of the output DC voltage or output DC current.

[Effect of the Invention J As described above, according to the present invention, the expected value when measuring the output DC voltage or output DC current is calculated for each terminal for which the output DC voltage or output DC current of the IC is to be measured. The test pattern When creating a test pattern, there is no need to detect the test cycle in which the output logic value should first reach a predetermined value for each terminal where the output DC voltage or output DC current of the IC is to be measured from the expected value data in the test pattern. Even when the number of terminals of an IC is large, test patterns can be created in a short time.

[Brief explanation of drawings]

Fig. 1 is a system diagram showing an example of an IC test system that implements the IC test method of the present invention, and Fig. 2 shows a test pattern for each terminal for measuring the output DC voltage or output DC current of the IC. FIG. 3 is a diagram showing a part of an example of expected value data of
It is a system diagram showing an example of a C test system.

Claims (1)

[Claims] (1) When measuring the output DC voltage or output DC current of the IC terminal, the output logic value of the above-mentioned terminal of the above-mentioned IC is set as the expected value, and is obtained by supplying the above-mentioned IC with a signal voltage based on the applied data. Compare with the output logic value of the terminal of the IC, and when the two match, measure the output DC voltage or output DC current of the terminal of the IC,
An IC testing method in which this is performed sequentially for each terminal of the IC whose output DC voltage or output DC current is to be measured.