JPH04246722A - Adder/subtracter - Google Patents

Abstract

PURPOSE:To execute the addition or the subtraction of an operation of an absolute value with a code bit at a high speed. CONSTITUTION:A parallel absolute value arithmetic part 11 inputs absolute value parts ¦A¦ and ¦B¦ of an operated number A and an operand B and executes addition (¦A¦+¦B¦), subtraction (¦A¦-¦B¦) and subtraction (¦B¦-¦A¦), and sends a result of these three operations, and a large/small comparing signal BA-B of ¦A¦ and ¦B¦ to a selector block 12. To the selector block 12, code bits Sa and Sb of the operated number A and the operand B, an addition/subtraction switching signal Add/Sub, said three operation results sent from the parallel absolute value arithmetic part 11, and the signal BA-B are inputted. The selector block 12 outputs a code bit S of a result of operation, based on the input signal, and also, selects one from in (¦A¦+¦B¦), (¦A¦-¦B¦), and (¦B¦-¦A¦) and outputs it with respect to a result of operation D of a final absolute value part.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder/subtractor which is an arithmetic circuit made of a semiconductor circuit, and more particularly to an adder/subtractor which handles absolute value data.

0002

2. Description of the Related Art The functions of a general adder/subtractor are shown in Table 1, and the overall configuration of a conventional adder/subtractor is shown in FIG.

0003

[Table 1]

Table 1 shows the sign bits sa and sb of operand A and operand B, and the sign bits sa and sb of operand A and operand B, respectively.
The sign bit S of the operation result for the magnitude of the absolute value part of
This shows the correspondence between the absolute value part calculation and the absolute value part calculation to be executed. sa, sb, and S are the signs of the original numbers expressed by absolute values, and are set to 1 when they are negative. Also, A≧B means that the operand A
When the absolute value part of is greater than or equal to the absolute value part of the arithmetic number B, it is set to 1, and otherwise it is set to 0. × indicates that either 1 or 0 is acceptable.

In a conventional adder/subtractor, operands A (=sa am-1 . . . a2 a1 ) each having a bit length m are expressed as absolute values and include one sign bit in the most significant bit.
In order to execute the addition A+B or subtraction A-B of the operation number B (=sb bm-1 . . . b2 b1 ), it was necessary to perform the following two steps.

As a first step, the absolute value part of the operand A and the absolute value part of the operand B are compared in magnitude.

[0007] As a second step, the results of comparing the magnitudes of the absolute value parts of operand A and operand B obtained in the first step, the sign bits of operand A and operand B, and the subtraction The sign bit of the operation result is determined from the selection signal for addition or addition, and at the same time subtraction or addition of the absolute value part is executed.

Referring to FIG. 4, the operation of a conventional absolute value adder/subtracter that performs the above-mentioned arithmetic processing will be explained. In FIG. 4, ALB (“ALB” means “A is less than B”)
The detection circuit 41 is a circuit that compares the absolute value parts of the operand A and the operand B. This ALB detection circuit 41
are the absolute value parts of operand A and operand B |A| and |B
| is input, and if |A|≧|B|, then the magnitude comparison signal (A
:B)=1 is output, and if |A|<|B|, a magnitude comparison signal (A:B)=0 is output. At this time, inside the ALB detection circuit 41, carry propagation is performed to generate a borrow signal (A:B), which is a magnitude comparison signal of the absolute value part, by executing the operation (|A|-|B|). occurs once. next,
The control signal generation circuit 42 generates the sign bits sa and sb of the operands A and B, the addition or subtraction switching signal Add/Sub, and the magnitude comparison signal (
A:B) are input, and the code bit S which is the calculation result is calculated and outputted, and at the same time, the calculation mode signal Mode is outputted to the Add/Sub calculation unit 43. The Add/Sub arithmetic unit 43 receives the arithmetic mode signal M from the control signal generation circuit.
ode, addition (|A|+|B|), subtraction (|A
One of the three types of operations, |−|B|) and subtraction (|B|−|A|), is executed, and the operation result D of the absolute value part is output. At this time, propagation of the carry due to the calculation occurs once inside the Add/Sub calculation unit 43 as well.

As described above, in the conventional adder/subtractor, the calculation is performed in two steps, so carry propagation occurs twice in the actual calculation. That is, the carry propagates once in order for the ALB detection circuit 41 to compare the absolute value parts |A| and |B| of the operand A and the operand B, and the Add/Sub operation unit 4
When executing the operation in 3, the carry is propagated one more time.

0010

[Problem to be Solved by the Invention] Conventionally, when adding or subtracting absolute values, first the magnitudes of the absolute value parts of operand A and operand B are compared, and then the magnitude of the absolute value parts of operand A and operand B are compared. Based on the number B of sign bits and the result of the magnitude comparison, the sign bit of the calculation result is determined and the absolute value part is calculated. Therefore, carry propagation occurs twice in the entire calculation, which is disadvantageous for high-speed calculation.

The present invention has been made in view of this problem, and it reduces the number of carry propagations in addition or subtraction of operands A and B expressed as absolute values with sign bits, thereby achieving high-speed calculations. The purpose is to provide an adder/subtractor that allows

0012

[Means for Solving the Problems] The adder/subtractor according to the present invention has operands A (= sa am-1
...a2 a1 ) and the operational number B (=sb bm-1 ...
In the adder/subtractor that adds and subtracts the numbers A and B, the addition (|A
|+|B|), subtraction (|A|-|B|), subtraction (|B|-|A|), and subtraction (|B|-|A|).
means for generating a borrow signal of |A|-|B|), the calculation result of the addition (|A|+|B|), and the subtraction (|A|-|
The operation result of B|), the operation result of subtraction (|B|-|A|), the borrow signal of subtraction (|A|-|B|), the sign bit of operand A and operation number B, and the addition or and means for outputting the sign bit and absolute value part of the result of addition or subtraction of the operand A and the operand B based on the subtraction switching signal.

[0013]

[Operation] In the adder/subtractor of the present invention, addition (|A|+|B|) is an absolute value operation of the operand A and the operand B.
, subtraction (|A|-|B|), and subtraction (|B|-|A|); and selector means for determining the sign bit of the operation result and selecting the operation result of the operation block. Because of this configuration, absolute value calculation with sign bit is executed by one carry propagation.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows the overall configuration of an absolute value adder/subtractor according to an embodiment of the present invention.

In FIG. 1, the parallel absolute value calculation unit 11 is
Absolute value parts of operand A and operand B, respectively |A| and |
B| is input, addition (|A|+|B|), subtraction (|A
Three types of operations, |−|B|) and subtraction (|B|−|A|), are executed in parallel, and the results of each operation are output to the selector block 12.

The selector block 12 also compares the sign bits sa and sb of the operands A and B, the switching signal Add/Sub for addition or subtraction, and the magnitudes of |A| and |B| A borrow signal BA-B of (|A|-|B|) calculated by the parallel absolute value calculation unit is input as a signal. Then, the selector block 12 determines the sign bit S of the operation result from the input data, and at the same time, the addition (|A|+|B|) and subtraction ( One of |A|-|B|) and subtraction (|B|-|A|) is selected and output as the calculation result.

Table 2 shows the functions of this selector block.

[0019]

[Table 2]

[0020] In Table 2, × indicates that either 1 or 0 is acceptable.

As shown in Table 2, selector block 12
outputs corresponding outputs for each combination of four inputs. The carry propagation only needs to be carried once because the parallel absolute value calculation unit 11 performs parallel calculations.

FIG. 2 shows 1 of the parallel absolute value calculation section 11 in FIG.
The configuration of an equivalent circuit corresponding to bits is shown.

The circuit of FIG. 2 operates on input signal Ai
, calculation input signal Bi , |A|+|B| carry input signal for addition CIA+B, |A|-|B| carry input signal for subtraction CIA-B, and |B|-|A| carry for subtraction Input signals CIB-A are input, and depending on their values,
|A|+|B|Addition result output signal DA+B, |A|-
|B| Subtraction result output signal DA-B, |B|-|A| Subtraction result output signal DB-A, |A|+|B| Carry output signal for addition COA+B, |A|-|B| For subtraction This circuit outputs a carry output signal COA-B and a carry output signal COB-A for subtraction, respectively. ｜
A|+|B|Addition result output signal DA+B, |A|-|
B | Subtraction result output signal DA-B, |B|-|A| Subtraction result output signal DB-A, |A|+|B| Carry output signal for addition COA+B, |A|-|B| Digit for subtraction The carry output signal COA-B and |B|-|A| carry output signal COB-A for subtraction are expressed by the following equations 1 to 6, respectively.

[0024]

[Math 1]

[0025]

[Math 2]

[0026]

[Math 3]

[0027]

[Math 4]

[0028]

[Math 5]

[0029]

[Formula 6] In the parallel absolute value calculation unit 11 of FIG.
When the respective absolute value parts |A| and |B| are input, the circuit as described above generates the addition result (|A|+|B|), the subtraction result (|A|-|B|) and (| B|−|A|) can be obtained at the same time.

FIG. 3 shows the configuration of an equivalent circuit of the selector block 12 of FIG. 1. The selector block 12 implements the truth table of Table 2 as described above. Figure 3
is an example of an equivalent circuit of the selector block 12, and since the operation is simple, a detailed explanation of the operation will be omitted here.

As described above, the addition or subtraction of operands A and B expressed as absolute values with sign bits, which was conventionally accomplished by two carry propagations, can be accomplished by one carry propagation. Since it is executed in , it is possible to perform calculations at high speed.

[0032]

As described above, according to the present invention, the operand A and the operand B expressed as absolute values with sign bits
addition or subtraction can be performed with one carry propagation, reducing the number of carry propagations in the operation,
It is possible to provide an adder/subtractor that enables high-speed calculations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an adder/subtractor according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the parallel absolute value calculation section in FIG. 1;

FIG. 3 is an equivalent circuit diagram of the selector block in FIG. 1.

FIG. 4 is a block diagram showing the overall configuration of an example of a conventional adder/subtractor.

[Explanation of symbols]

11; Parallel absolute value calculation section 12; Selector block

Claims (1)

[Claims] Claim 1: An operand A (=
sa am-1 ... a2 a1 ) and the operation number B (=sb
bm-1 ... b2 b1 ), based on the absolute value parts of operand A and operand B, the operation result of addition (|A|+|B|) and subtraction (|A|
-|B|), a calculation result of subtraction (|B|-|A|), and means for generating a borrow signal of subtraction (|A|-|B|); The calculation result of B|), the calculation result of subtraction (|A|-|B|), the calculation result of subtraction (|B|-|A
Based on the operation result of |) and the borrow signal of subtraction (|A|-|B|), the sign bit of operand A and operation number B, and the addition or subtraction switching signal, An adder/subtractor comprising means for outputting a sign bit and an absolute value part of a result of addition or subtraction of a number B.