JPH0424748A - Parallel processing processor - Google Patents

Abstract

PURPOSE:To eliminate the fear of the processing order of a process being impaired, and to raise the processing ability of the side to entrust the processing of a sub-process by forming a reservation table by storing the start address information of the sub-process on a memory, and providing a sub-process starter which retrieves the start address information and executes the sub-process. CONSTITUTION:A program starting means 100, instruction selecting means 1-3, a memory 200, a data bus 30, a context controller 7, a table generating means 8 which forms the reservation table, and first and second sub-process starters 21, 22 are provided. Then, there is an actuation to entrust the pressing of the sub-processor from a first processor part through the reservation table 40 to second and third processor parts. Thus, there is no fear that the processing order of the process is impaired, and the processing ability of the side that entrusts the processing of the sub-process is raised.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the structure of an instruction processing mechanism of a microprocessor.

2. Description of the Related Art In recent years, software programming type microprocessors have been widely used in various fields. Data input/output means (corresponding to data memory and input/output ports) whose addresses are specified by instructions stored in the program storage means, and data calculation based on instructions sent from the program storage means (data memory and input/output ports). It is characterized by comprising a calculation means for executing the above, and a data bus connecting the data input/output means and the calculation means.A typical configuration thereof is disclosed in Japanese Patent Publication No. 58-3358.
This is shown in Publication No. 4.

Microprocessors with this software programming method can be used for a variety of purposes, but on the other hand,
When used as a controller for some devices that require high-speed processing, it lacks real-time processing ability compared to a dedicated controller configured with wired logic, as shown in Japanese Patent Application No. 62-69351. Microprocessors with multiprocessing configurations have been proposed.

Microprocessors with multi-processing configurations have multiple processing processes running in parallel, which greatly improves real-time processing ability, but on the other hand, there are problems with the processing order of processes and the ability to keep pace between each process. there were.

Problems to be Solved by the Invention Accordingly, an object of the present invention is to improve the synchronization between processes in a microprocessor having a multiprocessing configuration more than ever before.

Means for Solving the Problems In order to solve the problems described above, the parallel processing processor of the present invention has a first configuration including a program storage means for storing a program consisting of a group of instructions to be executed sequentially, and a program storage means for storing a program consisting of a group of instructions to be executed sequentially. The first step is to sequentially select the stored instructions.
．． Second. a third instruction selection means; a memory having a plurality of addresses and whose contents are readable and writable; a data bus coupling between the memory and the program storage means; Second. a context controller that sequentially allocates execution cycles of the instructions selected by the third instruction selection means; and a context controller that stores the start address information of the child process in the memory according to the instructions via the first instruction selection means and creates a reservation table. first and second child processes that execute a child process by searching start address information stored in the reservation table according to an instruction via the second or third instruction selection means; Equipped with a starter.

In addition, in order to solve the above-mentioned problems, A"!1 of the present invention
1% raccoon dog? As a second configuration, the tygo has a program storage means for storing a program consisting of a group of instructions to be executed sequentially, a memory having a plurality of addresses and whose contents can be read and written, and the memory and the program. a data bus coupling between the storage means; and a first. Second. a third processor; table forming means for storing start address information of a child process on the memory by the first processor to form a reservation table; The child process is the second.
The apparatus includes first and second child process starters that are executed by a third processor, and a process distributor that suppresses the operation of one of the child process starters while the other child process starter is in operation.

Furthermore, in order to solve the above-mentioned problems, the present invention has a method for separating grains. 0-□, as a third configuration, in addition to the second configuration, when the first processor starts operating, the process distributor is configured to inform the process distributor that the first child process starter is operating. and initialization means for providing a pseudo signal shown in FIG.

Operation In the present invention, by the above-described first configuration, from the first processor section to the second processor section. Since the processing of the child process is entrusted to the third processor section via the reservation table, there is no fear that the processing order of the processes will be impaired, and the processing capacity of the side to which the processing of the child process is entrusted is increased.

Furthermore, the above-mentioned second configuration allows the second. Contention of the third processor is suppressed, and as a result, inter-process synchronization is improved.

Further, according to the third configuration described above, the first processor section is connected to the second processor section. The first processing is entrusted to one of the processor sections of the third processor section preferentially, and the processing order among the processors is also determined.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a parallel processing processor according to a first embodiment of the present invention, and includes an instruction ROM 100 in which a program consisting of a group of instructions to be executed sequentially is stored.
The instructions selected by the first to third programmable counters 1 to 3 are sent to an instruction queue 4 for holding and pre-reading instructions. The instruction once held in the instruction queue 4 is sent to the instruction decoder 5, and its address index part is sent to the address bus 10. A group of control signals produced by the instruction decoder 5 are supplied via a control bus 20 to each block making up the microprocessor. Further, a plurality of timing signals for processing by the microprocessor are generated in the timing generator 6, and these timing signals are supplied to each block via the controller bus 20. Address bus 10 and first to third programmable counters 1 to 3. First to third address registers 11 to 13. The data buses 30 are connected to each other so as to send address data to each other. 1st to 3rd
The address registers 11 to 13 of the RAM 200.
Holds the address of the general-purpose parallel input/output port 300. The three groups of input/output lines of the general-purpose parallel input/output port 300 are AO to A15 terminals, BO to B15 terminals,
A, B, configured by CO to C15 terminals
It is connected to the input/output terminal group of group C. Furthermore, the data bus 30 includes a first register 14 and a second register 1.
The input part of ALUle is connected through 5, and the ALUle
The output of is supplied to an accumulator unit 17 (which also includes a group of flags). The accumulator unit 17 and data bus 30 are also connected via a bidirectional bus.

On the other hand, the timing signal from the timing generator 6 is also supplied to the context controller 7, and the first output signal f1 of the context controller 7 is supplied to the first programmable counter 1 and the first address register 11 as an operation enable signal. , the second output signal f2 is supplied to the second programmable counter 2 and the second address register 12, and the third output signal f3 is supplied to the third
is supplied to the programmable counter 3 and the third address register 13.

The microprocessor shown in FIG. 1 includes a first processor section mainly composed of a first programmable counter 1 and a group of instructions retrieved by it, and a second programmable counter 2 and a group of instructions retrieved by it. It has a second processor section configured as a center, and a third processor section configured mainly around a third programmable counter 3 and a group of instructions fetched by the third programmable counter 3. Second. Each of the third processor sections includes an instruction ROM 100. Address bus 10, data bus 30. RAM200. General purpose parallel input/output capo) 300. We share ALUle etc.

Now, inside the RAM 200, there is a reservation pointer 8 for forming a reservation table 40 that stores the start address information of the child process, and an execution pointer 9 for executing the child process whose start address information is stored in the reservation table 40. A first child process starter 21 activated by the second processor unit and a first child process starter 22 activated by the third processor unit are formed,
The reservation pointer 8 is activated by the third output signal f3 of the context controller 7, and the execution pointer 9 is activated by the first or second output signal fl, f of the context controller 7.
2, each is configured such that its operation is permitted.

It is assumed that the data output section of each block has a three-state configuration, and is maintained in a high impedance state during a period when data output is not required. Further, it is assumed that necessary timing signals and control signals are supplied to each block via the control bus 20.

The operation of the parallel processing processor configured as described above will be explained with reference to the configuration diagram shown in FIG. 1 and the timing chart of the main parts shown in FIG. 2.

First, Figure 2A is the external clock input terminal CLK in Figure 1.
2B, C, D, and E each show the signal waveform of the basic timing signal output from the timing generator 6. F1 to F3 indicate first to third output signals f1 to f3 of the context controller 7, respectively.

Now, in the parallel processing processor shown in Fig. 1, the instruction RO
The instruction taken out from M100 is temporarily held in the instruction queue 4, and then the instruction decoder 5 interprets the processing content and executes it. The instruction queue 4 has first to third buffers 4A to 4C, the first buffer 4A and the second buffer 4A to 4C.
The buffer 4B forms a FIFO (first-in-first-out) stack, and stores the first byte of the instruction taken out by the first programmable counter 1 and the first byte of the instruction taken out by the second programmable counter 2. The first byte, and further the first byte of the instruction taken out by the third programmable counter 2, is configured to be stored sequentially. Also,
Judging from the first byte of the instruction code stored in the second bus 4B, if the instruction involves a second byte, the second byte of the instruction is stored in the third /'y node 4C. Ru.

The signal in FIG. 2B is used as a timing signal to precharge the address decoder included in the RAM 200 to determine the selected address, and the signal in FIG.
It is used as a timing signal for reading data from the AM 200 or the general-purpose parallel input/output port 300 onto the data bus 30.

Further, the signal in the second diagram is transmitted from the data bus 30 to the RAM 20.
The leading edge of the timing signal shown in FIG. 2E is the read timing, and the trailing edge is the write timing.

Here, the C interval in FIG. 2 is assigned to the execution interval of the instruction fetched by the first programmable counter 1, the b interval is assigned to the execution interval of the instruction fetched by the second programmable counter 2, and C Assuming that the interval is assigned to the execution interval of the instruction taken out by the third programmable counter 3, at time t
In order to transfer data at a specific address in the RAM 200 to the accumulator unit 17 in the period b from time t1, that address must be held in the second address register 12 before time t1. In the parallel processing processor of FIG. 1, C from time 10 to time t1 is
During the interval, that is, while executing the instruction stored in the first buffer 4A of the instruction queue 4, the context controller 7 supplies the operation enable signal shown in FIG. 2F to the second address register 12. However, if the instruction stored in the second buffer 4B of the instruction queue 4 is an instruction whose second byte includes address information of the RAM 200 or the general-purpose Halal input/output port 300, the third buffer 4C and the address bus 10 The new address supplied via the address register 12 is written to the second address register 12. Further, the operation enable signal from the context controller 7 is also supplied to the first to third programmable counters 1 to 3, and each time the C interval, b interval, or C interval in FIG. 3
It is also used to update the count values of programmable counters 1 to 3.

In this way, in the parallel processing processor shown in FIG.
Since instructions are read from the computer and executed sequentially, the real-time performance of processing in response to ever-changing external events is improved.

Now, in the parallel processing processor shown in FIG.
Processing is entrusted to the third processor unit in the form of a child process, and this process will be explained.

FIG. 3 shows the detailed structure of the reservation table 40 in FIG. 1. Four areas from address 0 to address 3 on the 16-bit memory are allocated as a reservation table for the child process. are assigned as a reservation pointer 8 and an execution pointer 9. Also, reserved table 4
The MSB (D15) of the first to fourth areas of 0 is used as a reservation flag, and is set when a child process is entrusted from the first processor unit, and when execution of the child process is started by the second processor unit. It will be reset when On the other hand, the remaining 15 bits in each of the first to fourth areas store the start address of the child process.

When the first processor section entrusts the execution of a child process to the second or third processor section, it checks the MSB of the area indicated by the reservation pointer 8 among the first to fourth areas, and the MSB is set. If not, the start address of the child process is stored, the MSB is set, and the value of reservation pointer 8 is incremented.

On the other hand, the second processor section performs operations based on the flowchart shown in FIG. In the processing block 51 and branch 52 in FIG. 4, the MSB of the area indicated by the execution pointer 9 is checked, and if the MSB is set, it is reset, the value of the execution pointer 9 is incremented, and the value before the increment is Starts execution of the child process whose start address is stored in the area pointed to by the pointer. A child process is written in the form of a subroutine on the instruction ROM, and when processing is completed,
The second processor section resumes the operation of the child process starter constituted by processing block 51 and branch 52 in FIG. The first child process starter 21 in FIG.
As can be seen from the fact that the second child process starter 22 is placed equally with the second child process starter 22, the third processor section also has the child process startup routine shown in FIG. In addition, the first to fourth areas of the reservation table 40 Reservation pointer 8. Execution pointer 9 is cleared in the microprocessor's initialization routine.

In this way, in the parallel processing processor shown in FIG. 1, the processing of the child process is entrusted from the first processor section to the second processor section via the reservation table 40, so that the processing order of the processes is impaired. There is no fear.

By the way, when a child process entrusted by a first processor is executed by multiple processors arranged equally, processor contention may occur, and the same child process is executed by different processors. There is a risk that the overall processing efficiency will deteriorate due to overlapping processing that is executed simultaneously.

The device includes a process distributor 23 that suppresses the operation of the other child process starter while one of the first child process starter 21 and the second child process starter 22 is in operation. The operation of the child process management mechanism shown in FIG.
This will be explained with reference to the configuration diagram of the reservation table shown in FIG. 6 and the flowchart shown in FIG.

FIG. 6 shows the detailed structure of the reservation table 40 in FIG. 5. Four areas from address 0 to address 3 on the 16-bit memory are allocated as a reservation table for the child process, are the reservation pointer 8 and the execution pointer 9, the first starter flag 21a set by the first child process starter 21 during the reservation table search period, and the second child process starter 22 during the reservation table search period. This flag is assigned as the second starter flag 22a, which is set within the flag. Furthermore, the MSBs of the first to fourth areas of the reservation table 40 are used as reservation flags, which are set when the first processor entrusts a child process, and the second processor starts executing the child process. It will be reset at the time when On the other hand, the remaining 15 bits in each of the first to fourth areas store the start address of the child process.

On the other hand, the second processor section performs operations based on the flowchart shown in FIG. As shown in branch 71 and processing block 72, the contents of the second starter flag set by the third processor section are checked, and if set, the program waits until it is reset. If it has been reset, the first starter flag is set and processing is transferred to the child process starter.

When the child process starter completes its processing, it resets the first starter flag as shown in processing block 73. In FIG. 7, branch 71 and processing block 72 constitute one of the two AND gates of process distributor 23 of FIG. 5, that is, one half of process distributor 23. In FIG.

The third processor section also performs the same operation as in the flowchart shown in FIG.

In this way, the normal %qr row E1. shown in FIG.
'7 includes a program storage means, a memory having a plurality of addresses and whose contents are readable and writable, a data bus coupling between the memory and the program storage means, and a first memory that shares at least the memory. Second. a third processor; a table forming means for storing start address information of a child process on the memory by the first processor to form a reservation table 40; and start address information stored in the child process reservation table 40. Search for the child process in the second . The first command executed by the third processor. Second child process starter 21.2
2, and a process distributor 23 that suppresses the operation of the other child process starter while one child process starter is operating, and since the process distributor 23 suppresses competition between child processors, there is no synchronization between processes. Sexuality increases.

At the start of operation, the initialization block 24 is configured to provide the process distributor 23 with a pseudo signal indicating that the first child process starter 21 is in operation.

Specifically, as shown in the flowchart shown in Figure 9,
In the initialization routine of the first processor, the first starter flag 21a shown in FIG. 6 is set (processing block 91) and the second starter flag 22a is reset (processing block 92). Thereby, the process distributor 23 operates so that the first child process delegated from the first processor is executed by the second processor with priority. In addition, in the flowchart of FIG. 9, when the processing of the initialization block is completed, the first processor detects an event change (boo 77 chi 93).
Then, the child process reservation processing (processing block 94) as described above continues.

In each of the embodiments of the present invention described above, an example is shown in which three types of processor units are provided, but it goes without saying that the present invention is also applicable to cases in which four or more types of processor units are included.

Effects of the Invention As is clear from the above description, the parallel processing processor of the present invention includes a program storage means (instruction ROM 100) and a first ROM for sequentially selecting instructions stored in the program storage means. Second. a third instruction selection means (first to third programmable counters 1 to 3); a memory (RAM) having a plurality of addresses and whose contents can be read and written;
200), a data bus 30 coupling between the memory and the program storage means, and the first . Second. a context controller 7 that sequentially allocates execution cycles of the instructions selected by the third instruction selection means; and a reservation table for storing start address information of child processes in the memory according to the instructions via the first instruction selection means. 40, and a table forming means (reservation pointer 8) that searches the start address information stored in the reservation table according to an instruction via the second or third instruction selection means and executes the child process. 1 and the second child process starter (child process starter 21.22)
Since it is equipped with a program storage means (instruction ROM 100) and a memory IJ (RAM 20) which has multiple addresses and whose contents can be read and written, there is no fear that the processing order of the process will be impaired.
0), a data bus 30 coupling between the memory and the program storage means, and a first .0) that shares at least the memory. Second. a third processor (consisting mainly of the first to third programmable counters 1 to 3 and a group of instructions taken out by these); and the first processor stores start address information of a child process on the memory. table forming means (reservation pointer 8) that stores the reservation table 40 by storing the reservation table 40, and retrieves the start address information stored in the reservation table to set the child process to the second. The first command executed by the third processor. Second child process starter (child process starter 2L)
22), and a process distributor 2 that suppresses the operation of one child process starter while the other child process starter is operating.
3, it is possible to improve the synchronization between processes more than before.

00), a memory (RAM 200) having a plurality of addresses and whose contents can be read and written, and a data bus 3 connecting the memory and the program storage means.
0 and the first .0 sharing at least the memory. Second. a third processor; table forming means (reservation pointer 8) for storing start address information of child processes on the memory by the first processor to form a reservation table 40; The address information is searched to locate the child process in the second. The first command executed by the third processor. a second child process starter (child process starter 21, 22), a process distributor 23 that suppresses the operation of the other child process starter while one of the child process starters is in operation; , an initialization means initialization block 24 for providing a pseudo signal to the process distributor indicating that the first child process starter is in operation, so that the first processor section is configured to provide a pseudo signal indicating that the first child process starter is in operation. One of the processor units of the third processor unit can be entrusted with the initial processing preferentially, and the processing order among the processors can also be determined.

FIG. 2 is a timing chart of the main part of FIG. 1, FIG. 3 is a configuration diagram of a reservation table, FIG. 4 is a border configuration diagram showing the operation of a child process starter,
FIG. 7 is a block diagram of the process distributor and the subsidiary Tsubaki Sobuki, and FIG. 9 is a flowchart showing the operation of the first processor.

1... first programmable counter, 2...
2nd programmable counter, 3... Third programmable counter, 7... Context controller, 8... Reserve pointer, 9... Execution pointer, 21... First child process starter, 22 ...first child process starter, 23...
・Process distributor, 24... initialization block,
30...Data bus, 40...Reservation table, 100...Instruction ROM, 200...R
A.M.

Name of agent: Patent attorney Shigetaka Awano Haka18th figure No. figure No. figure 5 Ivy Real f’iza inter 1st baby 0 cess starter V2 child O process starter Bu0 ses minutes &! vessel reservation raul No. figure chest of drawers figure Kuzu 3's buo uramalaruka counter 5 approx. Tokoyuki〆inter 1141 child ot + Fusdata 1! l12Φ child process starter Boot's 9! ni’ vessel First @ le pro 1. the law of nature reservation table No. figure

Claims (3)

[Claims] (1) A program storage means for storing a program consisting of a group of instructions to be executed sequentially; first, second, and third instruction selection means for sequentially selecting instructions stored in the program storage means; and a plurality of addresses. a memory whose contents are readable and writable; a data bus that connects the memory and the program storage means; and a data bus that connects the memory and the program storage means; a context controller for allocating sequentially; a table forming means for storing start address information of a child process on the memory according to an instruction via the first instruction selecting means to form a reservation table; A parallel processing processor comprising first and second child process starters that execute a child process by searching start address information stored in the reservation table according to an instruction via an instruction selection means. (2) a program storage means for storing a program consisting of a group of instructions to be executed sequentially; a memory having a plurality of addresses and whose contents can be read and written; and a data bus connecting the memory and the program storage means; , first, second, and third processors that share at least the memory; table forming means for storing start address information of a child process on the memory by the first processor to form a reservation table; first and second child process starters that search for start address information stored in a reservation table and cause the second and third processors to execute the child processes; and when one of the child process starters is running, the other child process starter A parallel processing processor comprising a process distributor that suppresses the operation of a process starter. (3) Claim 2, further comprising initialization means for supplying a pseudo signal to the process distributor when the first processor starts operating, indicating that the first child process starter is in operation.
Parallel processing processor as described.