JPH04247748A - Hdb3 code decoder - Google Patents

Abstract

PURPOSE:To surely decode simultaneously inputted signals to noninverting and inverting terminals with respect to a decoder decoding the input signal into an NRZ signal through the use of a specific code rule signal. CONSTITUTION:A shift register means 1 latches a noninverting signal and an inverting signal and shifts them by 4 bits. A polarity monitor signal receives the noninverting signal and the inverting signal to monitor the polarity of the input signals just after the simultaneous input, and an error pulse erasure means 3 receives an output of a polarity monitor means 2 and an output of a polarity comparison monitor means 7 and identifies which of the noninverting signal and the inverting signal is an error pulse at the simultaneous input of the signals and deletes the error pulse. Moreover, the polarity comparison monitor means 7 receives a bipolar rule signal from a bipolar rule identification section 4 and a signal of the polarity of a violation code to compare and monitor the polarity. Thus, an NRZ signal is obtained by comparing an output of a bipolar signal shift section 5 shifting the bipolar rule signal of the bipolar rule identification section 4 with a signal representing the position of the violation code outputted from the violation polarity identification section 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder for decoding a signal generated by encoding an NRZ signal using a specific coding rule.

0002

2. Description of the Related Art In PCM transmission, a decoder that is compatible with the coding rules used is required, and one example of such a decoder is an HDB3 code decoder. This HDB3 code decoder encodes the original signal of 4 consecutive '0's and generates 4 consecutive '0's.
' with a certain pattern of '1001' or '0001'
Convert it to and insert it into the positive side signal or negative side signal. Note that '1001' is 'B00V', and '0001' is '0'.
00V', B is a bipolar law code with a value of '1' (hereinafter referred to as code B), and V is a violation code with a value of '1' (hereinafter referred to as code V).
In the HDB3 code, as shown in FIGS. 5(A) to 5(C), if the preceding code V0 and the original signal '1' immediately before four consecutive '0's, that is, the signal B1, have the same polarity, the preceding code V0
'B2 00V2' for the positive side of the different polarity side of 0
Insert. Furthermore, as shown in FIGS. 5(D) to (F), if the preceding code V0 and signal B1 have different polarities, the preceding code V0
Insert '000V2' to the opposite polarity side. Below, the conventional decoder shown in FIG. 6 will be explained using FIGS. 7 and 8 together.

If the NRZ signal shown in FIG. 7(a) is the original signal, the clock and H signals shown in FIG. 7(b) to (d) are
The positive side signal and the negative side signal converted according to the DB3 code rule are input to a flip-flop circuit (hereinafter referred to as FF) 41 and an FF 42 and held therein. The outputs of FF41 and FF42 are the AND of the logical products that constitute the bipolar rule identification section 4.
OR gate 23c of logical sum with gates 23a and 23b
The output signal (e) from the selector 23 is input to the J input and K input of the J-KFF26.
is input, so every time the output signal (e) becomes '1', the output (h) of J-KFF26 and the output (h)
The output (h') (not shown in FIG. 7) having the opposite polarity is toggled and applied to the selector 23. Therefore, in the selector 23, the positive side signal and the negative side signal are taken out alternately, and a signal (bipolar law signal) (e) according to the bipolar law is obtained as an output. On the other hand, the output of FF41 is input to the AND gate 24, and the output from FF42 is input to the AND gate 25.
The D gate 24 outputs a signal that violates the bipolar rule on the positive side (bipolar rule violation signal), that is, a bipolar rule violation signal (f) consisting of the positive side sign V and the error pulse E. Similarly, the AND gate 25 outputs a negative bipolar rule violation signal (g). That is, the bipolar identification unit 4 outputs a bipolar rule signal and a bipolar rule violation signal obtained by removing the original signal and bipolar code B from the positive side signal and the negative side signal.

[0004] FFs 27 to 30 are a bipolar signal shift section 5, and each FF 27, 28, 29,
30, shift by 1 bit each, and FF28
Inverted output (j) from FF29, inverted output (k) from FF29
, the output (l) is output from the FF30. A signal (f
), and a signal (g) is added to the K input, and depending on the polarity of the sign V of this signal (g), J-KFF3
The polarity of the output (m) of 1 changes. Also, FF32 is J
-The polarity information of KFF31 is shifted by 1 bit and held. The exclusive OR (hereinafter referred to as EOR) of the output (n) of the FF32 and the output (m) of the J-KFF31 is expressed as E
The output of the EOR gate 33 (O
) as the polarity identification code V that erases the error pulse E.
1, outputs V2. That is, the symbols V1 and V2 in the positive side signal (c) and the negative side signal (d) are focused on the fact that the positive side and the negative side always alternate, and the preceding error pulse E that violates the bipolar rule is erased.

Next, NAN of the NAND of the signal decoding unit 7
The D gate 34 has the inverted output (j) of FF28, 29,
Three signals are input: (k) and the output (o) of the EOR gate 33, and when the EOR gate 33 outputs the code V1, the inverted output (j) of the FF 28 becomes '1', and then outputs V2. When is the inverted output of FF29 (k)
becomes '1', and therefore the output of the NAND gate 34 becomes the signal (p). When this signal (p) and the output (l) of the FF 30 are input to the AND gate 35 and a logical product is taken, by erasing B2 at the V2 position of the output (p) of the NAND gate 34, the same signal as the original signal is obtained. Obtain the decoded signal (q). This decoded signal (q) is clocked by the FF 32 and an NRZ decoded signal is sent out.

As shown in FIG. 7 above, for example, if the error pulse E added at timing ■ is at the same position as the '1' of the original signal and is added to the negative side of a different polarity, that is, if the error pulse E is added at timing ■. When the positive and negative sides become '1' at the same time due to the error pulse E, even if the positive and negative sides become '1' at the same time due to the error pulse E, the symbol V2 of the preceding timing ■ is on the negative side, and the simultaneous Since the polarity of the signal at the position of timing ■ immediately before input is negative, it is clear from the nature of the HDB3 code as shown in Figure 5 that the signal on the negative side of the simultaneous input is the error pulse E, and it is accurate. can be decrypted. In other words, if the number of signals existing between the code V2 of the preceding timing ■ and the error pulse E of the timing ■ becomes an even number, then
This conventional circuit can perform decoding.

However, as shown in FIG. 8, the sign V2 at the preceding timing ■ is on the negative side, and the polarity of the signal at the position of the timing ■ immediately before being simultaneously input is on the positive side. If the polarity of the signal at the position of the timing ■ immediately before the symbol V2 in ■ is input simultaneously is different, it is difficult to distinguish which polarity of the signal is the error pulse E when input simultaneously. Not stick. For example, the signal (c) on the positive side in FIG.
Comparing the signal (d) on the negative side and the signal (d) on the negative side, it is found that the input signals are exactly the same signal pulse until they are input simultaneously, and at this time, which polarity of the signal should be identified as the error pulse E and erased. I can't decide. For this reason, in the decoded signal (q), data is erased or data is added by codes V1 and V2. In other words, if the number of signals existing between the code V2 of the preceding timing (2) and the error pulse E of the timing (2) is an odd number, the conventional circuit cannot perform normal decoding.

[0008]

As described above, when the polarity of the preceding code V and the signal immediately before simultaneous input are different in polarity, there is a problem that the inserted error pulse cannot be identified and cannot be erased. The present invention aims to provide an HDB3 code decoder that can accurately decode by adding a function to identify and erase which pulse is an error pulse when signals are input to the positive and negative sides at the same time. purpose.

[0009]

[Means for Solving the Problems] In order to achieve the above object, in the present invention, the original signal is a four consecutive '0' signal from among the positive side signal and the negative side signal encoded according to the HDB3 coding rule. Shift register means 1 for shifting the bipolar signals by 4 bits, and polarity monitoring means for monitoring the polarity immediately after the simultaneous input of the bipolar signals. 2, an error pulse erasing means 3 which inputs the outputs of the polarity monitoring means 2 and the polarity comparison monitoring means 7 and erases error pulses in the simultaneous input signal, and a bipolar law signal from the bipolar law identification section 4. A polarity comparison monitoring means 7 is provided to monitor whether the polarity of the code is the same as the polarity of the preceding violation code from the violation polarity identification unit 6, and when the signals are input simultaneously, which side of the signal is an error pulse. The configuration is such that the signal can be identified and erased, and decoded into the original signal in the signal decoding section 8.

0010

[Operation] In the present invention, as shown in FIG. 1, the shift register means 1 holds the input positive and negative signals and performs a 4-bit shift, and the polarity monitoring means 2 holds the input positive and negative signals. The polarity of the input signal is monitored immediately after the signals are input simultaneously, and the error pulse erasing means 3 inputs the output of the polarity monitoring means 2 and the output of the polarity comparison monitoring means 7. When a signal on the positive side or the negative side is an error pulse, it is identified and erased, and the bipolar law signal from the bipolar law identification unit 4 and the signal of the polarity of the violation code are inputted to determine the polarity. A polarity comparison monitoring means 7 for carrying out comparison monitoring is provided.

Therefore, by comparing the output of the bipolar signal shifter 5 which has shifted the bipolar law signal of the bipolar law identifier 4 with the signal indicating the position of the violation code outputted by the violation polarity detector 6, NRZ signal can be obtained.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS The circuit shown in FIG. 2 will be explained below with reference to FIGS. 3 and 4. Note that (a) to (y) in Figures 3 and 4 refer to Figure 2.
This is the signal waveform at the position shown in . Shift register section 1
1 is a circuit corresponding to the shift register means 1, which includes 5 series FF11a to FF11e and 5 series FF11f.
~FF11j are formed, and if the NRZ signal shown in Fig. 3 is the original signal (a), the clock (b), the positive side signal (c), and the negative side signal (
d) input.

The polarity monitoring means 2 to which signals are simultaneously input consists of AND gates 12, 13, 14 for logical products, J-KFFs 15, 16 for alternating flip-flop operations, and N for negative logical sums.
It is composed of an OR gate 17. Positive side signal (c)
At timing ⑥ when the negative side signal (d) and the negative side signal (d) are simultaneously input, the output signal (e) of the AND gate 12 becomes '1', and the output (f) of the J-KFFs 15 and 16 becomes '1'.
, (g) both become '0' and the NOR gate 17 becomes '
It becomes 1'. Therefore, since the inputs on one side of AND gates 13 and 14 are both '1', if the next input signal is the positive side, the signal (f) of J-KFF15 will be '1'.
And if it is on the negative side, the output of J-KFF16 (g)
becomes '1'. Therefore, the polarity of the signal immediately after the signals are simultaneously input is revealed by the output signals (f) and (g) of J-KFF15 and 16, and this polarity monitoring information is transmitted to J-KFF15 and J-KFF16.
They are held in KFF15 and KFF16, respectively.

The error pulse erasing means 3 is an AND
It is composed of D gates 18, 21, 22 and NAND gates 19, 20 for negative AND. AND gate 18
The output (h) of FF11e is when the signals are simultaneously input.
, the output from FF11j becomes '1', and the NAN
In the D gates 19 and 20, the output of the AND gate 18 (h
) and the polarity of the preceding sign V at timing ■ and the polarity of the signals at subsequent timings ■ to ■ ENOR gate 3
Three signals are input: the feedback output (r) from J-KFF 4 and one of the outputs (f) and (g) of J-KFF 15 and 16. In other words, when signals are input simultaneously, NAND gate 1
Since either output (i) or (j) of 9 or 20 outputs '0', error pulse E can be erased by AND gate 21 or AND gate 22. In other words, the method for determining which polarity of the signal to erase when signals are simultaneously input is that when the polarity of the preceding code V and the signal immediately before the signal is simultaneously input are of different polarities, immediately after the signal is simultaneously input. If the signal is on the positive polarity side, the simultaneously input error pulse E signal on the positive polarity side is erased, and if the signal immediately after the signal is simultaneously input is on the negative polarity side, the simultaneously input error pulse E signal on the negative polarity side is erased. Erase.

As in the conventional example, the bipolar rule identification unit 4
A selector 23 consisting of ND gates 23a, 23b and an OR gate 23c, AND gates 24, 25, and J-
Consists of KFF26. When the selector 23 outputs a signal (m) that becomes '1', the J-KFF 26 toggles with the signal (m) and selects a signal with the opposite polarity for the next signal, so the signal (m) is a signal that follows the bipolar rule. is obtained. The signal (p) from J-KFF26 is '0' if the selected bipolar law signal is the positive side signal.
, if it is a negative side signal, it becomes '1'.

On the other hand, from the AND gates 24 and 25,
(n) and (0) as bipolar rule violation signals (sign V and error pulse E) on the positive and negative sides, respectively
get. The bipolar signal shift section 5 includes FFs 27, 28,
29 and 30, and the violation polarity identifying section 6 is composed of a J-KFF 31, an FF 32, and an EOR gate 33.

The positive side signal (n) that violates the bipolar rule from the AND gate 24 and the negative side signal (o) that violates the bipolar rule from the AND gate 25 are connected to J-KFF3.
1 to the J input and K input respectively. J-KF
The output signal (q) of F31 is output and held as '1' if the input code V is on the positive side, and '0' if it is on the negative side. The polarity comparison/monitoring means 7 between the sign V of the preceding timing (2) and the following signal is constituted by an ENOR gate 34 of a negative logical sum. When the output (p) indicating the polarity of the bipolar law signal from J-KFF 26 and the output (q) indicating the polarity of the preceding sign V from J-KFF 31 are input to the ENOR gate 34, the output (r
) is '0' if the polarity is the same, and '1' if the polarity is different.
becomes.

The signal decoding section 8 is composed of a NAND gate 35 and an AND gate 36 as in the conventional example. When the output (s) of the EOR gate 33 is '1', it is an output indicating the code V with the error pulse E erased. This output (s)
The three signals, the inverted output (u) of FF28 and the inverted output (v) of FF29, are added to the NAND gate 35 to obtain a NAND signal (x).
and the output (w) of the FF 30 are added to the AND gate 36 for decoding. Then, the NR decoded in FF37
It holds the Z signal for only one clock and outputs it.

When comparing FIGS. 3 and 4 with FIGS. 8 and 9,
The decoder of FIG. 2 is shown to be accurately decoding the original signal. FIG. 3 shows an example in which a signal on the positive side is regarded as an error pulse E and decoded when signals are simultaneously input, and FIG. 4 shows an example in which a signal on the negative side is regarded as an error pulse E and decoded.

[0020]

As described above, according to the present invention, even if '1' is input to the positive side signal and the negative side signal at the same time due to the error pulse, it is possible to always accurately decode the signal. The problem of deterioration can be solved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 3 is a diagram showing a first time chart of a circuit according to an embodiment of the present invention.

FIG. 4 is a diagram showing a second time chart of a circuit according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram of HDB3 code.

FIG. 6 is a diagram showing a circuit configuration of a conventional example.

FIG. 7 is a diagram showing a first time chart of a conventional example circuit.

FIG. 8 is a diagram showing a second time chart of the conventional example circuit.

[Explanation of symbols]

1 is shift register means 2 is polarity monitoring means 3 is error pulse erasing means 4 is the bipolar rule identification part 5 is a bipolar signal shift section 6 is violation polarity identification section 7 is polarity comparison monitoring means 8 is a signal decoding section

Claims (1)

[Claims] [Claim 1] The original signal consists of four consecutive '0's from among the positive side signal and negative side signal encoded according to the HDB3 coding rule.
In a device that monitors and decodes a specific pattern encoded when present in a signal, the shift register means (1) shifts the bipolar signals by 4 bits, and monitors the polarity immediately after simultaneous input of the bipolar signals. Polarity monitoring means (2)
, the polarity monitoring means (2), and the polarity comparison monitoring means (7)
an error pulse erasing means (3) for erasing error pulses in the simultaneous input signal; ) is provided to monitor whether the polarity of the preceding violation code is the same as that of the previous violation code (7), and to identify which side of the signal is an error pulse when signals are input simultaneously. An HDB3 code decoder characterized in that the signal can be erased and decoded into an original signal in a signal decoding section (8).