JPH04249493A - Digital convergence device - Google Patents

Abstract

PURPOSE:To smoothly correct by storing various correction pattern data in response to color slurring correction by a level required for the correction, selectively synthesizing the correction pattern and the correction level so as to form a convergence correction signal. CONSTITUTION:An output memory 1 stores a correction data on an adjustment point and the address is set by an address bus 2. At data read, an address encoder 7 generates a read address for a correction data based on horizontal and vertical reference signals inputted from a synchronizing signal input terminal 6 and a read address is obtained via a changeover circuit 4. In this case, an input B is selected by adding an address selection signal S to the circuit 4 to select an input B. A convergence correction data is required for all scanning lines between adjustment points and an interpolation circuit 6 generates an interpolation data including a vertical data from an adjacent adjustment point correction data. An LPF 18 implements the interpolation of a horizontal direction data by using the interpolation data and the result is outputted as a convergence correction signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence device for correcting color shift in a cathode ray tube type color receiver.

0002

2. Description of the Related Art FIG. 7 shows the configuration of a conventional digital convergence device disclosed, for example, in Japanese Patent Application Laid-open No. 61-78294, in which 1 is an output memory for storing convergence correction data, 2 is an address bus, and 3 is a convergence device. data bus, 4
5 is an address bus switching circuit, 5 is a data bus switching circuit, and 6 is an address bus switching circuit.
1 is an input terminal for a synchronization signal that defines the scanning timing, 7 is an address encoder that generates a read address for correction data, 8 is a CPU, 9 is an interface between the CPU 8 and the keyboard 10, 16 is an interpolation circuit for correction output data, and 17 is an A /D converter, 18 is a low-pass filter, 19 is a convergence correction output terminal, 21 to 28 are data ROMs that store pattern data of correction patterns for rough adjustment, 34 and 37 are interfaces, and 35 is a test signal generation circuit. , 38 is a cursor signal generation circuit, 36 is a mixing circuit, and 39 is a video signal output terminal.

Next, the operation of the conventional device having the above configuration will be explained. Output memory 1 that stores convergence correction data
has addresses corresponding to grid-like adjustment points in one screen. This address is generated by the address encoder 7 according to the timing defined by the synchronization signal input from the input terminal 6, and becomes the address of the memory 1 via the switching circuit 4. The data designated by this address is input to the interpolation circuit 16 via the switching circuit 5, where vertical data interpolation is performed, converted to an analog signal by the D/A converter 17, and smoothed by the low-pass filter 18. , and is supplied as a convergence correction signal from the output terminal 19 to an electromagnetic change means for convergence correction via an amplification stage (not shown).

Next, the operation of creating rough adjustment data in the above-described conventional apparatus will be explained. Data ROM21~
28 stores data for performing pin correction on the left half of the screen, as shown in FIG. 8A, for example, and the adjuster controls the adjustment level using the keyboard 10. FIG. 8(b) shows this situation three-dimensionally. Also, since the above data is standardized data,
The CPU 8 multiplies the called correction pattern by a predetermined coefficient set by the adjuster to calculate correction data for the adjustment points on the screen. The calculated correction data is combined with other similarly calculated correction data and transferred to the output memory 1. At this time, address bus 2 and data bus 3 are connected to CPU 8 via switching circuits 4 and 5, respectively. In this way, rough adjustment data for digital convergence is created.

[0005]

[Problems to be Solved by the Invention] The conventional digital convergence device is configured as described above, and the CPU
Since the pattern data read from 8 is multiplied by a predetermined coefficient and the correction data is added or subtracted, there is a time delay for calculation between when a key operation is performed for adjustment and when the next key operation is performed. There is a problem in that smooth adjustment cannot be made, and this problem becomes more pronounced as the number of adjustment points increases in order to improve correction accuracy.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a digital convergence device that can perform smooth convergence correction.

[0007]

[Means for Solving the Problems] A digital convergence device according to the present invention includes a plurality of pattern memories that store adjustment point data for each correction level as data for one screen divided into basic correction patterns, and a plurality of pattern memories for each correction level. The apparatus is provided with means for selectively combining the correction patterns and correction levels of the correction data stored in the pattern memory, and an output memory for storing the selectively combined correction data and outputting it as a convergence correction signal.

[0008]

In the present invention, various correction pattern data corresponding to color shift correction are stored in advance at levels necessary for correction, and the correction patterns and correction levels are selectively combined to form a convergence correction signal.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a digital convergence device according to this embodiment, in which 1 is an output memory for storing digital data for convergence correction, 2 is an address bus for controlling the address of the output memory 1, and 4 is an address bus for controlling the address of the output memory 1. An address bus switching circuit that switches the address bus 2 when writing and reading data; 6 is an input terminal for a synchronization signal that defines the screen scanning timing; 7 is a read address that is synchronized with the synchronization signal input from the input terminal 6; 16 is an interpolation circuit that creates convergence correction data for all scanning lines from the data read from the output memory 1, 17 is a D/A converter that converts the digital correction data into an analog signal, and 18 is a horizontal Analog low-pass filter that interpolates between data, 1
9 is an output terminal that outputs a convergence correction analog signal, 61 to 68 are pattern ROMs that store representative patterns for correcting color shift, and 69 to 76 are pattern R, respectively.
A pattern selection circuit selects a pattern with a necessary correction level from the OMs 61 to 68, 85 is a synthesis circuit, 86 is a memory for storing pattern information selected from the pattern ROMs 61 to 68, 60 is a control circuit, and 10 is for performing adjustment operations. keyboard.

Next, the operation will be explained. Adjustment points for digital convergence are set at positions where the screen is divided into a grid as shown in FIG. 2, and data for correcting color shift at each adjustment point is convergence correction data. Therefore, the adjustment point data is read out using addresses synchronized horizontally and vertically on the screen. The output memory 1 stores the correction data on the adjustment points, and its address is set by the address bus 2. When reading data, the address encoder 7 generates a read address for correction data based on the horizontal and vertical reference signals inputted from the synchronization signal input terminal 6, which becomes the read address via the switching circuit 4. At this time, by applying the address selection signal S to the switching circuit 4, the input B side is selected.

As shown in FIG. 4, convergence correction data is necessary on all scanning lines between adjustment points, and therefore, the interpolation circuit 16 extracts vertical interpolation data (interpolation data) from adjacent adjustment point correction data. ). The correction data including this interpolation data is sent to the D/A converter 17.
is converted to analog data by low-pass filter 1.
8 interpolates the horizontal data and outputs it from the output terminal 19 as a convergence correction signal.

Next, the operation of creating correction data in the output memory 1 will be described. The pattern ROMs 61 to 68 have one screen worth of data obtained by decomposing adjustment data into basic correction patterns for various correction levels. The data shown in Figure 5 is of nth order with horizontal and vertical periods (n is an integer from 1 to 4).
The vertical axis represents the correction level. FIG. 3 shows this correction pattern data in more detail, and in this case, the pattern ROM 61
68 is a pattern memory in which data in the horizontal direction changes according to a quadratic function for a correction screen having 5 horizontal adjustment points and 5 vertical adjustment points, and has pattern data of ±4 levels.

The adjuster selects pattern R using the keyboard 10.
An operation for selecting pattern data of OMs 61 to 68 is performed, and signals from the keyboard 10 are sent via a control circuit 60 to control pattern selection circuits 69 to 76 as pattern data selection signals S1 to S8. This pattern selection circuit 69
~76 selects data of various levels from the pattern ROMs 61~68, and the selected data is sent to the synthesis circuit 85.
are synthesized and written to the output memory 1. This data writing is performed during the vertical blanking period of screen scanning in order to avoid affecting the screen display. At this time, the switching circuit 4 selects the address on the input A side in response to the address selection signal S, and this address is generated by the control circuit 60.

As described above, pattern ROM61~
Since the data selected from 68 is written to the output memory 1, smooth adjustment can be performed without requiring time such as waiting for calculations during adjustment. When the adjustment is completed, the pattern selection information is written into the non-volatile memory 86, and by reading this data, it is possible to synthesize the correction data, and there is no need to readjust the convergence.

In the above embodiment, the pattern selection circuits 69 to 76, the synthesis circuit 85, and the control circuit 60 are configured as independent hardware, but it is also possible to replace these with a one-chip microcomputer. Functions can be realized by software. The configuration in this case is shown in FIG. 6. When adjusting the convergence, the adjuster operates the keyboard 10 to select the data in the pattern ROMs 61 to 68. The signal from the keyboard 10 enters the MPU 88, and the MPU 88 inputs data to the pattern ROM 61.
Output the address to select pattern data of ~68,
The pattern data specified by this address is
88. The MPU 88 adds the captured pattern data and then writes it into the output memory 1. Other configurations and operations are similar to those of the first embodiment.

[0016]

[Effects of the Invention] As described above, according to the present invention, digital convergence correction data is created by selectively combining correction patterns for each correction level, so no calculation is required during correction, and convergence correction can be performed smoothly. can be done.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a first embodiment of the device of the present invention.

FIG. 2 is a diagram showing convergence adjustment points on the screen.

FIG. 3 is a diagram showing correction data stored in a pattern ROM according to the present invention.

FIG. 4 is an explanatory diagram of interpolated data.

FIG. 5 is an explanatory diagram of pattern data according to the present invention.

FIG. 6 is a configuration diagram of a second embodiment of the device of the present invention.

FIG. 7 is a configuration diagram of a conventional device.

FIG. 8 is an explanatory diagram of data stored in a conventional data ROM.

[Explanation of symbols] 1 Output memory 10 Keyboard 60 Control circuit 61-68 Pattern ROM 69-76 Pattern selection circuit 85 Synthesis circuit 88 MPU

Claims (1)

[Claims] Claim 1: In a digital convergence device, the points obtained by dividing the screen of a color receiver into a grid are used as adjustment points for convergence correction, and the adjustment point data is provided in a digital convergence device having data for correcting color shift of the receiver for each adjustment point. a plurality of pattern memories for storing each correction level as one screen's worth of data decomposed into basic correction patterns; and means for selecting and combining correction patterns and correction levels of correction data stored in each pattern memory; , a digital convergence device comprising an output memory for storing selectively combined correction data, and performing convergence adjustment based on the output of the output memory.