JPH04250730A - Line control data multiplexer circuit - Google Patents

Abstract

PURPOSE:To control a latch timing of a data to a 2nd buffer and to multiplex a line control data of an input generated from a control section onto a time division multiplex signal without missing by providing a write inhibit control circuit to the multiplexer circuit even when plural ports are employed. CONSTITUTION:The multiplexer circuit is provided with a write inhibit control circuit 2, which prevents missing of the line control data by inhibiting the latch to a 2nd buffer 3 in the write state to the 1st buffer 1 when a line control data to be multiplexed in a multi-frame period timing is latched to the 2nd buffer 3 from the 1st buffer 1 to receive the line control data at first, in the case of the line control data for plural ports inserted to an optional time slot of the time division multiplex signal whose each frame consists of plural time slots and whose plural frames form one multi-frame is inputted at a period being an integral number of multiple of the said frame period and in excess of the multi-frame.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line control data multiplexing circuit, and more particularly to a line control data multiplexing circuit that inputs line control data to be multiplexed into a designated time slot of a time division multiplexed signal, multiplexes the data, and outputs the multiplexed signal. .

0002

2. Description of the Related Art Generally, as shown in FIG. 3, in a time division multiplexed signal, one multiframe set on the time axis as a multiplexed frame is divided into multiple frames, for example, m frames (m is an integer). Configure. In this configuration, each frame (frames 1 to m) consists of a frame first byte F and multiple time slots, and one of these time slots is designated for transmission of line control data, for example, time slots S1 to Sm are designated. are doing. On the other hand, as shown in the lower part of FIG. 3, the line control data to be transmitted has, for example, a 5-bit configuration (A1 to A5 bits in the case of port 1), and the line control data from ports 1 to 4 are asynchronously transmitted. Suppose that it is input at an arbitrary phase. However, if there is a completely asynchronous relationship, there is a risk that content will be lost when multiplexing into a frame of a time division multiplexed signal, so some restrictive conditions are required. Now, the condition is that the signal speed of the line control data generated is sufficiently slower than the amount of transmission information to be multiplexed into the time division multiplex signal, and the signal speed of the line control data generated is V1, the line control data given by the time division multiplex signal. Let the transmission speed of V2 be V1<<V2. That is, in FIG. 3, for time T1 of the 1-bit pulse width of the line control data for port 1, 1 of the multiplexed frame
The bit pulse width time is S/5, and low-speed line data with sufficient margin is multiplexed. Now port 1~
To explain an example of multiplexing up to 3 line data, bits A1 to A5 of port 1 correspond to each time slot S1 to S5 of frames 1 to m (assuming m=5) of the multiplexed frame.
are distributed and inserted. Bits B1 to B5 of port 2 are distributed and inserted into time slots S1 to S5. Thereafter, bits C1 to C5 of port 3 are also assigned to time slot S.
It is distributed and inserted into S1 to S5. Now port 1 to port 3
Each line control data is asynchronous to each other and has a time delay ΔT1,
Multiplexing is possible even if ΔT2 and ΔT3. However, in FIG. 3, if the line control data of port 4 has a further time delay ΔT4, it will not be possible to extract it even if it is attempted to be inserted into time slots S1 to S5.

[0003] Therefore, even if the conventional line control data described above is asynchronous, it is limited to ports 2 and 3 in order to multiplex it with sufficient margin.

The above-mentioned conventional line control data multiplexing circuit includes a MUX 4, which time-division multiplexes a time-division multiplex signal 100, which is a transmission signal, and multiplexed line control data 103, as shown in FIG. A first buffer that inputs and temporarily stores a plurality of line control data of ports 1 to 4 shown in FIG. m-frame pulses MF1, MF in Figure 3
It was composed of a second buffer 3 for reading, writing and temporarily storing line control data in the first buffer 1 at intervals of 2). Here, as mentioned above, when transferring from the first buffer 1 to the second buffer 2, for example, port 4
Only enough line control data was entered to ensure that no line control data was missing.

[0005]

[Problem to be Solved by the Invention] The conventional line control data multiplexing circuit described above is concerned with determining whether a plurality of asynchronous line control data to be multiplexed are multiplexed within a designated time slot of a time division multiplexed signal. Since there is no circuit that monitors the data and prohibits transfer from the first buffer to the second buffer in the event of an overflow, there is a drawback that part of the line control data is not multiplexed and is lost.

[0006]

[Means for Solving the Problems] In the line control data multiplexing circuit of the present invention, each frame is composed of a plurality of time slots, and the plurality of frames constitute one multiframe. When line control data for multiple ports to be inserted is input at an integral multiple of the frame period and at a period exceeding the multi-frame period, the multi-frame period starts from the first buffer into which the line control data is first input. When latching the line control data to be multiplexed at the timing to the second buffer, if writing to the first buffer is in progress, the second buffer
The present invention is characterized in that the loss of the line control data is prevented by prohibiting latching into the buffer.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, the circuit of the present invention includes a first buffer 1, a write inhibit control circuit 2, a second buffer 3 and an M
It is composed of UX4.

Next, this operation will be explained. In order to multiplex it into a time division multiplexed signal, input line control data 101 is taken into the first buffer 1 by a clock A synchronized with the input line control data 101 in the control unit 5. The conditions for input line control data 101 and clock A are the same as those described in the conventional example. In addition, multi-frame pulses MF1, M of the time division multiplexed signal
The relationship between F2 (period m) and one period (period k) of the input multiplex line control data frame pulses KA1 to KD2 is m<
Let it be k. In the conventional example, the data output from the first buffer 1 is latched by the second buffer 3 at m frame pulses 104, but since multiple ports are implemented, one period (k frames) of input line control data ), the time length of the multiplexed line control data for four ports becomes longer than the frame length of the time division multiplexed signal. Here, the write prohibition control circuit 2 controls the write timing using m frame pulses. Specifically, multiplexed data frame pulses KA1 to KD1 are provided at the beginning of each line control data for ports 1 to 4 in FIG. The multiplexed data frame pulse signal 105 shown in FIG.
T1 is counted. When this delay time difference ΔT1 is 0 (see FIG. 3), the time between the start pulse KA1 of the line control data for port 1 and the start pulse KA2 of the next cycle is clearly different from that of the multi-frame pulses MF1 and MF2. Since it is in between, multiplexing is possible. Next, in the case of ports 2 and 3, there is a delay time difference ΔT2, ΔT3, but even if this delay time difference is added, the time until the next start pulse KA2, KB2 is the same as that between multi-frame pulses MF1 and MF2. Therefore, multiplexing is possible. However, in the case of port 4, there is a delay time difference ΔT4 between MF1 and the start pulse KD1 of the line control data, and the time interval between KD1 and KD2 shifts significantly from the time interval between MF1 and MF2, resulting in a time division multiplexed signal. Because the timing does not match, multiplexing is not possible. In such a case, the write prohibition control circuit 2 determines that multiplexing is not possible and starts the next multi-frame pulse M.
F2 is not sent to the second buffer 3. Therefore, if the line control data of the ports scheduled to be multiplexed into one multiframe are, for example, 4 ports, and it is determined that all the line control data of the 4 ports can be multiplexed using the above method, the multiframe pulse MF2 is All the control data for 4 ports is transferred to the second buffer 2. Note that the number of port control data that can be multiplexed into one multiframe is determined by design conditions. If an m-frame pulse is generated while the line control data is being written to the first buffer 1 in this manner, the write prohibition control circuit 2 prohibits latching from the first buffer 1 to the second buffer 3. However, the line control data for port 4 in FIG. 3, which has been once prohibited from being latched, is always latched at the timing of the next m frame pulse and can be taken into the second buffer 3. The latched input line control data 101 is frame-multiplexed into each time slot S1 to S3 of each frame of the time-division multiplexed signal and output.

0010

Effects of the Invention As explained above, in the present invention, even if there are multiple ports, the latch timing of data to the second buffer is controlled by providing a write prohibition control circuit. This has the effect that generated input line control data can be multiplexed into a time division multiplexed signal without any loss.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a line control data multiplexing circuit according to an embodiment of the present invention.

FIG. 2 is a general signal timing diagram illustrating the present embodiment and a conventional example.

FIG. 3 is a block diagram of a conventional line control data multiplexing circuit.

[Explanation of symbols]

1 First buffer 2 Write protection control circuit 3 Second buffer

Claims (2)

[Claims] 1. Each frame is composed of a plurality of time slots, and the line control data for multiple ports is inserted into an arbitrary time slot of a time division multiplexed signal in which the plurality of frames constitute one multiframe. When the line control data is input at an integral multiple of the cycle and at a cycle exceeding the multi-frame cycle, the line control data to be multiplexed at the multi-frame cycle timing is transferred from a first buffer into which the line control data is first input to a second buffer. A line control data multiplexing circuit characterized in that when latching, if writing to the first buffer is in progress, latching to the second buffer is prohibited, thereby preventing loss of the line control data. 2. Inputting a multiplexed data frame pulse for starting line control data for each port from the first buffer and a starting pulse for a multi-frame pulse from the outside,
The delay time difference between these two pulses is compared to determine all the line control data for a plurality of predetermined ports that can be multiplexed within the multiframe, and if it is determined that even one port cannot be multiplexed, the 2. The line control data multiplexing circuit according to claim 1, further comprising a write prohibition control circuit for prohibiting transmission of multi-frame pulses to the second buffer.