JPH0425077A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To prevent a substrate current by employing an SOI(Silicon On Insulator) substrate as a semiconductor substrate for forming a semiconductor nonvolatile memory, i.e., a memory cell array of flash type EEPROM. CONSTITUTION:A thick insulating film 2 is formed on a semiconductor substrate 1 in a flash type EEPROM memory cell, and a P-type semiconductor element region 3 is formed through the film 2. N<+> type source and drain regions 4, 5 are so provided through the film 2 as to hold the region 3 therebetween. Further, a gate insulating film 6 of a thin silicon oxide film 6 is formed on the region 3. A floating gate electrode 7 made of polysilicon is provided through the film 6. Since an SOI substrate is used as the semiconductor substrate, the semiconductor element forming region is electrically independently floated at each memory cell, and hence a substrate current is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to an electrically programmable and erasable semiconductor nonvolatile memory, that is, a flash type EEPROM (Industrial Application Field), which is characterized by electrical bulk erasing.
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[1 Summary of the Invention] The present invention relates to a flash which is an electrically programmable and erasable semiconductor non-volatile memory characterized by electrical bulk erasing using a source or train region on a semiconductor substrate as an erasing region. In type E E PROM, a highly integrated memory cell array is fabricated using SOI (Silicon
The purpose of this is to prevent a large amount of substrate current from flowing during electrical erasing by forming a 7J board (On Inverter) 7J board, thereby realizing a low voltage of the highly integrated Fra-Nocie type EEPROM. .

[Conventional technology]

FIG. 3 is a cross-sectional structural diagram of a memory cell of a straw/cis type EEPROM manufactured using a conventional method. In this memory cell, an active region -1- of a surface portion of a semiconductor substrate 1 made of, for example, a) type Norini 1 is provided with an N' type source region 4. A train region 5 is provided, and a K-edge I pattern 6 of a thin silicon oxide film is formed on the channel region sandwiched between the source region and the train region.

A floating electrode 7 made of polysilicon is provided via a metal insulation film 6.

Further, on this 1-1-tinging gate I/electrode 7, a control gate 1/'1L pole 9 made of polysilicon is provided with a capacitive insulating film 8 interposed therebetween.

[Inventiveness<tl'+i Problem to be solved] Flanonyu type E E P with a memory cell structure as described in L.
In a ROM, a source region or an I-rain region is used as an erase region. However, since the impurity region on the semiconductor substrate is provided under a thin gate insulating film, surface breakdown occurs when a high voltage is applied, and a large amount of substrate current flows. Therefore, when attempting to erase highly integrated memory cells all at once, a large amount of board current is generated, causing the voltage to drop, making it difficult to lower the voltage. .

Furthermore, the booster circuit must be made very large to compensate for the voltage drop, which also hinders memory integration.

Furthermore, since a large amount of substrate current flows, it is difficult to reduce power consumption.

[Failure to solve the problem]

In order to solve the problems described below, in the present invention, an SO+ substrate is used as a semiconductor substrate forming a highly integrated memory cell array of a flash type F, E, I) ROM.

[Effect]

As mentioned above, when an SO1 bulk plate is used as the semiconductor substrate forming the memory cell array of a highly integrated flash EEPROM, the semiconductor element formation region for each memory cell is electrically independent and in a floating state. Current generation is prevented. Therefore, even if highly integrated memory cells are erased all at once, almost no voltage drop occurs, and the voltage of the memory can be reduced. Furthermore, since the booster circuit only needs to be the minimum necessary, the area occupied by the memory can be small, making it easy to achieve high integration. Furthermore, since no substrate current flows, power consumption can be reduced.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings. FIG. 1 shows a flash type T": I" according to the present invention.
: f) It is a cross-sectional structural diagram of a memory cell of ROM.

In this memory cell, a thick insulating film 2 is formed on a semiconductor substrate 1.
A P-type 21 is formed through the insulating film 2.
A F-body element region 3 is formed. The N-type source region 4, sandwiching the cliff conductor element (region 3),
A 1-rain region 5 is provided with the insulating film 2 interposed therebetween. Further, iii. Semiconductor device 11 work 1 area 3-,
A gate insulating film 6 of thin silicon oxide is formed on the surface of the gate electrode. A floating, hard electrode 7 made of polysilicon 7 is provided via this gate insulator 1. Furthermore, capacitive insulation) 8 is added to the flow tube 1 and electrode 7+ by
A contact electrode 9 consisting of 11 contacts is provided.

FIG. 2 shows a planar structural diagram of a memory cell of a furanosive type EEPROM according to the present invention. A feature of the present invention is that since an SOI substrate is used as the semiconductor substrate, the portion that contacts the substrate is electrically floating, which may be inconvenient for memory operations. Therefore, the portion corresponding to the source region of a normal transistor is divided into two parts: the source region and the substrate. In the flash type EEPROM mentioned in the embodiment, the source region is used as an erase region.When injecting electrons into the floating gate I-, the substrate is grounded and When extracting electrons from the semiconductor to the source region, the substrate is turned into an oven to achieve memory operation.

〔Effect of the invention〕

As explained above, the semiconductor non-volatile memory ζ of the present invention uses a Sol substrate as the semiconductor substrate forming the memory cell array of the highly integrated flannel type EEPROM. Because it is electrically independent and in a floating state,
Generation of substrate current is prevented. Therefore, even when highly integrated memory cells are erased all at once, almost no voltage drop occurs, making it possible to reduce the voltage of the memory. In addition, since the field pressure recall can be kept to the minimum required level, the area occupied by the memory can be small, making it easy to achieve high integration.

Furthermore, since no substrate current flows, it was possible to reduce power consumption.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of a memory cell of a flash-type EEPROM according to the present invention, and FIG. 2 is a planar structural diagram of a memory cell of a flash-type IF and E F ROM according to the present invention.
FIG. 3 is a cross-sectional structural diagram of a memory cell of a conventional Frannonyu type EEPROM. ] ・Semiconductor substrate 2 ・Insulating film ・Semiconductor element region 4 ・ ・ 5 ・ 6 ・ 7 ・ 8 ・ ・ 9 ・ ・Source region train region ・Gate insulating film ・Floating gate 1 ・Electrode capacitor insulating film ・Control gate electrode and above Applicant Seiko Electronics Industries Co., Ltd. Agent Patent attorney Takayuki Hayashi

Claims (1)

[Claims] Impurity regions of a first conductivity type are provided near the surface of a semiconductor substrate as source/drain regions at a certain interval, and a first insulating film is formed over the interval, that is, a channel region. A semiconductor nonvolatile memory having a floating gate electrode provided via a second insulating film and a control gate electrode provided on the floating gate electrode via a second insulating film, wherein a semiconductor element forming region of the semiconductor substrate is insulated. A semiconductor substrate provided through a film, the so-called SOI (Silic
1. A semiconductor nonvolatile memory characterized in that it is an onOnInsulator) substrate.