JPH0425242A - Delayed locked loop circuit - Google Patents

Abstract

PURPOSE:To acquire phase synchronization between a PN code and a PNM code in a reception signal at all times by providing an adjustment means on at least one of correlation devices and adjusting the means so that the gain balance between the devices is made identical. CONSTITUTION:This circuit is provided with transformers 16, 17 being adjusting means arranged before and after the band pass filter 7 of a 1st correlation device 3 and similarly with transformers 18, 19 being adjusting means arranged before and after the band pass filter 8 of a 2nd correlation device 4. The adjusting means are used to adjust the 1st and 2nd correlation devices 3, 4 so that the gain balance is made identical. Thus, unbalanced gain between the two correlation devices is avoided and the phase synchronization between a PN code and a PNM code in a reception signal is taken at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION E-INDUSTRIAL APPLICATION FIELD This invention relates to a delay locked loop circuit used for receiving spread spectrum signals.

[Conventional technology]

Figure 3 shows, for example, the Radio Research Institute Quarterly Report, Vol. 25, No. 133 (
FIG. 2 is a block diagram showing a conventional delay-locked loop circuit shown in "Development and Experimental Concept of Multiplexed Digital 5SRA Device" published on pages 133 to 159 of June 1979. In the figure, 1 is an input terminal to which a received signal is input, and 2 is composed of an n-stage feedback shift register, and the n-th stage outputs a first pseudo-noise code signal (hereinafter referred to as PN).
E code) is output, and the corresponding PS is output from the (n-1)th stage.
This is a local pseudo-noise code generator (hereinafter referred to as a local PN code generator) that outputs a second pseudo-noise code signal (hereinafter referred to as a PNL code) whose phase is delayed by one clock from the E code.

3 is the received signal from the input terminal l and the local PN code generator 2
A first correlator 4 correlates the received signal with the PNP code output from the local PN code generator 2, and a second correlator 4 similarly correlates the received signal with the PNL code output from the local PN code generator 2. 5
．． 6 is a multiplier that multiplies the received signal by the PNE code or PNL code, 7.8 is a band pass filter connected to this multiplier 5 or 6, and 9.10 is connected to band pass filter 7 or 8. It is a square law detector.

11 is constituted by an adder, and the first correlator 3
12 is a synthesizing circuit that synthesizes the output of the second correlator 4 and the output of the second correlator 4, and 12 is a loop filter that receives the output of this synthesizing circuit 11 and converts it into a DC voltage signal. The oscillation frequency of the output signal is controlled by the DC voltage signal from the loop filter 12, and the output signal is transmitted to the local P
This is a voltage controlled oscillator (hereinafter referred to as VCO) that inputs to the N code generator 2 and controls the output phase of the local PN code generator 2.

14 is the PNE code output from the local PN code generator 2.
This is a 1/2-bit delay circuit that generates a pseudo-noise code signal (hereinafter referred to as a PNM code) delayed by /2 clocks. Reference numeral 15 denotes a synchronization acquisition circuit that performs synchronization acquisition on the PNM code generated by the 1/2-bit delay circuit 14 and the received signal inputted to the input terminal 1.

Next, the operation will be explained. In spread spectrum communication, first, the PNE code output from the nth stage of the local PN code generator 2 is sent to the 1/2 bit delay circuit 14, and the PNE code is sent to the 1/2 bit delay circuit 14.
Generate NM code. Next, the PNM code is sent to the synchronization acquisition circuit 15, and rough synchronization is achieved by acquiring the synchronization with the received signal from the input terminal 1. After synchronization is acquired in this manner, precise phase synchronization between the received signal and the PNM code is achieved by the delay lock loop circuit.

The operation of this delay locked loop circuit will be explained below. The received signal input from the input terminal 1 is input to the first correlator 3 and the second correlator 4, and the multiplier 5 or 6
is multiplied by the PNE code or PNL code output from the local PN code generator 2. Here, the phase of the PNE code is ahead of the PNM code by 1/2 clock, and the phase of the PNL code is delayed by 1/2 clock. The output of this multiplier 5 or 6 is sent to a square law detector 9 or 10 via a bandpass filter or 8 and is detected.

FIGS. 4(a) and 4(b) show the output characteristics of the square law detectors 9 and 10. In the figure, the vertical axis represents the voltage, and the horizontal axis represents the time deviation from the correct value of the time delay of the pseudo noise code (hereinafter referred to as PN code) included in the received signal. Further, Tc is the clock cycle time of ■C013. As shown in FIGS. 4(a) and 4(b), the output of the square law detector 9 is -T from the point where the phase of the received signal is locked.
The output of the square law detector 10 reaches its maximum at a point delayed by TC/2 from the point where the phase of the received signal is locked.

The outputs of the square law detectors 9 and 10 are input to a combining circuit 11,
The output of the square-law detector 9 is phase-inverted, and the output is summed with the output of the wave multiplier 10 to be synthesized. Therefore, from this synthesis circuit 11, an S-shaped output characteristic as shown in FIG. 4(c) is obtained.

The output signal of this synthesis circuit 11 is supplied to a VCO 13 via a loop filter 12. The oscillation frequency of this ■C013 is controlled by the DC voltage signal output from the loop filter 12, and the output signal of ■C013 is local PN
The signal is input to the code generator 2. That is, the PNE code and the PNL code output from the local PN code generator 2 are correlated with the received signal at phases corresponding to the oscillation frequency l of the VCO 13, and these two signals output from the combining circuit 11 are The phase of the PN code of the received signal is driven so that the difference between the two correlation outputs becomes "'o", that is, the stable point shown in FIG. 2(c).

When the output of the synthesis circuit 11 becomes "0", the PN code of the received signal and the P output from the local PN code generator 2 are
This means that phase synchronization with the NM code has been achieved.

Here, if the gain balance between the first correlator 3 and the second correlator 4 collapses, a certain offset voltage will appear in the output of the combining circuit 11, causing a problem that will have a negative impact on synchronization establishment. do. This point will be explained below using a specific example.

The input/output characteristics of the multiplier 5, band-pass filter 7, and square-law detector 9 that make up the first correlator 3 are the same as those of the multiplier 6, band-pass filter 8, and square-law detector 1 that make up the second correlator 4.
If it is worse than the human output characteristic of 0, then the square law detector 9
．． The peak levels output from lO are shown in Figure 5 (
a), (b). From this, the square law detector 9
It can be seen that the peak level output from the square law detector 10 is smaller than the peak level output from the square law detector 10.

A synthesis circuit 11 that synthesizes the outputs of the square law detectors 9 and 10.
The output waveform of is shown in FIG. 5(c). Therefore, the PN code of the received signal and the P
At the point where the time difference is "0" where the phase synchronization with the NM code is completely matched, it will not be "'0", and the output of the synthesis circuit Ill will be 0°.
At this point, the phase synchronization between the PN code and PNM code of the received signal is not achieved.

[Problem to be solved by the invention]

Since the conventional delay-locked loop circuit is configured as described above, if the gain balance between the first correlator 3 and the second correlator 4 is lost, the PN code of the received signal and the local There was a problem in that it became difficult to establish phase synchronization of the PNM code from the PN code generator 2.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a delay locked loop circuit that can always maintain phase synchronization between a PN code and a PNM code of a received signal.

[Means to solve the problem]

In the delay locked loop circuit according to the present invention, at least one of the first and second correlators is provided with adjustment means for adjusting the gain balance between the two correlators to be the same.

[For production]

The adjustment means in this invention prevents the gain balance from being lost between the two correlators by adjusting the gain balance between the first correlator and the second correlator to be the same. , to realize a delay lock loop circuit that can always achieve phase synchronization between the PN code and the PNM code of a received signal.

(Example) Hereinafter, an example of the present invention will be explained with reference to the drawings.
In the figure, 1 is an input terminal, 2 is a local PN code generator,
3 is a first correlator, 4 is a second correlator, 5.6 is a multiplier, 7.8 is a band pass filter, 9.10 is a square law detector, 11 is a synthesis circuit, 12 is a loop filter, 13 is■C
0114 is a 1/2-bit delay circuit, and 15 is a synchronization acquisition circuit, which are the same or equivalent parts as those in the conventional circuit denoted by the same reference numerals in FIG. 3, and detailed explanation thereof will be omitted.

Further, 16.17 is a transformer as an adjustment means arranged before and after the bandpass filter of the first correlator 3, and 18.19 is a transformer as an adjustment means arranged before and after the bandpass filter 8 of the second correlator 4. This is a transformer as an adjustment means placed before and after the

Next, the operation will be explained. In order to make the explanation easier to understand, we will make the following assumptions.

That is, in the first correlator 3, the gain of the square law detector 9 is smaller than the gain of the square law detector 1o of the second correlator 4, and the input/output impedance of the bandpass filter is equal to that of the multiplier 5 and the square law detector 9. Assume that impedance matching is not achieved. However, even without these assumptions, the effects of this embodiment are not affected in any way.

Now, the output characteristics of the square law detector 9.10 without the transformers 16, 17, 18, and 19 are shown in FIG. 2(a).

In the case of (b), a certain offset voltage appears in the output of the combining circuit 11. Therefore, an attempt is made to insert transformers 16.17 before and after the band-pass filter and adjust the transformers 16.17 to make the output peak level of the square-law detector 9 the same as the output characteristics of the square-law detector 1o. , in this case they are not the same, and the square law detector 1 is still
less than the output peak level of 0. The output characteristics of the square law detector 9 at this time are shown in FIG. 2(c).

Therefore, transformers 18 are also installed before and after the bandpass filter 8.
．． 19, adjust this transformer 18.19,
The output peak level of the square law detector 10 is lowered to match the adjusted output peak level of the square law detector 9. The output characteristics of the square law detector 10 at this time are shown in FIG. 2(d). This makes it possible to make the output characteristics of the square law detectors 9 and 10 the same. At this time, the output characteristic of the combining circuit 11 becomes as shown in FIG.
Phase synchronization with the PNM code output from the N code generator 2 is achieved.

[Effects of the Invention] As described above, according to the present invention, the adjustment means is arranged in at least one of the first correlator and the second correlator, and the gain balance between the two is adjusted so as to be the same. With this configuration, there is no loss of gain balance between the two correlators, and a delay lock loop circuit that can always maintain phase synchronization between the PN code and PNM code of the received signal can be obtained. .

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a delay locked loop circuit according to an embodiment of the present invention, Fig. 2 is a characteristic diagram for explaining its operation, and Fig. 3 is a conventional delay locked loop circuit. A block diagram showing the circuit, and FIGS. 4 and 5 are characteristic diagrams for explaining its operation. 2 is a local PN code generator, 3 is a first correlator, 4 is a second
11 is a synthesis circuit, 12 is a loop filter, 1
3 is a VCo, and 16 to 19 are adjustment means (transformers). In addition, in the figures, the same reference numerals indicate the same or equivalent parts. (2 others)

Claims (1)

[Claims] a local pseudo-noise code generator that generates a first pseudo-noise code signal and a second pseudo-noise code signal whose phase lags that of the first pseudo-noise code signal; A first correlator that takes a correlation with the first pseudo-noise code signal that is output, and a first correlator that takes a correlation between the received signal and the second pseudo-noise code signal that is output from the local pseudo-noise code generator. a second correlator that combines the output of the first correlator and the second correlator, a loop filter that converts the output of the synthesis circuit into a DC voltage signal, a voltage-controlled oscillator whose oscillation frequency is controlled by a DC voltage signal from a loop filter, the output phase of the local pseudo-noise code generator is controlled by the output of the voltage-controlled oscillator, and the output phase of the local pseudo-noise code generator is controlled by the received signal and the local pseudo-noise. In a delay locked loop circuit that performs synchronized tracking with a code, adjusting means for adjusting a gain balance between the first correlator and the second correlator in at least one of the first and second correlators. A delay-locked loop circuit characterized by having.